Patent application number | Description | Published |
20090119451 | Redriven/Retimed Registered Dual Inline Memory Module - A memory module may include a plurality of dynamic random access memory (DRAM) chips, each of which may have one or more data input/output (D/Q) terminals. The memory module may include data redriving/retiming circuits connected to the D/Q terminals of the plurality of DRAM chips. The data redriving/retiming circuits may provide isolation between a system memory bus and the D/Q terminals of the DRAM chips. | 05-07-2009 |
20090300439 | Method and Apparatus for Testing Write-Only Registers - There is disclosed a test circuit for testing an integrated circuit containing at least one write-only register and providing at least one output signal through at least one output pin. The test circuit may include a test mode decoder circuit to enable a test mode and a data selector circuit to select at least a portion of data stored in the at least one write-only register as test data. The test data may be output from the integrated circuit through the at least one output pin. | 12-03-2009 |
20120260024 | MEMORY BUFFER WITH ONE OR MORE AUXILIARY INTERFACES - The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The additional interfaces may include, for example, a SATA interface, an Ethernet interface, an optical interface, and/or a radio interface. | 10-11-2012 |
20120266041 | SYSTEMS AND METHODS FOR ERROR DETECTION AND CORRECTION IN A MEMORY MODULE WHICH INCLUDES A MEMORY BUFFER - The present systems include a memory module containing a plurality of RAM chips, typically DRAM, and a memory buffer arranged to buffer data between the DRAM and a host controller. The memory buffer includes an error detection and correction circuit arranged to ensure the integrity of the stored data words. One way in which this may be accomplished is by computing parity bits for each data word and storing them in parallel with each data word. The error detection and correction circuit can be arranged to detect and correct single errors, or multi-errors if the host controller includes its own error detection and correction circuit. Alternatively, the locations of faulty storage cells can be determined and stored in an address match table, which is then used to control multiplexers that direct data around the faulty cells, to redundant DRAM chips in one embodiment or to embedded SRAM in another. | 10-18-2012 |
20130073802 | Methods and Apparatus for Transferring Data Between Memory Modules - A computer-implemented method for transferring data from a computer system programmed to perform the method includes receiving in a memory buffer in a first memory module hosted by the computer system, a request for data stored in RAM of the first memory module from a host controller of the computer system, retrieving with the memory buffer, the data from the RAM, in response to the request, formatting with the memory buffer, the data from the RAM into formatted data in response to a defined software transport protocol, and initiating with the memory buffer, transfer of the formatted data to a storage destination external to the first memory module via an auxiliary interface of the memory buffer, bypassing the host controller of the computer system. | 03-21-2013 |
20140215138 | MEMORY BUFFER WITH ONE OR MORE AUXILIARY INTERFACES - The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The additional interfaces may include, for example, a SATA interface, an Ethernet interface, an optical interface, and/or a radio interface. | 07-31-2014 |
20140215291 | SYSTEMS AND METHODS FOR ERROR DETECTION AND CORRECTION IN A MEMORY MODULE WHICH INCLUDES A MEMORY BUFFER - The present systems include a memory module containing a plurality of RAM chips, typically DRAM, and a memory buffer arranged to buffer data between the DRAM and a host controller. The memory buffer includes an error detection and correction circuit arranged to ensure the integrity of the stored data words. One way in which this may be accomplished is by computing parity bits for each data word and storing them in parallel with each data word. The error detection and correction circuit can be arranged to detect and correct single errors, or multi-errors if the host controller includes its own error detection and correction circuit. Alternatively, the locations of faulty storage cells can be determined and stored in an address match table, which is then used to control multiplexers that direct data around the faulty cells, to redundant DRAM chips in one embodiment or to embedded SRAM in another. | 07-31-2014 |
20150103481 | HYBRID MEMORY BLADE - The present invention is directed to server systems and methods thereof. More specifically, embodiments of the present invention provides a memory controller within a server system, where the memory controller is disengageably connected to one or more processors, a plurality of volatile memory modules, and plurality of solid-state memory modules. This memory controller may be connected to other similarly configured memory controllers. The volatile and solid-state memory modules can be removed and/or replaced. There are other embodiments as well. | 04-16-2015 |
20150261442 | MEMORY BUFFER WITH ONE OR MORE AUXILIARY INTERFACES - The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The memory buffer may be employed in various types of systems, such as a computer server system, a network system, or a data center. | 09-17-2015 |
20160026601 | HYBRID MEMORY BLADE - The present invention is directed to server systems and methods thereof. More specifically, embodiments of the present invention provides a memory controller within a server system, where the memory controller is disengageably connected to one or more processors, a plurality of volatile memory modules, and plurality of solid-state memory modules. This memory controller may be connected to other similarly configured memory controllers. The volatile and solid-state memory modules can be removed and/or replaced. There are other embodiments as well. | 01-28-2016 |
Patent application number | Description | Published |
20100330269 | Titanium-Based High-K Dielectric Films - This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO | 12-30-2010 |
20100330772 | METHODS FOR DEPOSITING HIGH-K DIELECTRICS - Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide. | 12-30-2010 |
20110014359 | Yttrium and Titanium High-K Dielectric Film - This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions. | 01-20-2011 |
20110151136 | METHODS FOR DEPOSITING HIGH-K DIELECTRICS - Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide. | 06-23-2011 |
20110203085 | TITANIUM-BASED HIGH-K DIELECTRIC FILMS - This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO | 08-25-2011 |
20120061799 | Yttrium and Titanium High-K Dielectric Films - This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions. | 03-15-2012 |
20120123744 | System and Method for Step Coverage Measurement - Determining an unknown step coverage of a thin film deposited on a 3D wafer includes exposing a planar wafer comprising a first film deposited thereon to X-ray radiation to create first fluorescent radiation; detecting the first fluorescent radiation; measuring a number of XRF counts on the planar wafer; creating an XRF model of the planar wafer; providing a portion of the 3D wafer comprising troughs and a second film deposited thereon; determining a multiplier factor between the portion of the 3D wafer and the planar wafer; exposing the portion of the 3D wafer to X-ray radiation to create second fluorescent radiation; detecting the second fluorescent radiation; measuring a number of XRF counts on the portion of the 3D wafer; calculating a step coverage of the portion of the 3D wafer; and determining a uniformity of the 3D wafer based on the step coverage of the portion of the 3D wafer. | 05-17-2012 |
20120156854 | METHOD OF FORMING STACKED METAL OXIDE LAYERS - This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor or DRAM cell. In such a device, a high-K zirconia-based layer may be used as the primary dielectric together with a relatively inexpensive metal electrode based on titanium nitride. To prevent corruption of the electrode during device formation, a thin barrier layer can be used seal the electrode prior to the use of a high temperature process and a (high-concentration or dosage) ozone reagent (i.e., to create a high-K zirconia-based layer). In some embodiments, the barrier layer can also be zirconia-based, for example, a thin layer of doped or un-doped amorphous zirconia. Fabrication of a device in this manner facilitates formation of a device with dielectric constant of greater than 40 based on zirconia and titanium nitride, and generally helps produce less costly, increasingly dense DRAM cells and other semiconductor structures. | 06-21-2012 |
20120156889 | METHODS FOR FORMING HIGH-K CRYSTALLINE FILMS AND RELATED DEVICES - This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor or DRAM cell. In such a device, a high-K zirconia-based layer may be used as the primary dielectric together with a relatively inexpensive metal electrode based on titanium nitride. To prevent corruption of the electrode during device formation, a thin barrier layer can be used seal the electrode prior to the use of a high temperature process and a (high-concentration or dosage) ozone reagent (i.e., to create a high-K zirconia-based layer). In some embodiments, the barrier layer can also be zirconia-based, for example, a thin layer of doped or un-doped amorphous zirconia. Fabrication of a device in this manner facilitates formation of a device with dielectric constant of greater than 40 based on zirconia and titanium nitride, and generally helps produce less costly, increasingly dense DRAM cells and other semiconductor structures. | 06-21-2012 |
20120160173 | Vapor Based Processing System with Purge Mode - Embodiments of the present invention provide vapor deposition tools. In one example, a vapor deposition tool includes housing. A substrate support is positioned within the housing and configured to support a substrate. A backing plate is positioned above the substrate support. A showerhead is positioned between the substrate support and the backing plate and has a plurality of openings therethrough. A fluid trap member is positioned around a periphery of the showerhead. A fluid trap member actuator is coupled to the fluid trap member and configured to move the fluid trap member between first and second positions relative to the backing plate. | 06-28-2012 |
20120235276 | ELECTRODE TREATMENTS FOR ENHANCED DRAM PERFORMANCE - A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO | 09-20-2012 |
20130069201 | Yttrium and Titanium High-K Dielectric Films - This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions. | 03-21-2013 |
20130069202 | Electrode Treatments for Enhanced DRAM Performance - A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO | 03-21-2013 |
20130071990 | Yttrium and Titanium High-K Dielectric Films - This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions. | 03-21-2013 |
20130071991 | Electrode Treatments for Enhanced DRAM Performance - A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO | 03-21-2013 |
20130143383 | METHOD OF FORMING AN ALD MATERIAL - In some embodiments of the present invention, methods are developed wherein a gas flow of an electron donating compound (EDC) is introduced in sequence with a precursor pulse and alters the deposition of the precursor material. In some embodiments, the EDC pulse is introduced sequentially with the precursor pulse with a purge step used to remove the non-adsorbed EDC from the process chamber before the precursor is introduced. In some embodiments, the EDC pulse is introduced using a vapor draw technique or a bubbler technique. In some embodiments, the EDC pulse is introduced in the same gas distribution manifold as the precursor pulse. In some embodiments, the EDC pulse is introduced in a separate gas distribution manifold from the precursor pulse. | 06-06-2013 |
20130272496 | System and Method for Step Coverage Measurement - Determining an unknown step coverage of a thin film deposited on a 3D wafer includes exposing a planar wafer comprising a first film deposited thereon to X-ray radiation to create first fluorescent radiation; detecting the first fluorescent radiation; measuring a number of XRF counts on the planar wafer; creating an XRF model of the planar wafer; providing a portion of the 3D wafer comprising troughs and a second film deposited thereon; determining a multiplier factor between the portion of the 3D wafer and the planar wafer; exposing the portion of the 3D wafer to X-ray radiation to create second fluorescent radiation; detecting the second fluorescent radiation; measuring a number of XRF counts on the portion of the 3D wafer; calculating a step coverage of the portion of the 3D wafer; and determining a uniformity of the 3D wafer based on the step coverage of the portion of the 3D wafer. | 10-17-2013 |
20140077337 | High Temperature ALD Process for Metal Oxide for DRAM Applications - A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive metal oxide formed using a high temperature, low pressure ALD process. The high temperature ALD process results in a layer with enhanced crystallinity, higher density, reduced shrinkage, and lower carbon contamination. The high temperature ALD process can be used for either or both the bottom electrode and the top electrode layers. | 03-20-2014 |
Patent application number | Description | Published |
20130044404 | Titanium-Based High-K Dielectric Films - This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO | 02-21-2013 |
20130056852 | Methods For Depositing High-K Dielectrics - Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide. | 03-07-2013 |
20130320495 | Integration of Non-Noble DRAM Electrode - A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment. | 12-05-2013 |
20130330902 | ENHANCED NON-NOBLE ELECTRODE LAYERS FOR DRAM CAPACITOR CELL - A metal oxide first electrode material for a MIM DRAM capacitor is formed wherein the first and/or second electrode materials or structures contain layers having one or more dopants up to a total doping concentration that will not prevent the electrode materials from crystallizing during a subsequent anneal step. Advantageously, the electrode doped with one or more of the dopants has a work function greater than about 5.0 eV. Advantageously, the electrode doped with one or more of the dopants has a resistivity less than about 1000 μΩ cm. Advantageously, the electrode materials are conductive molybdenum oxide. | 12-12-2013 |
20140080284 | High Temperature ALD Process of Metal Oxide for DRAM Applications - A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive metal oxide formed using a high temperature, low pressure ALD process. The high temperature ALD process results in a layer with enhanced crystallinity, higher density, reduced shrinkage, and lower carbon contamination. The high temperature ALD process can be used for either or both the bottom electrode and the top electrode layers. | 03-20-2014 |
20140166840 | Substrate Carrier - A substrate carrier is provided. The substrate carrier includes a base for supporting a substrate. A plurality of support tabs is affixed to a surface of the base. The plurality of support tabs have a cavity defined within an inner region of each support tab of the plurality of support tabs. A plurality of protrusions extends from the surface of the base, wherein one of the plurality of protrusions mates with one cavity to support one of the plurality of support tabs. A film is deposited over the surface of the base, surfaces of the plurality of support tabs and surfaces of the plurality of protrusions. | 06-19-2014 |
20160035631 | Atomic Layer Deposition of HfAlC as a Metal Gate Workfunction Material in MOS Devices | 02-04-2016 |