Patent application number | Description | Published |
20090119357 | ADVANCED CORRELATION AND PROCESS WINDOW EVALUATION APPLICATION - A method only has the user input (or select) a data type, a report key, a dependent variable table, and/or filtering restrictions. Using this information, the method automatically locates independent variable data based on the data type and the report key. This independent variable data can be in the form of a table and comprises independent variables. The method automatically joins the dependent variable table and the independent variable data to create a joint table. Then, the method can automatically perform a statistical analysis of the joint table to find correlations between the dependent variables and the independent variables and output the correlations, without requiring the user to input or identify the independent variables. | 05-07-2009 |
20090125829 | AUTOMATED YIELD SPLIT LOT (EWR) AND PROCESS CHANGE NOTIFICATION (PCN) ANALYSIS SYSTEM - Disclosed are an automated data analysis system and method. They system provides a standardized data analysis request form that allows a user to select an experiment (e.g., a wafer-level based yield split lot (EWR) analysis, a lot-level based process change notification (PCN) analysis, and lot-level based tool/mask qualification analysis) and a data analysis for a specific process module of interest. For each specific data analysis request, the system identifies critical test parameters, which are grouped depending on in-line test levels and photolithography levels. The system links the analysis request to test data sources and automatically monitors the test data sources, searching for the critical test parameters. When the critical test parameters become available, the system automatically performs the requested analysis, generates a report of the analysis and publishes the report with optional drill downs to more detailed results. The system further provides automatic e-mail notification of the published report. | 05-14-2009 |
20090143999 | REAL TIME SYSTEM FOR MONITORING THE COMMONALITY, SENSITIVITY, AND REPEATABILITY OF TEST PROBES - A system and a method for effectively determining the measurement sensitivity, repeatability, and probe commonality to assist a test engineer determine if the tester meets the specified resolution at every test. A statistical measurement of inherent tester specifications are provided with the added accumulation of the probe contact resistance during the probing process. It further provides a feedback to the test probe card noise level while testing is in progress. Moreover, the system and the method determine the test probing integrity in-situ when testing integrated circuit chips or wafers, dynamically detecting probing errors, and modifying data associated with defective test probes. | 06-04-2009 |
20090150811 | METHODS AND COMPUTER PROGRAM PRODUCTS FOR EXCLUDING VARIATIONS ATTRIBUTABLE TO EQUIPMENT FROM SPLIT ANALYSIS PROCEDURES - Excluding variations attributable to equipment from split analysis is performed by identifying dependent variables related to at least one of the split analysis or an experiment to be performed. A test is performed to ascertain whether or not a variation attributable to equipment exists with respect to any of the identified dependent variables. If such a variation exists, a target data set and a training data set are constructed. A signature is identified for the variation. A statistical model is selected based upon the identified signature. The selected statistical model is constructed using the training data set to generate a statistical output. The target data set is joined with the statistical output. The identified dependent variables in the target data set are adjusted using the statistical output. The target data set including the adjusted identified dependent variables is loaded to an application for performing split analysis. | 06-11-2009 |
20090299679 | Method of Adaptively Selecting Chips for Reducing In-line Testing in a Semiconductor Manufacturing Line - A method for identifying potentially defective integrated circuit chips and excluding them from future testing as wafers move through a manufacturing line The method includes data-collecting steps, tagging the chips on wafers identified as potentially bad chips based on information collected as the wafer moves down the fabrication line, evaluating test cost savings by eliminating any further tests on the tagged chips preferably using a test cost database. Considering all the future tests to be preformed, the tagged chips are skipped if it is determined that the test cost saving is significant. Tagging bad chips is based on various criteria and models which are dynamically adjusted by performing the wafer final test on samples of the tagged chips and feeding-back the final test results. The dynamic adaptive adjustment method preferably includes a feedback loop or iterative process to evaluate financial tradeoffs when assessing the profit of salvaging chips against the additional test costs. | 12-03-2009 |
20090306807 | MULTIDIMENSIONAL PROCESS WINDOW OPTIMIZATION IN SEMICONDUCTOR MANUFACTURING - A method for optimizing multiple process windows in a semiconductor manufacturing process is disclosed. The message comprises performing dependent variable composition on a plurality of dependent variables. Metrology data is joined with the dependent variables, and then a partial least squares regression is performed on the joined data set to obtain a prediction equation, and a variable importance prediction for each process window in a process window set. A set of product limited yield are derived, and the process window set is adjusted, and the yields recalculated, until an optimal process window set is derived. | 12-10-2009 |
20090317924 | METHOD FOR OPTIMIZING THE ROUTING OF WAFERS/LOTS BASED ON YIELD - A method for increasing overall yield in semiconductor manufacturing including routing wafers or wafer lots based on process variation data obtained from the wafers or wafer lots and on process variation data obtained from tools processing the wafers or wafer lots. A system for increasing overall yield in semiconductor manufacturing includes a module for routing wafers or wafer lots based on process variation data obtained from the wafers or wafer lots and on process variation data obtained from the tools processing the wafers or wafer lots. | 12-24-2009 |
20090319074 | METHOD FOR COMPENSATING FOR TOOL PROCESSING VARIATION IN THE ROUTING OF WAFERS/LOTS - A method for increasing overall yield in semiconductor manufacturing including routing wafers or wafer lots from tool to tool in a manner which at least partially neutralizes or compensates for processing variations. A system for increasing overall yield in semiconductor manufacturing includes a module for recording processing data from plural first and second types of tools and a module for routing wafers or wafer lots from tools of the first type of tools to tools of the second type of tools so as to at least partially neutralizes or compensate for processing variation. | 12-24-2009 |
20100017010 | MONITORING A PROCESS SECTOR IN A PRODUCTION FACILITY - Monitoring a process sector in a production facility includes establishing a tool defect index associated with a process sector in the production facility. The tool defect index includes a signal representing a defect factor associated with a tool in the process sector. Monitoring the process also requires determining whether the defect factor is a known defect factor or an unknown defect factor, and analyzing a unit from the tool if the defect factor is an unknown defect factor. Monitoring the process further requires identifying at least one defect on the unit from the tool, establishing that the at least one defect is a significant defect, determining cause of the significant defect, and creating an alert indicating that the tool associated with the process sector is producing units having significant defects. | 01-21-2010 |
20100185675 | SECURITY CONTROL OF ANALYSIS RESULTS - A system and a method are provided. The method includes assigning an entity to a ticket group associated with an ID thereof, displaying to the entity reports, which are each organized with an associated security access control, in accordance with the ticket group, determining whether the entity is authorized to access any selected one or more of the reports in accordance with a result of a comparison between an access level associated with the entity ID and the security access control associated with each of the one or more of the stored reports, and granting or denying the access in accordance with the determination. | 07-22-2010 |
20100204940 | METHOD AND SYSTEM OF COMMONALITY ANALYSIS FOR LOTS WITH SCRAPPED WAFER - According to an embodiment of the present invention is to provide methods to evaluate the impact of scrapped wafers on the remaining wafers in a lot by using scrap codes and statistical models. An embodiment of the present invention provides a method to obtain a baseline lot population by using cluster analysis model and functional limited yields. The functional limited yields may be for example chain limited yield, dc limited yield, or ac abist limited yield. By utilizing statistical modeling it is possible to determine which failures have an impact on the lot yield and require rework for the lot. In addition by monitoring the impact of failures, it is possible to determine if corrective actions need to be taken for lots that passed through a process prior to correction of the fault. | 08-12-2010 |
20120146682 | YIELD ENHANCEMENT FOR STACKED CHIPS THROUGH ROTATIONALLY-CONNECTING-INTERPOSER - A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i−1)/N×2π. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield. | 06-14-2012 |
20120241977 | CONFIGURABLE INTERPOSER - A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers. | 09-27-2012 |
20130169308 | LCR TEST CIRCUIT STRUCTURE FOR DETECTING METAL GATE DEFECT CONDITIONS - A test structure for an integrated circuit device includes a series inductor, capacitor, resistor (LCR) circuit having one or more inductor elements, with each inductor element having at least one unit comprising a first segment formed in a first metal layer, a second segment connecting the first metal layer to a semiconductor substrate beneath the first metal layer, and a third segment formed in the semiconductor substrate; and a capacitor element connected in series with each inductor element, the capacitor element defined by a transistor gate structure including a gate electrode as a first electrode, a gate dielectric layer, and the semiconductor substrate as a second electrode. | 07-04-2013 |
20130307159 | PHYSICAL DESIGN SYMMETRY AND INTEGRATED CIRCUITS ENABLING THREEDIMENTIONAL (3D) YIELD OPTIMIZATION FOR WAFER TO WAFER STACKING - One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been relocated due to rotation. A communication channel formed from a pair of pads that are interconnected by a Through Substrate Vias can be placed in each die and can convey selected information from one die to the next. A code representative of the position orientation of each die can be recorded in a Programmable Read Only Memory located on each die, or may be down loaded from a remote source. Any additional wafer may be stacked serially, and each one may be rotated relative to the wafer that precedes it in the stack. | 11-21-2013 |
20140145351 | CONFIGURABLE INTERPOSER - A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers. | 05-29-2014 |
20140203448 | RANDOM CODED INTEGRATED CIRCUIT STRUCTURES AND METHODS OF MAKING RANDOM CODED INTEGRATED CIRCUIT STRUCTURES - Randomized coded arrays and methods of forming a randomized coded array. The methods include: forming a dielectric layer on a semiconductor substrate; forming an array of openings extending through the dielectric layer; introducing particles into a random set of less than all of the openings; and forming a conductive material in each opening of the array of openings, thereby creating the randomized coded array, wherein a first resistance of a pathway through the conductive material in openings containing the particles is different from a second resistance of a path through openings not containing the particles. Also, a physically unclonable function embodied in a circuit. | 07-24-2014 |