Patent application number | Description | Published |
20130063374 | METHOD FOR CONVERTING CONTROL INPUT OF INPUT DOMAIN INTO CONTROL OUTPUT OF CONTROL DOMAIN USING VARIABLE CONTROL RESOLUTION TECHNIQUE, AND RELATED CONTROL APPARATUS THEREOF - An exemplary method for determining a control output in a control domain includes: obtaining a control input of an input domain, wherein the control input includes a previous input value and a current input value; and dynamically adjusting a control resolution setting, and converting the control input of the input domain into the control output in the control domain according to the control resolution setting, wherein the control output includes a previous output value and a current output value corresponding to the previous input value and the current input value, respectively, the control resolution setting for the current input value is determined according to at least the previous input value, and the current output value is identical to the previous output value when the current input value and the previous input value are generated in response to a same user input. | 03-14-2013 |
20130249864 | METHODS FOR INPUT-OUTPUT CALIBRATION AND IMAGE RENDERING - One of the embodiments of the invention provides an input-output calibration method performed by a processing unit connected to an output device and an input device. The output device and the input device correspond to an output device coordinate system and an input device coordinate system, respectively. The processing unit first derives M calibration points' coordinates in the input device coordinate system by using the input device to sense a viewer specifying the M calibration points' positions, wherein M is a positive integer. Then, the processing unit uses the M calibration points' coordinates in the output device coordinate system and coordinates in the input device coordinate system to derive the relationship between the output device coordinate system and the input device coordinate system. | 09-26-2013 |
20140085416 | METHOD AND APPARATUS OF TEXTURE IMAGE COMPRESS IN 3D VIDEO CODING - A method and apparatus for texture image compression in a 3D video coding system are disclosed. Embodiments according to the present invention derive depth information related to a depth map associated with a texture image and then process the texture image based on the depth information derived. The invention can be applied to the encoder side as well as the decoder side. The encoding order or decoding order for the depth maps and the texture images can be based on block-wise interleaving or picture-wise interleaving. One aspect of the present invent is related to partitioning of the texture image based on depth information of the depth map. Another aspect of the present invention is related to motion vector or motion vector predictor processing based on the depth information. | 03-27-2014 |
20150331516 | METHODS FOR INPUT-OUTPUT CALIBRATION AND IMAGE RENDERING - One of the embodiments of the invention provides an input-output calibration method performed by a processing unit connected to an output device and an input device. The output device and the input device correspond to an output device coordinate system and an input device coordinate system, respectively. The processing unit first uses the input device to derive a plurality of lines in the input device coordinate system for M calibration points by sensing a viewer specifying the M calibration points' positions, wherein the plurality of lines are between the M calibration points and the viewer's the predetermined object's different positions, and M is a positive integer equal to or larger than three. Then, the processing unit derives the M calibration points' coordinates in the input device coordinate system according to the plurality of lines and uses the M calibration points' coordinates in the output device coordinate system and coordinates in the input device coordinate system to derive the relationship between the output device coordinate system and the input device coordinate system. | 11-19-2015 |
Patent application number | Description | Published |
20110079285 | POLYMER SOLAR CELL AND MANUFACTURING METHOD THEREOF - A manufacturing method of a polymer solar cell is illustrated. A substrate and a first conductive layer formed thereon are provided. An organic active semiconductor material and a functional organic material, which features modifying an interface between an organic layer and electrodes, are dissolved in an organic solvent to form a blend. The blend is deposited on the first conductive layer by solution process. The organic solvent is removed, such that the functional organic material and the organic active semiconductor material exhibit phase separation so as to form an organic modified layer on the top of the organic active semiconductor layer. A second conductive layer is deposited by thermal coating on the organic modified layer. Importantly, the organic modified layer formed by spontaneous phase separation effectively modifies the interface between the organic active semiconductor layer and a second conductive layer, thereby enhancing efficiency of an organic solar cell. | 04-07-2011 |
20120115266 | MANUFACTURING METHOD FOR ORGANIC OPTOELECTRONIC THIN FILM - Disclosed is a manufacturing method for an organic optoelectronic thin film comprising the steps of providing a substrate and a first electrode; forming a semiconductor layer on the substrate, wherein the semiconductor layer includes polyethylene glycol (PEG); forming a conductive polymer layer on the first electrode; disposing the substrate and the semiconductor layer on the conductive polymer layer and adhering the semiconductor layer to the conductive polymer layer; and removing the substrate; and forming a second electrode on the semiconductor layer. A first adhesion between the semiconductor layer and the substrate is generated. A second adhesion between the semiconductor layer and the conductive polymer layer is generated. The second adhesion is greater than the first adhesion so that while the substrate is removed, the semiconductor layer and the conductive polymer layer are still adhered. | 05-10-2012 |
20130140662 | PHOTODIODE DEVICE FOR IMPROVING THE DETECTIVITY AND THE FORMING METHOD THEREOF - A method for forming the photodiode device is provided. The method comprises providing a substrate, then a transparent conductive film is formed on the substrate. A conductive polymer is formed on the transparent conductive film. A photoactive layer is formed on the conductive polymer. A charge blocking layer is formed on the photoactive layer. Finally, a cathode metal is formed on the charge blocking layer. | 06-06-2013 |
Patent application number | Description | Published |
20130190140 | ANTI-DRIFT MECHANISM FOR TREADMILL - An anti-drift mechanism for a treadmill having a chassis, a support frame, and endless belt is mounted between a bottom side of the support frame and a lower half part of the endless belt includes a guide member and a pressing axial member sleeved onto the guide member. The guide member is mounted to the chassis of the treadmill and movable longitudinally with respect to the endless belt in such a way that the pressing axial member can be driven by the guide member to oppress the endless belt so as to increase the pressure applied to the endless belt for the purpose of adjusting the drifting belt back to its normal operational position. | 07-25-2013 |
20140031172 | WEIGHT TRAINER WITH LOAD DETECTION SYSTEM - A weight trainer with a load detection system includes a frame, a load detecting device, and a display device. The frame has a transmission device, a weight allocating device, and a stand. The transmission device is disposed on one side of the frame. The weight allocating device is connected to the transmission device and can undergo displacement in the vertical direction of the stand. The load detecting device is disposed beneath the weight allocating device. The load detecting device includes a sensor, a base, and a platform. The sensor is abuttingly disposed between the base and the platform. The display device is electrically connected to the load detecting device. Accordingly, the weight trainer with a load detection system is effective in detecting a weight change precisely, enabling a user taking fitness exercise to gain access to information thereof in real time, and quantifying the information. | 01-30-2014 |
Patent application number | Description | Published |
20150035201 | METHOD OF MANUFACTURING ELECTRONIC PACKAGE MODULE - A method of manufacturing electronic package module is provided. The method provides selective molding by attaching tapes on the circuit substrate on which electric components are mounted thereon, forming molding compound to cover the circuit substrate, and removing tapes along with the molding compound thereon. | 02-05-2015 |
20150036296 | EMI COMPARTMENT SHIELDING STRUCTURE AND FABRICATING METHOD THEREOF - A package-integrated EMI compartment shielding structure includes an encapsulating member disposed on a mounting surface of a substrate. The substrate has a ground pad exposedly arranged thereon. The encapsulating member, who defines a peripheral surface, covers the ground pad and encapsulates at least one electronic element. A compartment structure is disposed in the encapsulating member, electrically connecting the ground pad and substantially dividing the encapsulating member into at least two package compartments. The terminal portions of the compartment structure are arranged within the encapsulating member proximal to yet without compromising the peripheral surface. A notch is disposed into the encapsulating member from the peripheral surface corresponding to the location of the terminal portions of the compartment structure to expose the lateral surface thereof across the thickness of the encapsulating member. A conformal shield is disposed on the encapsulating member, electrically connecting the compartment structure through the notch. | 02-05-2015 |
20150036297 | ELECTRONIC MODULE AND METHOD OF MAKING THE SAME - A method of manufacturing electronic module is provided. The method can perform selective partial molding by forming the tapes in a predetermined area on the circuit substrate, setting electronic components out the predetermined area on the circuit substrate, forming the molding member encapsulating the whole circuit substrate and removing the tapes along of the molding member thereon. Following, forming an EMI shielding layer on the molding member and setting optoelectronics in the predetermined area on the circuit substrate could protect the electronic components from electromagnetic disturbance and avoid the optoelectronics being encapsulated. | 02-05-2015 |
20160081235 | ELECTRONIC PACKAGED DEVICE - A manufacturing method of electronic packaged device includes the following. A plurality of electronic components is disposed on a substrate carrier. An encapsulating member is disposed on the substrate carrier and covers the electronic components. The substrate carrier is separated from the encapsulating member. A plurality of first trenches is arranged on a first surface of the encapsulating member. Conductive material is disposed onto the first surface and into the first trenches to form a conductive layer. The conductive layer is patterned on the first surface to form a circuit layer. The circuit layer includes at least one grounding pad. A plurality of second trenches is arranged on a second surface of the encapsulating member. At least one shielding structure is formed in the first trenches and the second trenches. An electromagnetic shielding layer is connected to the grounding pad. | 03-17-2016 |
Patent application number | Description | Published |
20140160708 | LEAD STRUCTURE - A lead structure disposed on a substrate is provided. The substrate includes a display area disposed with a device and a peripheral area disposed with a lead structure including first pads, a second pad, first traces and a second trace. The first traces are connected to the device. Each first trace has a first linear portion and a first bonding portion connected together. Each first trace is electrically connected to one of the first pads through the first bonding portion. The second trace has a second linear portion and a second bonding portion connected together. The second trace is electrically connected to the second pad through the second bonding portion. A width of the first linear portion is smaller than a width of the first bonding portion, and a width of the second linear portion is smaller than a width of the second bonding portion. | 06-12-2014 |
20140184950 | TOUCH PANEL - A touch panel, having a peripheral region, includes a first substrate, a touch-sensing structure, first outer traces, a first ground wire and an outer device. The first outer trace is electrically connected to the touch-sensing structure. The first outer traces extend to a connection region in the peripheral region. The first ground wire extends to the connection region, and the first ground wire has at least one discontinuous section in the connection region. The outer device is electrically connected to the first ground wire and the first outer traces in the connection region. The outer device electrically connects two ends of the discontinuous section of the first ground wire in the connection region, and the two ends of the discontinuous section of the first ground wire are electrically connected via the outer device. | 07-03-2014 |
20140184952 | TOUCH PANEL - A touch panel, having a peripheral region, includes a first substrate, a plurality of first conductive series, a plurality of first outer traces, and an outer device. The first conductive series are disposed on the first substrate and extend along a first direction. The first outer traces are disposed in the peripheral region. Two ends of each of the first outer traces are respectively connected to two ends of the corresponding first conductive series. The first outer traces connected to the each of the first conductive series extend to a connection region within the peripheral region and include discontinuous sections within the connection region. The outer device is disposed in the peripheral region and is electrically connected to the first outer traces. Each of the first outer traces, each corresponding first conductive series, and the outer device in the connection region constitute a closed conductive path on the first substrate. | 07-03-2014 |
20140300835 | TOUCH PANEL - A touch panel, having a light transmission touch sensing region and a peripheral region adjacent to at least one side of the light transmission touch sensing region, includes an inner frame and a decoration frame disposed in the peripheral region. The peripheral region has an inner edge and an outer edge, wherein the inner edge is closer to the light transmission touch sensing region than the outer edge. The inner sidewall of the inner frame is disposed along the inner edge of the peripheral region. The decoration frame includes at least one decoration layer. The pattern of the decoration layer does not exceed the inner edge of the peripheral region. | 10-09-2014 |
20140354591 | TOUCH PANEL - A touch panel includes a substrate, a patterned decoration layer, a patterned transparent conductive layer and an optical compensation layer. The patterned decoration layer is disposed on the substrate so as to define an opening region and a hole on the substrate. The hole is disposed adjacently to a side of the opening region. The patterned transparent conductive layer is disposed on the substrate. The patterned transparent conductive layer includes a transparent conductive pattern. The transparent conductive pattern is disposed correspondingly to the hole, and the transparent conductive pattern completely covers the hole along a vertical projective direction perpendicular to the substrate. The optical compensation layer is disposed on the substrate, and the optical compensation layer covers the hole along the vertical projective direction. | 12-04-2014 |
20140362043 | TOUCH PANEL - The present invention discloses a touch panel, which includes a substrate, a plurality of first axis electrodes, a plurality of second axis electrodes and an insulation structure. The first axis electrodes are disposed on the substrate along a first direction and each of the first axis electrodes includes a plurality of first sub electrodes and a plurality of connection structures. Each of the connection structures is at least partially disposed between each of the first sub electrodes and the substrate, and is electrically connected to two adjacent first sub electrodes. Each of the connection structures includes a first metal layer and a low reflective layer disposed between the substrate and the first metal layer. The low reflective layer of the present invention is applied to reduce the visibility of the connection structures, as well as to enhance the reliability of the touch panel. | 12-11-2014 |
20150049263 | TOUCH DISPLAY DEVICE - A touch display device including a touch panel, a protection layer, a conductive optical adhesive layer and a display panel is provided. The touch panel includes a substrate, pads, at least one grounding pad, a touch-sensing device, and at least one ESD protection line. The touch panel includes a pad area and an active area. The pads and the grounding pad are disposed on the substrate and located in the pad area. The touch-sensing device is disposed on the substrate and located in the active area. The ESD protection line is disposed on the substrate and located at a side of the active area. The protection layer including a first opening covers the touch panel and a portion of the pad area is exposed by the first opening. The conductive optical adhesive layer is disposed on the protection layer and electrically connected to the ESD protection circuit. | 02-19-2015 |
20150070604 | TOUCH DEVICE - A touch device includes a cover substrate, a thin substrate, a first adhesive layer, a first touch sensing unit and a first outer unit. The thin substrate is disposed opposite to the cover substrate. The thin substrate has a first surface and a second surface opposite to the first surface. The first surface faces the cover substrate. A thickness of the thin substrate is thicker than or equal to 0.05 millimeter and thinner than or equal to 0.25 millimeter. The first adhesive layer is disposed between the cover substrate and the thin substrate. The first touch sensing unit is disposed on the thin substrate. The first outer unit is electrically connected to the first touch sensing unit. | 03-12-2015 |
20150077654 | TOUCH PANEL - A touch panel having a light transmitting area and a light shielding area adjacent to the light transmitting area is provided. The touch panel includes a cover plate, a first decoration layer, a touch-sensing element and a metal conductive layer. The first decoration layer is disposed on the cover plate and located in the light shielding area. The first decoration layer has at least one hollow area. The touch-sensing element is disposed on the cover plate and at least located in the light transmitting area. The metal conductive layer is disposed on the first decoration layer, located in the light shielding area and surrounds the touch-sensing element. A portion of the metal conductive layer surrounds the hollow area. | 03-19-2015 |
Patent application number | Description | Published |
20130283221 | METHOD FOR INPUT/OUTPUT DESIGN OF CHIP - Method for input/output (IO) design of a chip, including: according to a signal IO pin sequence and associated driving parameters, sequentially placing a signal IO cell in the IO design associated with each of the signal IO pins; after a signal IO cell is placed, performing a simultaneous switching output (SSO) verification step according to physical layout parameters and locations of the signal IO cells placed in the IO design, so as to check whether an SSO specification is violated; if not violated, continuing to place a signal IO cell of a next signal IO pin; if violated, including a decoupling capacitor, an IO power cell and/or an IO ground cell in the IO design. | 10-24-2013 |
20150042369 | METHOD AND AN APPARATUS OF DETERMINING PERFORMANCE OF AN INTEGRATED CIRCUIT - The present invention discloses an efficient method to determine the performance of an integrated circuit or a chip by instantiating a plurality of HPM in the integrated circuit to generate the performance of the integrated circuit according to a performance function, wherein each term of the performance function is based on the values of the HPM(s) and the weighting of the term is determined through machine leaning, so that the performance of each chip can be determined by the performance function. | 02-12-2015 |
20150226790 | ELECTRONIC DEVICE, PERFORMANCE BINNING SYSTEM AND METHOD, VOLTAGE AUTOMATIC CALIBRATION SYSTEM - A method for determining performance of an integrated circuit (IC) is disclosed herein. The method includes following operations: disposing hardware performance monitors (HPMs) in each of ICs, in which each of HPMs generates a value for generating the performance of the IC; providing a performance function including of terms according to values generated by the HPMs, in which a weight is associated with each of terms; determining the weight of each of terms according to a first set of ICs of the ICs, wherein the performance of each of the ICs is known; and determining the performance of a first ICs of the ICs according to the performance function, wherein the performance function and the weights are built into the first ICs. | 08-13-2015 |
20150301107 | AGING DETECTION CIRCUIT AND METHOD THEREOF - An aging detection circuit is provided. The aging detection circuit is configured on a chip and includes a testing circuit and an aging signal generation circuit. The testing circuit is electrically coupled to the aging signal generation circuit. The testing circuit generates an output signal. The aging signal generation circuit includes a signal generation circuit and a selection circuit. The signal generation circuit generates multiple input signals having different frequencies. The selection circuit selectively outputs one of the input signals as an aging signal to an input terminal of the testing circuit or feeds back the output signal generated by the testing circuit to the input terminal of the testing circuit. | 10-22-2015 |
Patent application number | Description | Published |
20080305610 | METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION STRUCTURE - A method of forming a shallow trench isolation structure includes steps of providing a substrate having a patterned mask layer formed thereon, wherein a trench is located in the substrate and the patterned mask layer exposes the trench. Thereafter, a dielectric layer is formed over the substrate to fill the trench. Then, a main polishing process with a first polishing rate is performed to remove a portion of the dielectric layer. An assisted polishing process is performed to remove the dielectric layer and a portion of the mask layer. The assisted polishing process includes steps of providing a slurry in a first period of time and then providing a solvent and performing a polishing motion of a second polishing rate in a second period of time. The second polishing rate is slower than the first polishing rate. Further, the mask layer is removed. | 12-11-2008 |
20090061623 | METHOD OF FORMING ELECTRICAL CONNECTION STRUCTURE - A method of forming an electrical connection structure is described. A dielectric layer is formed covering a first conductor on a substrate, and then an opening is formed in the dielectric layer exposing the first conductor. A first cleaning step is conducted using fluorine-containing plasma to clean the surfaces of the dielectric layer and the exposed first conductor, and then at least one low-temperature annealing step is conducted. A second cleaning step is conducted using argon plasma to clean the above surfaces. A second conductor is then formed in the opening. | 03-05-2009 |
20090298294 | METHOD FOR CLEARING NATIVE OXIDE - A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF | 12-03-2009 |
20120220134 | METHOD FOR CLEARING NATIVE OXIDE - A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF | 08-30-2012 |
20130316540 | METHOD FOR REMOVING OXIDE - A method for removing oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A removing oxide process is performed to the substrate using nitrogen trifluoride (NF | 11-28-2013 |
Patent application number | Description | Published |
20090116244 | LIGHT-EMITTING MODULE - A light-emitting module includes a substrate having a first surface and a second surface, at least one light-emitting device disposed on the first surface of the substrate, and an optical reflection layer disposed on the first surface of the substrate and surrounding the light-emitting device for receiving a portion of light emitted from the light-emitting device and reflecting the portion of light. The substrate can be rigid or flexible. | 05-07-2009 |
20090173529 | CIRCUIT STRUCTURE AND FABRICATION METHOD THEREOF - A circuit structure and a fabrication method thereof manly use a plurality of wires to connect in series a plurality of pads to form a stretchable circuit. Each of the wires has a first end, a second end and an intermediate segment located between the first end and the second end, wherein the first end and the second end are respectively connected to different pads, and the position of the intermediate segment is higher than the positions of the first end and the second end. Since the connection manner of the wires and the pads has 3-D freedoms, the circuit structure can withstand both horizontal and vertical deformations and has an outstanding reliability. | 07-09-2009 |
20100163296 | STRUCTURE OF MULTIPLE COAXIAL LEADS WITHIN SINGLE VIA IN SUBSTRATE AND MANUFACTURING METHOD THEREOF - A plurality of coaxial leads is made within a single via in a circuit substrate to enhance the density of vertical interconnection so as to match the demand for higher density multi-layers circuit interconnection between top circuit layer and bottom circuit layer of the substrate. Coaxial leads provide electromagnetic interference shielding among the plurality of coaxial leads in a single via. | 07-01-2010 |
20100163897 | FLEXIBLE LIGHT SOURCE DEVICE AND FABRICATION METHOD THEREOF - A flexible light source device including a substrate, a light emitting device, a molding compound, a dielectric layer, and a metal line is provided. The substrate has a first surface, a second surface opposite to the first surface, and a first opening. The light emitting device is disposed on the first surface of the substrate and covers the first opening. The molding compound is located above the first surface and covers the light emitting device. The dielectric layer is disposed on the second surface and covers a sidewall of the first opening. The dielectric layer has a second opening which exposes part of the light emitting device. The metal line is disposed on the dielectric layer, wherein the metal line is electrically connected to the light emitting device via the second opening in the dielectric layer. Additionally, a fabrication method of the flexible light source device is also provided. | 07-01-2010 |
20130128610 | PLANE LIGHT SOURCE AND FLEXIBLE PLANE LIGHT SOURCE - A plane light source including a circuit substrate, a plurality of sets of side-view light-emitting devices (LEDs), and a diffusive light-guiding layer is provided. The side-view LEDs are arranged in array over the circuit substrate and are electrically connected with the circuit substrate. The diffusive light-guiding layer covers the side-view LEDs, wherein the diffusive light-guiding layer includes a plurality of diffusive light-guiding units arranged in array and connected to each other. Each of the diffusive light-guiding units is respectively corresponded to illumination coverage of one set of side-view LEDs. Each set of side-view LEDs at least includes two side-view LEDs for emitting light respectively along two different directions and towards into one single diffusive light-guiding units. | 05-23-2013 |