Patent application number | Description | Published |
20090055798 | METHOD AND APPARATUS FOR ADDRESS TAKEN REFINEMENT USING CONTROL FLOW INFORMATION - A computer implemented method, apparatus, and computer program product for obtaining aliasing information for a target variable in a computer program. A control flow graph representing the computer program is partitioned into an taken address portion that includes all reachable nodes in which an address of the target variable is taken and an untaken address portion that includes all other reachable nodes. All references to the target variable are replaced with a temporary variable in the untaken address portion. The target variable is initialized with the value from the temporary variable at each intermediary node in a set of intermediary nodes in the taken address portion. An intermediary node is a node at which an address of a target variable is taken. The aliasing information for the target variable is generated using the modified computer program. | 02-26-2009 |
20090055815 | Eliminate Maximum Operation in Loop Bounds with Loop Versioning - A method and computer program product for eliminating maximum and minimum expressions within loop bounds are provided. A loop in a code is identified. The loop is determined to meet conditions, which require an upper loop bound and a lower loop bound to contain maximum and minimum expressions, loop-invariant operands, a predetermined size for a code size, and a total number of instructions to be greater than a predetermined constant. A profitability of loop versioning is determined based on a performance gain of a fast version of the loop, a probability of executing the fast version of the loop at runtime, and an overhead for performing loop versioning. A pair of lower loop bound and upper loop bound values resulting in a constant number is identified. A loop iteration value is checked to be a non-zero constant. Branches are identified, and loop versioning is performed to generate a versioned loop. | 02-26-2009 |
20090287766 | BROKERING MOBILE WEB SERVICES - The invention provides a novel mobile web services discovery method that is capable of fulfilling the requirements from both the clients and providers. It allows the provider to balance the cost/performance ratios and utilize the network bandwidth more effectively, while also attaining the quality levels expected by the client. | 11-19-2009 |
Patent application number | Description | Published |
20090115457 | Apparatus and Methods for Self-Biasing Differential Signaling Circuitry Having Multimode Output Configurations for Low Voltage Applications - The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output. | 05-07-2009 |
20090121761 | INTRA-PAIR DIFFERENTIAL SKEW COMPENSATION METHOD AND APPARATUS FOR HIGH-SPEED CABLE DATA TRANSMISSION SYSTEMS - A differential serial communication receiver circuit automatically compensates for intrapair skew between received differential signals on a serial differential communication link, with deterministic skew adjustment set during a receiver training period. Intrapair skew refers to the skew within a pair of differential signals, and is hence interchangeable with the term differential skew in the context of this document. During the receiver training period, a training data pattern is received, such as alternating ones and zeros (e.g., a D10.2 pattern as is known in the art), rather than an actual data payload. The differential serial communication receiver circuit includes a differential skew compensation circuit to compensate for intrapair skew. The differential skew compensation circuit receives a pair of complementary differential input signals including a noninverting input signal and an inverting input signal, and in response generates a skew compensated first differential output signal and a skew compensated second differential output signal. The differential skew compensation circuit compares the relative delay of the skew compensated first differential output signal and the skew compensated second differential output signal, and in response delays at least one of the noninverting input signal or the inverting input signal to reduce intrapair skew. | 05-14-2009 |
20110060847 | METHOD AND APPARATUS FOR TRANSPORTING AND INTEROPERATING TRANSITION MINIMIZED DIFFERENTIAL SIGNALING OVER DIFFERENTIAL SERIAL COMMUNICATION TRANSMITTERS - A differential serial communication transmitter (i.e. PCI Express or other suitable type of transmitter) can be used to transport and interoperate transition minimized differential signaling. The differential serial communication transmitter control logic receives display configuration control data and in response configures at least one differential serial communication transmitter of a plurality of differential serial communication transmitters in an integrated circuit for communication with a display (i.e. visual digital display) employing transition minimized differential signaling. For example, the integrated circuit, such as a graphics processor, may include the plurality of differential serial communication transmitters for communication with devices, such as a northbridge circuit and a display within a computer system. The differential serial communication transmitter control logic may configure at least one of the plurality of differential serial communication transmitters for communication with the display via a differential serial communication display link (i.e. DVI or other suitable type of link). The plurality of differential serial communication transmitters may also be configured for communication with one or more other devices, such as with a bridge circuit such as a northbridge. | 03-10-2011 |
20110066778 | METHOD AND APPARATUS FOR TRANSPORTING AND INTEROPERATING TRANSITION MINIMIZED DIFFERENTIAL SIGNALING OVER DIFFERENTIAL SERIAL COMMUNICATION TRANSMITTERS - A differential serial communication transmitter (i.e. PCI Express or other suitable type of transmitter) can be used to transport and interoperate transition minimized differential signaling. The differential serial communication transmitter control logic receives display configuration control data and in response configures at least one differential serial communication transmitter of a plurality of differential serial communication transmitters in an integrated circuit for communication with a display (i.e. visual digital display) employing transition minimized differential signaling. For example, the integrated circuit, such as a graphics processor, may include the plurality of differential serial communication transmitters for communication with devices, such as a northbridge circuit and a display within a computer system. The differential serial communication transmitter control logic may configure at least one of the plurality of differential serial communication transmitters for communication with the display via a differential serial communication display link (i.e. DVI or other suitable type of link). The plurality of differential serial communication transmitters may also be configured for communication with one or more other devices, such as with a bridge circuit such as a northbridge. | 03-17-2011 |
Patent application number | Description | Published |
20080245555 | CIRCUIT SUBSTRATE WITH PLATED THROUGH HOLE STRUCTURE AND METHOD - A circuit substrate includes an outer plated through hole structure and an inner plated through hole structure located within the outer plated through hole structure. In one example, the circuit substrate includes a core and an outer plated through hole structure having a first metal layer configured over the core to form an outer plated through hole. The circuit substrate also includes an inner plated through hole structure located within the outer plated through hole structure having a second metal layer positioned inside of the outer plated through hole with an insulation layer interposed between the first and second metal layers. Methods for making such a circuit substrate are also described. | 10-09-2008 |
20090032971 | Die Stacking Apparatus and Method - Various stacked semiconductor devices and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor die that has a first bulk semiconductor side and a first opposite side. A second semiconductor die is provided that has a second bulk semiconductor side and a second opposite side. The second opposite side of the second semiconductor die is coupled to the first opposite side of the first semiconductor die. Electrical connections are formed between the first semiconductor die and the second semiconductor die. | 02-05-2009 |
20090278264 | Semiconductor Chip Bump Connection Apparatus and Method - Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad. | 11-12-2009 |
20100140798 | SEMICONDUCTOR CHIP BUMP CONNECTION APPARATUS AND METHOD - Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad. | 06-10-2010 |
20100320599 | DIE STACKING APPARATUS AND METHOD - Various stacked semiconductor devices and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor die that has a first bulk semiconductor side and a first opposite side. A second semiconductor die is provided that has a second bulk semiconductor side and a second opposite side. The second opposite side of the second semiconductor die is coupled to the first opposite side of the first semiconductor die. Electrical connections are formed between the first semiconductor die and the second semiconductor die. | 12-23-2010 |
Patent application number | Description | Published |
20080197477 | Flip-Chip Grid Ball Array Strip and Package - The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units. The use of a retention wall of a stiffener layer over an expensive substrate layer allows for the use of disposable edges around the strip including indexing holes or other holding mechanisms. What is also contemplated is a method of manufacture of a compact strip, matrix, or array comprised of a plurality of integrated circuit packages where no waste or additional cuts are needed to produce individual integrated circuit packages. | 08-21-2008 |
20090218689 | FLIP CHIP SEMICONDUCTOR ASSEMBLY WITH VARIABLE VOLUME SOLDER BUMPS - A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column bumps to a corresponding substrate-pad to form a subassembly; and reflowing the subassembly so that the column bumps form robust electrical and mechanical connections between the die pads and the substrate pads. | 09-03-2009 |
20120127689 | INTEGRATED PACKAGE CIRCUIT WITH STIFFENER - The present disclosure relates to an improved integrated circuit package and method with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units. | 05-24-2012 |