Efland, US
Greg Efland, Palo Alto, CA US
Patent application number | Description | Published |
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20110176527 | SHARED ANTENNA CONTROL - A scheme for sharing antenna control pins in a wireless communications device implemented on a single CMOS integrated circuit is described. By providing a routing circuit for coupling the antenna control signal to the appropriate transceiver circuitry in a multi-transceiver system, antenna control signals may be efficiently processed using a minimum of pins on the wireless communication device. | 07-21-2011 |
Kris Efland, Palo Alto, CA US
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20150199503 | METHOD AND APPARATUS FOR PROVIDING SECURITY WITH A MULTI-FUNCTION PHYSICAL DIAL OF A COMMUNICATION DEVICE - A method, apparatus and computer program product are provided to facilitate controlled access to a communication device in accordance with predefined security levels in an independent manner that does not require a network connection. In the context of a method, a combination lock code is associated with a predefined security level for the communication device. The method also includes receiving input indicative of rotation of a multi-function physical dial carried by the communication device. The method also determines whether the input corresponds to the combination lock code and, in an instance in which the input does correspond to the combination lock code, permits access to the communication device in a manner consistent with the predefined security level. | 07-16-2015 |
Taylor Efland, Richardson, TX US
Patent application number | Description | Published |
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20140197486 | POWER INTEGRATED CIRCUIT INCLUDING SERIES-CONNECTED SOURCE SUBSTRATE AND DRAIN SUBSTRATE POWER MOSFETS - A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region parallel to channel current flow. The RESURF trenches have dielectric liners and electrically conductive RESURF elements on the liners. Source contact metal is disposed over the body region and source regions. A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer, and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region perpendicular to channel current flow. Source contact metal is disposed in a source contact trench and extended over the drain drift region to provide a field plate. | 07-17-2014 |
20150145036 | POWER INTEGRATED CIRCUIT INCLUDING SERIES-CONNECTED SOURCE SUBSTRATE AND DRAIN SUBSTRATE POWER MOSFETS - A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region parallel to channel current flow. The RESURF trenches have dielectric liners and electrically conductive RESURF elements on the liners. Source contact metal is disposed over the body region and source regions. A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer, and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region perpendicular to channel current flow. Source contact metal is disposed in a source contact trench and extended over the drain drift region to provide a field plate. | 05-28-2015 |
Taylor R. Efland, Richardson, TX US
Patent application number | Description | Published |
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20090115053 | Semiconductor Package Thermal Performance Enhancement and Method - A semiconductor device package and related method are disclosed for providing a semiconductor device encapsulated in a protective package body. The device has an exposed surface to which a thermal compound is applied for improving a thermal path for the egress of heat from the device. Preferred embodiments are disclosed in which a removable cover is attached to the thermal compound for further improved protection during handling. | 05-07-2009 |
20110024895 | Semiconductor Package Thermal Performance Enhancement and Method - A semiconductor device package and related method are disclosed for providing a semiconductor device encapsulated in a protective package body. The device has an exposed surface to which a thermal compound is applied for improving a thermal path for the egress of heat from the device. Preferred embodiments are disclosed in which a removable cover is attached to the thermal compound for further improved protection during handling. | 02-03-2011 |
20120086112 | Multi-Component Electronic System Having Leadframe with Support-Free Cantilever Leads | 04-12-2012 |
Taylor Rice Efland, Richardson, TX US
Patent application number | Description | Published |
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20090256212 | LATERAL DRAIN-EXTENDED MOSFET HAVING CHANNEL ALONG SIDEWALL OF DRAIN EXTENSION DIELECTRIC - An integrated circuit ( | 10-15-2009 |
20100252882 | MOS Transistor with Gate Trench Adjacent to Drain Extension Field Insulation - An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer. | 10-07-2010 |
20110108914 | MOS TRANSISTOR WITH GATE TRENCH ADJACENT TO DRAIN EXTENSION FIELD INSULATION - An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer. | 05-12-2011 |
20110111569 | MOS TRANSISTOR WITH GATE TRENCH ADJACENT TO DRAIN EXTENSION FIELD INSULATION - An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer. | 05-12-2011 |
20110151634 | LATERAL DRAIN-EXTENDED MOSFET HAVING CHANNEL ALONG SIDEWALL OF DRAIN EXTENSION DIELECTRIC - An integrated circuit ( | 06-23-2011 |