Chu, Kaohsiung City
Ann-Kuo Chu, Kaohsiung City TW
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20110052202 | HDMI OPTICAL TRANSCEIVER - An HDMI optical transceiver comprises an optical bench, at least one light emitter disposed on the optical bench, at least one first fiber assembly, at least one photodetector disposed on the optical bench and at least one second fiber assembly. The optical bench has a surface, at least one first groove recessed from the surface and at least one second groove recessed from the surface. The light emitter has a light-emitting surface. The first fiber assembly is disposed at the first groove of the optical bench and comprises a first sleeve fixed at the first groove and a first optical fiber which is disposed in the first sleeve and aligned with the light-emitting surface. The photodetector has a light-receiving surface. The second fiber assembly is disposed at the second groove of the optical bench and comprises a second sleeve fixed at the second groove and a second optical fiber which is disposed in the second sleeve and aligned with the light-receiving surface. | 03-03-2011 |
Bo Yu Chu, Kaohsiung City TW
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20160005415 | AUDIO SIGNAL PROCESSING APPARATUS AND AUDIO SIGNAL PROCESSING METHOD THEREOF - An audio signal processing apparatus and an audio signal processing method thereof are provided. The audio signal processing apparatus is configured to receive an audio signal and divide the audio signal into a plurality of frames. The audio signal processing apparatus is also configured to apply Fourier Transform on each of the frames to obtain a plurality of acoustic spectra. The audio signal processing apparatus is also configured to apply Fourier Transform again on each of component combinations corresponding to respective acoustic frequencies in these acoustic spectra to obtain a two-dimensional joint frequency spectrum. The two-dimensional joint frequency spectrum has an acoustic frequency dimension and a modulation frequency dimension. The audio signal processing apparatus is also configured to calculate at least one feature of the audio signal according to the two-dimensional joint frequency spectrum. | 01-07-2016 |
Cheng-Jye Chu, Kaohsiung City TW
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20110180788 | COMPOUND SEMICONDUCTOR THIN FILM WITH ANTI-FOG FUNCTION AND THE MANUFACTURING METHOD THEREOF - The disclosure is a compound semiconductor thin film with anti-fog function and the manufacturing method thereof. The thin film at least includes a dense semiconductor thin film combined with a porous-needle semiconductor thin film. The disclosed compound semiconductor thin film decreases the contact angle of water and achieves hydrophilic and anti-fog properties for a long lifetime. | 07-28-2011 |
Chien-Tzu Chu, Kaohsiung City TW
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20090114918 | PANEL STRUCTURE AND MANUFACTURING METHOD THEREOF - A panel structure and a manufacturing method thereof are provided. The panel structure is disposed in a display device. The panel structure includes a substrate, several first transistors and second transistors. The substrate has a display circuit and a control circuit. The first transistors are disposed at the display circuit of the substrate. Each of the first transistors has a first active layer. The second transistors are disposed at the control circuit of the substrate. Each of the second transistors has a second active layer. The materials of at least one of the first active layer and the second active layer include ZnO. | 05-07-2009 |
Ching-Hua Chu, Kaohsiung City TW
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20130200442 | SALICIDE FORMATION USING A CAP LAYER - A semiconductor device having a source feature and a drain feature formed in a substrate. The semiconductor device having a gate stack over a portion of the source feature and over a portion of the drain feature. The semiconductor device further having a first cap layer formed over substantially the entire source feature not covered by the gate stack, and a second cap layer formed over substantially the entire drain feature not covered by the gate stack. A method of forming a semiconductor device including forming a source feature and drain feature in a substrate. The method further includes forming a gate stack over a portion of the source feature and over a portion of the drain feature. The method further includes depositing a first cap layer over substantially the entire source feature not covered by the gate stack and a second cap layer over substantially the entire drain feature not covered by the gate stack. | 08-08-2013 |
20130234217 | MOS Devices Having Non-Uniform Stressor Doping - A device includes a semiconductor substrate, a gate stack over the semiconductor substrate, and a stressor region having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor region includes a first stressor region having a first p-type impurity concentration, a second stressor region over the first stressor region, wherein the second stressor region has a second p-type impurity concentration, and a third stressor region over the second stressor region. The third stressor region has a third p-type impurity concentration. The second p-type impurity concentration is lower than the first and the third p-type impurity concentrations. | 09-12-2013 |
Chi-Wen Chu, Kaohsiung City TW
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20150114821 | Method for Modifying Properties of Graphene - A method for modifying properties of graphene includes a graphene film provision step and a modification step. In the graphene film provision step, a graphene film is provided, and the graphene is formed on a substrate. In the modification step, the graphene film is placed in a vacuum environment and radiated by an electron beam to obtain a graphene material. | 04-30-2015 |
Fang-Hsien Chu, Kaohsiung City TW
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20130169497 | COMMUNICATION DEVICE AND ANTENNA STRUCTURE THEREIN - A communication device includes an antenna structure, wherein the antenna structure includes a ground element and an antenna element. One edge of the ground element has a notch, and the notch is extended into the interior of the ground element to form a slot region. The slot region is substantially extended along the edge of the ground element. The antenna element includes a first radiating portion and a second radiating portion. The first radiating portion is disposed in the slot region and is excited to form at least a resonant mode in the first operating band of the antenna element. The second radiating portion is an open-slot antenna and is formed by the slot region. The second radiating portion is excited to form a resonant mode in the second operating band of the antenna element. | 07-04-2013 |
20130300615 | COMMUNICATION DEVICE AND ANTENNA STRUCTURE THEREIN - A communication device including a multilayer circuit board and an antenna structure therein is provided. The multilayer circuit board has at least a first plane, a second plane, and a third plane. A ground plane is disposed on one of the planes, and the ground plane is in proximity to a clearance region of the multilayer circuit board. An antenna structure is disposed in the clearance region. The antenna structure includes a first metal portion and a second metal portion. The first metal portion is coupled to a signal source through a feeding portion. The second metal portion includes at least a first line segment and a second line segment. The first line segment and the second line segment are disposed respectively on any two planes of the multilayer circuit board. The first metal line and the second metal line forms a loop structure through two conductive vias. | 11-14-2013 |
20140125536 | COMMUNICATION DEVICE AND WIDE-BAND ANTENNA ELEMENT THEREIN - A communication device including a ground element and an antenna element is provided. The antenna element is disposed adjacent to the ground element. The antenna element includes a first radiation element and a second radiation element. The first radiation element includes a first portion and a second portion. The first portion is coupled through an inductive element to the second portion. The first portion is coupled to a signal source. The second portion includes a plurality of bends such that a coupling gap is formed between an open end of the second portion and the first portion. The second radiation element has a shorted end and an open end. The shorted end of the second radiation element is coupled to the ground element. The second radiation element extends and at least partially surrounds the first radiation element. | 05-08-2014 |
Hsin-Kun Chu, Kaohsiung City TW
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20160031056 | Method of fault detection and classification (FDC) for improved tool control capabilities - A method of a fault detection and classification (FDC) may be used to determine outlier tools from a plurality of tools. The method includes generating a plurality of parameter charts, generating a plurality of group charts according to the plurality of parameter charts, generating a score table according to the plurality of group charts, determining outlier tools according to the score table, and performing tool correction on the outlier tools. | 02-04-2016 |
Hung-Chi Chu, Kaohsiung City TW
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20080309608 | DC-DC converter with temperature compensation circuit - A DC-DC converter includes a temperature compensation circuit arranged between a feedback differential amplification circuit and an output voltage detection circuit to compensate the variation of the voltage level of the DC output voltage of the converter caused by ambient temperature changes. The temperature compensation circuit includes a temperature detection circuit that detects the ambient temperature and, in response thereto, generates a temperature signal; and a current source circuit that is connected between a feedback signal input terminal of the feedback differential amplification circuit and the output voltage detection circuit. The current source circuit, based on the temperature signal, generates an electrical current and a compensation voltage proportional to the electrical current. The compensation voltage is applied to the DC output voltage to thereby regulate the voltage level of the DC output voltage. The temperature signal is a temperature signal of positive temperature characteristics and/or a temperature signal of negative temperature characteristics. | 12-18-2008 |
20090051338 | Constant current regulator with current sensing circuit loop - A constant current regulator includes a current sensing circuit loop connected to a switch unit of the constant current regulator to detect a current flowing through the switch unit and to generate a detection current that is in proportion to the current flowing through the switch unit. The detection current flows through a detection resistor to induce a detection voltage. A differential amplifier bases on a set voltage and the received detection voltage to generate an error voltage to a pulse width modulation controller, which in turn causes a gate driver circuit to control the switching operation of the switch unit thereby supplying a constant current to a load connected to an output voltage of the regulator. | 02-26-2009 |
20130241423 | METHODS AND APPARATUS FOR DRIVING LED-BASED LIGHTING UNITS - A plurality of switching units interleaves with a plurality of LED-based lighting units to configure the interconnection of the LED-based lighting units for providing multiple lighting modes. Each switching unit disposed between a leading lighting unit and a trailing lighting unit is separately controlled by a controller. The switching unit can be configured to connect the two LED-based lighting units in parallel or in series, or to bypass the leading LED-based lighting unit. All the LED-based lighting units are connected in series when an input voltage supply is at a maximum voltage level, and connected in parallel when the input voltage supply is at a minimum voltage level. As the input voltage level decreases, the number of LED-based lighting units connected in parallel increases, and vice versa. | 09-19-2013 |
20130313987 | METHODS AND APPARATUS FOR SEGMENTING AND DRIVING LED-BASED LIGHTING UNITS - A plurality of LED-based lighting units is segmented into a plurality of LED-based lighting segments connected in series. Each lighting segment has a plurality of LED-based lighting units connected in series with at least a series-connection switch, and a bypass-connection switch is connected in parallel with the series of LED-based lighting units. The total number of LED-based lighting units can be determined by a maximum voltage level of an input voltage supply and the forward voltage of the LED-based lighting unit for achieving optimal efficiency. The number of lighting segments and the number of lighting units in each lighting segment are properly chosen based on the total number of the LED-based lighting units in such away that any number up to the total number of all the LED-based lighting units can be connected in series by respectively controlling the series-connection switch and the bypass-connection switch of each LED-based lighting segment. | 11-28-2013 |
20140055050 | APPARATUS FOR DRIVING A PLURALITY OF SEGMENTS OF LED-BASED LIGHTING UNITS - An LED-based lighting apparatus includes a plurality of LED-based lighting segments connected in series with a current control device. Each lighting segment has at least one LED-based lighting unit connected in series. A plurality of switch controllers controlled by a switching voltage comparator unit is connected with the plurality of LED-based lighting segments to provide multiple operation modes for turning on different number of LED-based lighting segments. In one embodiment, each switch controller is connected in parallel with a corresponding segment. The switching voltage comparator unit generates a propagation signal that propagates through and controls the plurality of switch controllers. In the other embodiment, each switch controller is connected between a positive end of the corresponding segment and a current control device. The switching voltage comparator unit generates two propagation signals that propagate through and control the plurality of switch controllers. | 02-27-2014 |
20140159593 | APPARATUS HAVING UNIVERSAL STRUCTURE FOR DRIVING A PLURALITY OF LED STRINGS - An apparatus comprises a plurality of controllable LED strings interposed with a plurality of switching units with each switching unit being connected between a leading controllable LED string and a trailing controllable LED string. A controller controls the switching units so that controllable LED strings are connected in a combination of series and parallel connections by connecting two adjacent leading and trailing controllable LED strings in series or parallel or by-passing the leading controllable LED string based on an automatically detected input voltage range. Each controllable LED string includes a plurality of LEDs connected in series between positive and negative ends of the controllable LED string and a plurality of controlling switches each corresponding to an LED. The number of LEDs connected in series in each controllable LED string is further adjusted by the controller as the input voltage varies with time. | 06-12-2014 |
Hung-Sung Chu, Kaohsiung City TW
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20100321099 | EFFICIENCY AND THERMAL IMPROVEMENT OF A CHARGE PUMP BY MIXING DIFFERENT INPUT VOLTAGES - For a charge pump, a control circuit switches two or more input voltages to apply to one or more pumping capacitors under auto-sensing control to modulate a maximum pumping voltage as close as to a demanded output voltage to thereby reduce the difference between the maximum pumping voltage and the output voltage for efficiency and thermal improvement of the charge pump. The maximum pumping voltage is produced by mixing the different input voltages and the charge pump may provide more operation modes. | 12-23-2010 |
Jenn Lien Chu, Kaohsiung City TW
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20090150380 | SYSTEM AND METHOD FOR PROCESSING SOCIAL RELATION ORIENTED SERVICE - A method for social relationship oriented service processing, which comprises steps of: providing relationship data, searching for at least one first level social member from a first level social network according to the relationship data, forwarding a list of the first level social members to a server, and searching by the server for at least one second level social member from a second level social network according to the list and the relationship data. | 06-11-2009 |
20140189101 | AUTO-CONFIGURATION SERVER AND MANAGEMENT METHOD OF CUSTOMER PREMISES EQUIPMENTS - An auto-configuration server (ACS) and a management method of customer premises equipments (CPEs) thereof are provided, and the ACS includes a sub server communication module and a group management module. When an online message is received from a new CPE, the management method includes performing an extension procedure including the following steps. A health value of the ACS is calculated. When the health value of the ACS is less than or equal to a health threshold, a new group and a sub server corresponding to the new group are added and the new CPE is managed by the sub server corresponding to the new group. | 07-03-2014 |
Jiing Shiuh Chu, Kaohsiung City TW
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20120038687 | Driving Method To Neutralize Grey Level Shift For Electrophoretic Displays - The present invention provides driving methods for a display having a binary color system of a first color and a second color, which methods can effectively neutralize the grey level shifts due to degradation of a display medium. | 02-16-2012 |
Jiun-Sian Chu, Kaohsiung City TW
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20090249396 | METHOD OF SHARING CHANNEL INFORMATION AND RELATED DEVICE - To provide convenience to usage of an electronic program guide, known as EPG, the present invention provides a method of sharing channel information for a client device coupled to a server including a plurality of communities. The method includes the following steps. A plurality of channels is received to generate a first program list. Community information corresponding to the device is obtained. One of the communities of the server is selected according to the community information. The first program list is then uploaded to the selected community. | 10-01-2009 |
20130300823 | STEREO EFFECT ENHANCEMENT SYSTEMS AND METHODS - In one embodiment, a stereo effect enhancement method, comprising: receiving a first multimedia stream and a second multimedia stream, the second multimedia stream comprising a second frame at a second depth and the first multimedia stream comprising a first frame at a first depth that is to be presented within the second frame; adjusting a difference between the first and second depths by reducing parallax between the first and second frames; and adding a border around the first frame, wherein the adjusting and adding provide a more visually satisfying presentation of stereoscopic content corresponding to the first and second frames, the receiving, adjusting, and adding performed by a processor. | 11-14-2013 |
Kao-Hone Chu, Kaohsiung City TW
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20120290186 | MULTIPLEX CONTROL SYSTEM, TRANSPORT DEVICE HAVING MULTIPLEX CONTROL SYSTEM, AND CONTROL METHOD THEREOF - A conveying device includes a multiplexing control device and power wheels, and the multiplexing control device includes sensors, a bus, a first controller and a second controller. The sensors are used to receive travelling information and output sensing signals. The bus is used to receive the sensing signals and output the sensing signals to the first controller and the second controller. When the conveying device operates, the first controller controls the power wheels according to the sensing signals. If the sensing signals are too complicated, the second controller performs processing together with the first controller. If the first controller is damaged, the second controller replaces the first controller and controls the power wheels according to the sensing signals. | 11-15-2012 |
Lin-Abel Chu, Kaohsiung City TW
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20140327650 | TOUCH PANEL WHICH PROVIDES ACCURATE AND EFFICIENT TOUCH OPERATIONS - A capacitive touch panel includes an effective detecting region having a plurality of non-overlapping detecting sections. A main sensor is disposed in the effective detecting region. An auxiliary sensor is disposed in at least one detecting section for differentiating an actual touch coordinate from a ghost finger coordinate. | 11-06-2014 |
Lin-Chih Chu, Kaohsiung City TW
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20150350964 | MOBILE COMMUNICATIONS DEVICES AND METHODS FOR INTER-RADIO ACCESS TECHNOLOGY PERFORMANCE ENHANCEMENT - A method for inter-radio access technology (inter-RAT) performance enhancement in a mobile communications device is provided. First, a first RAT is camped on to perform a first service. Thereafter, it is moved/fallen back to a second RAT from the first RAT to perform a second service. Cell information of the first RAT is then measured and collected during the performance of the second service in the second RAT. A first cell to return to the first RAT is determined according to the collected cell information of the first RAT after a call connection of the second RAT is released. | 12-03-2015 |
Pin-Chien Chu, Kaohsiung City TW
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20120094460 | METHOD FOR FABRICATING MOS TRANSISTORS - A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and epitaxial layer is grown in each of the two recesses. By thinning the spacer before the epitaxial layer is formed, the present invention could stop the epitaxial layer to grow against the sidewall of the spacer, thereby preventing problem such as Ion degradation. | 04-19-2012 |
Po-Chia Chu, Kaohsiung City TW
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20150032944 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A FLASH memory control technique with wear leveling between the different blocks of the FLASH memory. By a controller managing the blocks of a FLASH memory within a data storage device, some of the blocks are pushed into a spare queue waiting to be allocated as data blocks or system blocks and some blocks are pushed into a jail queue to be inaccessible. When the jail queue is full and any block within the spare queue has an erase count greater than any block within the jail queue, for wear leveling between the different blocks within the FLASH memory, the controller releases a first block selected from the jail queue and pushes a second block selected from the spare queue into the jail queue. | 01-29-2015 |
20150067239 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A FLASH memory control technique with wear leveling between the different blocks of the FLASH memory. By a controller managing the blocks of a FLASH memory within a data storage device, some of the blocks are pushed into a spare queue waiting to be allocated as data blocks or system blocks. When the number of blocks within the spare queue is lower than a clean threshold and any block within the spare queue has an erase count greater than an overused lower threshold, the controller performs a garbage correction operation with wear leveling between the different blocks. | 03-05-2015 |
20150261671 | GARBAGE COLLECTION METHOD FOR FLASH MEMORY - A garbage collection method for a flash memory is provided. The flash memory includes a spare block pool and a data block pool, wherein the spare block pool includes spare blocks and the data block pool includes data blocks. The method includes the steps of: receiving target data from a host and writing the target data to a current data block of the data blocks; sorting an erase count of each data block when performing a wear-leveling process to write the target data; sorting a valid page number of each first block when it is determined that at least two first blocks in the data blocks have the smallest erase count; and selecting a second block having a smallest valid page number from the first blocks and writing valid pages of the second block to one of the spare blocks to perform a data cleaning process. | 09-17-2015 |
Po-Han Chu, Kaohsiung City TW
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20130023252 | METHODS FOR PROVIDING SERVING NETWORK INFORMATION AND COMMUNICATIONS APPARATUSES UTILIZING THE SAME - A communications apparatus is provided. A processor is coupled to a subscriber identity card and a radio transceiver module. The subscriber identity card camps on a cell operating in a serving network having a serving network identifier via the radio transceiver module. The processor at least includes a first processor logic unit obtaining information regarding the serving network identifier, a second processor logic unit carrying the information regarding the serving network identifier in a message to be transmitted to the serving network, and a third processor logic unit transmitting the message to the serving network via the radio transceiver module. | 01-24-2013 |
Shih-Tsun Chu, Kaohsiung City TW
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20130054134 | TELEMATICS APPARATUS FOR DRIVING ASSISTANCE, SYSTEM OF THE SAME, AND METHOD OF THE SAME - A telematics apparatus for providing driving assistance, and a system and a method are provided. The telematics apparatus receives position information indicating a current position of the telematics apparatus. The telematics apparatus transmits a request signal to the server. According to the request signal, the server obtains the position information, time information indicating a current time of the telematics apparatus, and identification information identifying a user of the telematics apparatus. The telematics apparatus displays driving assistance information received from the server which generates the driving assistance information according to the identification information, the position information, and the time information by searching through a route usage history of a plurality of routes and referring to a plurality of reference values of the routes. The reference value of each route indicates the telematics apparatus user's familiarity with that route. | 02-28-2013 |
Tai Chi Chu, Kaohsiung City TW
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20080308405 | Optical Fiber Photocatalytic Reactor And Process For The Decomposition Of Nitrogen Oxide Using Said Reactor - An optical fiber photocatalytic reactor is provided. The reactor comprises a reaction zone and multiple fibers located in the reaction zone. The fiber comprises a photocatalyst that is coated onto its surface via a thermal hydrolysis method. The adhesion between the fiber and the photocatalyst thereon is strong, and thus, the delamination of the photocatalyst film on the fiber can be prevented. Moreover, the optical fiber photocatalytic reactor is useful for the decomposition of nitrogen oxide which is one of air's most harmful contaminants. The present invention exhibits a high conversion of nitrogen oxide. | 12-18-2008 |
Tun-Hsiao Chu, Kaohsiung City TW
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20110118621 | MUSCULAR ENERGY STATE ANALYSIS SYSTEM AND METHOD FOR SWING MOTION AND COMPUTER PROGRAM PRODUCT THEREOF - A muscular energy state analysis system and method for a swing motion and a computer program product thereof are provided. The system includes: a swing implement, for a user to perform the swing motion, and including an acceleration sensor for sensing acceleration of the swing implement when the swing implement is swung, so as to generate a swing speed data; a plurality of signal detection modules, for detecting electromyographic (EMG) signals generated by a muscles of the user; a database, for storing a muscular energy sample value; a muscular energy analysis module, for analyzing the EMG signals and the swing speed data so as to obtain a plurality of muscular performance values; and a comparison module, for comparing the swing speed data and the muscular performance values with the at least one muscular energy sample value in the database, so as to generate a comparison result data. | 05-19-2011 |
20130116801 | SYSTEM, METHOD AND RECORDING MEDIUM FOR DRIVING A PROGRAMMABLE LOGIC CONTROLLER - A system, a method and a recording medium for driving a programmable logic controller are disclosed. This system includes a server and an adaptive unit electrically connected to the server. When determining that a programmable logic controller is connected, a hardware layer management module of the adaptive unit informs the server. The server outputs a controller query data to query the programmable logic controller through the hardware layer management module. The server generates a control data conforming to a specification of the programmable logic controller according to a controller response data of the programmable logic controller, for the hardware layer management module to control the programmable logic controller. | 05-09-2013 |
Wei-Lin Chu, Kaohsiung City TW
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20130167621 | BIOLOGICAL DETECTION DEVICE AND DETECTING METHOD - The present invention discloses a biological detection device and a detecting method. The biological detection device comprises a substrate, an electric field unit, a liquid crystal/polymer composite film (LCPCF), a power supply, a processing unit, and an image sensor. Because of the electrically tunable orientations of the liquid crystal (LC) director anchored among the polymer grains, the wettability of the LCPCF changes with an applied electric field. As a result, we can manipulate a blood droplet on the LCPCF by a wettability gradient owing to the distribution of LC directors on the LCPCF. The motion states of the blood droplet can be related to the various qualities of the blood, and finally determines the health of the test sample. The change of contact angle of blood on LCPCF and the blood droplet motion on LCPCF indicate the concentration of TG and the concentration of HDL. | 07-04-2013 |
Wen-Chung Chu, Kaohsiung City TW
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20120132854 | LIQUID CRYSTAL COMPOUND AND LIQUID CRYSTAL MIXTURE - A LC compound and a LC mixture are provided. The LC mixture includes a compound represented by (I) and at least one compound selected from a group consisting of compounds represented by (II) to (IV): | 05-31-2012 |
Wen-Ting Chu, Kaohsiung City TW
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20090051413 | APPARATUS AND METHOD FOR INCREASING CHARGE PUMP EFFICIENCY - A charge pump circuit is provided which includes at least two charge pump stages connected in series with a front charge pump stage having a first transistor for receiving an input voltage and a last charge pump stage having a second transistor for providing an output voltage. The first transistor is configured to operate at a first threshold voltage and the second transistor is configured to operate at a second threshold voltage different than the first threshold voltage. | 02-26-2009 |
20140091272 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a conductive structure. The resistance variable memory structure is over the conductive structure. The resistance variable memory structure includes a first electrode over the conductive structure. A resistance variable layer is disposed over the first electrode. A cap layer is disposed over the resistance variable layer. The cap layer includes a first metal material. A second electrode disposed over the cap layer. The second electrode includes a second metal material different from the first metal material. | 04-03-2014 |
20140131650 | RESISTANCE VARIABLE MEMORY STRUCTURE - A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer. | 05-15-2014 |
20140131651 | LOGIC COMPATIBLE RRAM STRUCTURE AND PROCESS - A memory cell and method including a first electrode conformally formed through a first opening in a first dielectric layer, a resistive layer conformally formed on the first electrode, a second electrode conformally formed on the resistive layer, and a second dielectric layer conformally formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer is formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond a region defined by the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the region defined by the first opening. The second electrode is coupled to a second metal layer using a via that extends through the second opening. | 05-15-2014 |
20140131654 | LOGIC COMPATIBLE RRAM STRUCTURE AND PROCESS - A memory cell and method including a first electrode conformally formed through a first opening in a first dielectric layer, a resistive layer conformally formed on the first electrode, a spacing layer conformally formed on the resistive layer, a second electrode conformally formed on the resistive layer, and a second dielectric layer conformally formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer is formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening. | 05-15-2014 |
20140166961 | RESISTIVE RANDOM ACCESS MEMORY (RRAM) AND METHOD OF MAKING - The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure electrically connected to the transistor. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer over the bottom electrode and having a same width as the top portion of the bottom electrode, and a top electrode over the resistive material layer and having a smaller width than the resistive material layer. | 06-19-2014 |
20140175365 | RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE AND METHOD OF MAKING THE RRAM STRUCTURE - The present disclosure provides a resistive random access memory (RRAM) cell. The RRAM cell includes a transistor, a bottom electrode adjacent to a drain region of the transistor and coplanar with the gate, a resistive material layer on the bottom electrode, a top electrode on the resistive material layer, and a conductive material connecting the bottom electrode to the drain region. | 06-26-2014 |
20140175366 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer. | 06-26-2014 |
20140247644 | Resistive Memory Reset - A resistive memory cell includes a switch and a resistive switching device. The switch includes a first terminal connected to a select line and a gate terminal connected to a word line. The resistive switching device is connected between a second terminal of the switch and a bit line. The resistive switching device is resettable by having a positive bias applied to the word line and a negative bias applied to the bit line. | 09-04-2014 |
20140252297 | Resistive Memory Cell Array with Top Electrode Bit Line - A method for forming a resistive memory cell within a memory array includes forming a patterned stopping layer on a first metal layer formed on a substrate and forming a bottom electrode into features of the patterned stopping layer. The method further includes forming a resistive memory layer. The resistive memory layer includes a metal oxide layer and a top electrode layer. The method further includes patterning the resistive memory layer so that the top electrode layer acts as a bit line within the memory array and a top electrode of the resistive memory cell. | 09-11-2014 |
20140264222 | Resistive Switching Random Access Memory with Asymmetric Source and Drain - The present disclosure provides one embodiment of a resistive random access memory (RRAM) structure. The RRAM structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage; and a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element. The FET includes asymmetric source and drain. The resistive element includes a resistive material layer and further includes first and second electrodes interposed by the resistive material layer. | 09-18-2014 |
20140264233 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround at least the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode. The second electrode is disposed over the resistance variable layer. | 09-18-2014 |
20140264234 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, a protection material and a second electrode. The first electrode has a top surface on the memory region. The resistance variable layer has at least a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection material surrounds the second portion of the resistance variable layer. The protection material is configurable to protect at least one conductive path in the resistance variable layer. The second electrode is disposed over the resistance variable layer. | 09-18-2014 |
20140264534 | ARCHITECTURE TO IMPROVE CELL SIZE FOR COMPACT ARRAY OF SPLIT GATE FLASH CELL - Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing isolated source regions that are diffused only in the active regions between the stacked control gate structures. The architecture contains no CS under the isolation region, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. A metal layer is disposed along the semiconductor body above the common source regions to provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. Hence, this particular architecture reduces the resistance and the metal connection over several cells in an array suppresses the area over head. | 09-18-2014 |
20150069315 | RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - One embodiment in the present disclosure provides a resistor in a resistive random access memory (RRAM). The resistor includes a first electrode; a resistive layer on the first electrode; an electric field enhancement array in the resistive layer; and a second electrode on the resistive layer. The electric field enhancement array includes a plurality of electric field enhancers arranged in a same plane. One embodiment in the present disclosure provides a method of manufacturing a resistor structure in an RRAM. The method comprises (1) forming a first resistive layer on a first electrode; (2) forming a metal layer on the resistive layer; (3) patterning the metal layer to form a metal dot array on the resistive layer; and (4) forming a second electrode on the metal dot array. The metal dot array comprises a plurality of metal dots, and a distance between adjacent metal dots is less than 40 nm. | 03-12-2015 |
20150069316 | RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor structure which includes a conductive layer and a resistance configurable structure over the conductive layer. The resistance configurable structure includes a first electrode, a resistance configurable layer over the first electrode, and a second electrode over the resistance configurable layer. The first electrode has a first sidewall, a second sidewall, and a bottom surface on the conductive layer. A joint between the first sidewall and the second sidewall includes an electric field enhancement structure. The present disclosure also provides a method for manufacturing the above semiconductor structure, including patterning a hard mask on a conductive layer; forming a spacer around the hard mask; removing at least a portion of the hard mask; forming a conforming resistance configurable layer on the spacer; and forming a second conductive layer on the conforming resistance configurable layer. | 03-12-2015 |
20150090949 | RRAM CELL STRUCTURE WITH LATERALLY OFFSET BEVA/TEVA - The present disclosure relates to a resistive random access memory (RRAM) cell architecture, with off-axis or laterally offset top electrode via (TEVA) and bottom electrode via (BEVA). Traditional RRAM cells having a TEVA and BEVA that are on-axis can cause high contact resistance variations. The off-axis TEVA and BEVA in the current disclosure pushes the TEVA away from the insulating layer over the RRAM cell, which can improve the contact resistance variations. The present disclosure also relates to a memory device having a rectangular shaped RRAM cell having a larger area that can lower the forming voltage and improve data retention. | 04-02-2015 |
20150092471 | MEMORY CELLS BREAKDOWN PROTECTION - A method is disclosed that includes the operations outlined below. A first voltage is applied to a gate of an access transistor of each of a row of memory cells during a reset operation, wherein a first source/drain of the access transistor is electrically connected to a first electrode of a resistive random access memory (RRAM) device in the same memory cell. An inhibition voltage is applied to a second electrode of the RRAM device or to a second source/drain of the access transistor of each of a plurality of unselected memory cells when the first voltage is applied to the gate of the access transistor. | 04-02-2015 |
20150109850 | MEMORY DEVICES - A device is disclosed that includes an I/O memory block. The I/O memory block includes memory cells, bit lines and a source line. The number of the formed bit lines is at least 4. The bit lines and the source line are electrically connected to the memory cells. In the I/O memory block, the source line and the bit lines are configured to provide logical data to the memory cells. | 04-23-2015 |
20150131361 | MEMORY DEVICE - A device includes a storage region, and a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array is disclosed herein. The storage region includes a first storage array and a second storage array. The first storage array includes a plurality of first storage cells. The second storage array includes a plurality of second storage cells. The second storage cells are configured to be in place of the first storage cells. The RRAM-based non-volatile storage array is configured to record at least one corresponding relationship between the first storage cells and the second storage cells. | 05-14-2015 |
20150144859 | Top Electrode Blocking Layer for RRAM Device - An integrated circuit device including a resistive random access memory (RRAM) cell formed over a substrate. The RRAM cell includes a top electrode having an upper surface. A blocking layer covers a portion of the upper surface. A via extends above the top electrode within a matrix of dielectric. The upper surface of the top electrode includes an area that interfaces with the blocking layer and an area that interfaces with the via. The area of the upper surface that interfaces with the via surrounds the area of the upper surface that interfaces with the blocking layer. The blocking layer is functional during processing to protect the RRAM cell from etch damage while being structured in such a way as to not interfere with contact between the overlying via and the top electrode. | 05-28-2015 |
20150194602 | RRAM RETENTION BY DEPOSITING Ti CAPPING LAYER BEFORE HK HfO - The present disclosure relates to a resistance random access memory (RRAM) device architecture where a Ti metal capping layer is deposited before the deposition of the HK HfO resistance switching layer. Here, the capping layer is below the HK HfO layer, and hence no damage will occur during the top RRAM electrode etching. The outer sidewalls of the capping layer are substantially aligned with the sidewalls of the HfO layer and hence any damage that may occur during future etching steps will happen at the outer side walls of the capping layer that are positioned away from the oxygen vacancy filament (conductive filament) in the HK HfO layer. Thus the architecture in the present disclosure, improves data retention. | 07-09-2015 |
20150214276 | RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE - A resistive random access memory (RRAM) cell comprises a transistor having a gate and a source/drain region, a bottom electrode having an upper surface coplanar with a top surface of the gate, a resistive material layer on the bottom electrode, a top electrode on the resistive material layer, and a conductive material connecting the bottom electrode to the source/drain region. | 07-30-2015 |
20150287917 | HIGH YIELD RRAM CELL WITH OPTIMIZED FILM SCHEME - The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a good yield, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer, and forming a variable resistance dielectric data storage layer having a first thickness onto the bottom electrode. A capping layer is formed onto the dielectric data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 to approximately 3 times thicker than the first thickness. A top electrode is formed over the capping layer, and an upper metal interconnect layer is formed over the top electrode. | 10-08-2015 |
20150295172 | RRAM Cell with Bottom Electrode - The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for low leakage currents within the RRAM cell without using insulating sidewall spacers, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A bottom dielectric layer is disposed over the lower metal interconnect layer and/or the lower ILD layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the dielectric data storage layer onto the bottom dielectric layer increases a leakage path distance between the bottom and top electrodes, and thereby provides for low leakage current for the RRAM cell. | 10-15-2015 |
20150325786 | RRAM CELL STRUCTURE WITH LATERALLY OFFSET BEVA/TEVA - The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell. The method forms a bottom electrode over a bottom electrode via. The method further forms a variable resistive dielectric layer over the bottom electrode, and a top electrode over the variable resistive dielectric layer. The method forms a top electrode via vertically extending outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the bottom electrode via. The top electrode via has a smaller width than the top electrode. Laterally offsetting the top electrode via from the bottom electrode via provides the top electrode via with good contact resistance. | 11-12-2015 |
20150371721 | MEMORY DEVICE - A device includes a storage region, and a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array is disclosed herein. The storage region includes a first storage array and a second storage array. The first storage array includes a plurality of first storage cells. The second storage array includes a plurality of second storage cells. The second storage cells are configured to be in place of the first storage cells. The RRAM-based non-volatile storage array is configured to record at least one corresponding relationship between the first storage cells and the second storage cells. | 12-24-2015 |
20150380063 | SEMICONDUCTOR ARRANGEMENT AND METHODS OF USE - A semiconductor arrangement and method of use are provided. A semiconductor arrangement includes a resistance random access memory (RRAM) component including a source line electrically coupled to a first active area. The source line of the RRAM comprises a first metal line in parallel with a second metal line, where both the first metal line and the second metal line are electrically coupled to the first active area. The RRAM component also includes a resistor electrically coupled to a second active area. A positive bias is applied to a selected RRAM component during at least one of a set operation or reset operation while a negative bias is concurrently applied to a non-selected RRAM component of the semiconductor arrangement. | 12-31-2015 |
20150380644 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure includes depositing a first electrode material over a conductive structure and a dielectric layer, patterning the first electrode material to form a first electrode contacting the conductive structure, depositing a resistance variable layer over the first electrode and the dielectric layer, depositing a second electrode material over the resistance variable layer, and etching a portion of the second electrode material and the resistance variable layer to form a second electrode over a remaining portion of the resistance variable layer. | 12-31-2015 |
20160035975 | TOP ELECTRODE FOR DEVICE STRUCTURES IN INTERCONNECT - Some embodiments relate to an integrated circuit device. The integrated circuit device includes a resistive random access memory (RRAM) cell, which includes a top electrode and a bottom electrode that are separated by a RRAM dielectric layer. The top electrode of the RRAM cell has a recess in its upper surface. A via is disposed over the RRAM cell and contacts the top electrode within the recess. | 02-04-2016 |
Yen-Hsin Chu, Kaohsiung City TW
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20120306680 | CURRENT PROVIDING SYSTEM, ADC WITH THE CURRENT PROVIDING SYSTEM, AND CURRENT PROVIDING METHOD - A current providing system, for providing an output current, which comprises: a frequency detecting circuit, for receiving at least one input signal, and for detecting a frequency of the input signal; a frequency-controlled current providing circuit, for providing the output current according to the input signal frequency when the input signal frequency is in a first predetermined range; and a predetermined current providing circuit, for providing the output current with a first predetermined current value, when the input signal frequency is not in the first predetermined range. | 12-06-2012 |
Yen-Yin Chu, Kaohsiung City TW
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20130027321 | DISPLAY SYSTEM AND METHOD - A display system is disclosed. The display system includes several electrical apparatuses and a display control unit. The display control unit builds connections with the electrical apparatuses. The display control unit includes an information generating module and a display driving module. When the display system is in a combination display mode, the information generating module detects and generates combination information about combination relations among the display units of the electrical apparatuses. The display driving module drives each of the display units to display a corresponding image block according to the combination information. Hence, the displayed corresponding image blocks can be combined to form an entire image. A display method is also disclosed. | 01-31-2013 |
Yung-Ping Chu, Kaohsiung City TW
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20130199086 | METHOD FOR PRODUCING A BIO-COAL - A method for producing a bio-coal includes the following steps: | 08-08-2013 |
Yun-Wen Chu, Kaohsiung City TW
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20150132973 | Ultraviolet Curing Apparatus And Ultraviolet Curing Method Thereof - An ultraviolet curing apparatus includes a chamber, a gas flow generator, and an ultraviolet lamp. The gas flow generator includes a top liner and a bottom liner coupled to each other. The top liner and the bottom liner are disposed in the chamber, and are made of low-coefficient of thermal expansion material. The ultraviolet lamp is disposed on the chamber and is configured for providing ultraviolet light. | 05-14-2015 |
Yu-Yi Chu, Kaohsiung City TW
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20100139070 | Device and A Method Thereof for Producing A Patterned Plate - A device for producing a patterned plate from a tubular work piece is disclosed wherein walls of the tubular work piece comprise at least one forming surface. The device comprises a die and an electromagnetic actuator, wherein the die comprises a patterned surface with a pattern formed thereon and a fracturing part. The tubular work piece is disposed between the die and the electromagnetic actuator such that the walls of the tubular work piece correspond to walls of the die, and the forming surface corresponds to the patterned surface. When the electromagnetic actuator is supplied with a current pulse, an eddy current is induced in the tubular work piece, generating a repulsive force between the electromagnetic actuator and the tubular work piece. Therefore, the tubular work piece impacts the die, and the forming surface is deformed against the patterned surface and the fracturing part, thus replicating the pattern of the patterned surface onto the forming surface. At the same time, the tubular work piece is fractured at the position corresponding to the fracturing part. A method for producing a patterned plate from a tubular work piece is also disclosed. | 06-10-2010 |
20100147043 | Device for Producing Patterns - A device for producing a pattern onto a work piece is disclosed. The device comprises a die, an electromagnetic actuator and a base; wherein the die comprises a patterned surface and the patterned surface comprises a pattern. The electromagnetic actuator comprises an plate body, a convex part and a strip unit connected to the plate body; the electromagnetic actuator is disposed in the base. When the electromagnetic actuator is activated while a work piece is being positioned between the patterned surface and the electromagnetic actuator, an inductive current is generated on the work piece by the electromagnetic actuator, and then a repulsive force is generated between the electromagnetic actuator and the work piece. The repulsive force then causes the work piece to adhere to the patterned surface, forcing the work piece to deform against the patterned surface and to take on the shape of the pattern. | 06-17-2010 |
20120291506 | Method for Producing Patterned Plate - A device producing a patterned plate includes a die and an electromagnetic actuator. The die includes a patterned surface with a pattern formed thereon and a fracturing part. The tubular work piece is disposed between the die and the electromagnetic actuator such that walls of the tubular work piece correspond to walls of the die. When the electromagnetic actuator is supplied with a current pulse, an eddy current is induced in the tubular work piece, generating a repulsive force between the electromagnetic actuator and the tubular work piece. Therefore, the tubular work piece impacts the die, and a forming surface of the tubular work piece is deformed against the patterned surface and the fracturing part, thus replicating the pattern of the patterned surface onto the forming surface. At the same time, the tubular work piece is fractured at the position corresponding to the fracturing part. | 11-22-2012 |