Patent application number | Description | Published |
20090114457 | Object detection for a capacitive ITO touchpad - In the detection of multiple objects touching on a capacitive ITO touchpad, the relative levels of the capacitive measurements received by a touch integrated circuit are used to determine the relative position between the multiple objects. | 05-07-2009 |
20090135152 | Gesture detection on a touchpad - A gesture detection on a touchpad includes detecting whether any object touches on the touchpad, and if any object is detected on the touchpad, further detecting whether more object touches on the touchpad, by which it may determine a gesture function to start a default function, such as drag an object, scroll a scrollbar, open a file, or zoom in a picture. | 05-28-2009 |
20100001966 | Two dimensional application of a one dimensional touch sensor in a capacitive touchpad - A capacitive touchpad includes a controller, a plurality of scan lines and a plurality of sensor pads distributed over a one dimensional touch sensor. Each of the sensor pads is connected to the controller by a respective one of the scan lines to transmit a sensed value to the controller. The controller uses the sensed values and the positions of some of the sensor pads in an interpolation to determine the two dimensional coordinates of one or more touched positions. Based on the sensed values, the controller selects one or more of the sensor pads as one or more reference points for the interpolation. | 01-07-2010 |
20110109575 | METHOD FOR CURSOR MOTION CONTROL BY A TOUCHPAD TO MOVE A CURSOR ON A DISPLAY SCREEN - A cursor control method using a touchpad triggers an automatic movement signal for a cursor when an object moves from a first defined region into a second defined region of a two-dimensional touch sensor, or when an object stays in the second defined region for a preset duration after it moves from the first defined region into the second defined region, and define the automatic movement signal with the direction identical to that of the object moving into the second defined region, so that the cursor will keep moving in its last moving direction. | 05-12-2011 |
Patent application number | Description | Published |
20140161455 | TEMPERATURE CONTROLLED MULTI-CHANNEL TRANSMITTER OPTICAL SUBASSEMBLY AND OPTICAL TRANSCEIVER MODULE INCLUDING SAME - A temperature controlled multi-channel transmitter optical subassembly (TOSA) may be used in a multi-channel optical transceiver. The multi-channel TOSA generally includes an array of lasers optically coupled to an arrayed waveguide grating (AWG) to combine multiple optical signals at different channel wavelengths. A temperature control system may be used to control the temperature of both the array of lasers and the AWG with the same temperature control device, e.g., a thermoelectric cooler (TEC). The multi-channel optical transceiver may also include a multi-channel receiver optical subassembly (ROSA). The optical transceiver may be used in a wavelength division multiplexed (WDM) optical system, for example, in an optical line terminal (OLT) in a WDM passive optical network (PON). | 06-12-2014 |
20140241726 | TEMPERATURE CONTROLLED MULTI-CHANNEL TRANSMITTER OPTICAL SUBASSEMBLY AND OPTICAL TRANSCEIVER MODULE INCLUDING SAME - A temperature controlled multi-channel transmitter optical subassembly (TOSA) may be used in a multi-channel optical transceiver. The temperature controlled multi-channel TOSA generally includes an array of lasers optically coupled to an optical multiplexer, such as an arrayed waveguide grating (AWG), to combine multiple optical signals at different channel wavelengths. The lasers may be thermally tuned to the channel wavelengths by establishing a global temperature for the array of lasers and separately raising local temperatures of individual lasers in response to monitored wavelengths associated with the lasers. A temperature control device, such as a TEC cooler coupled to the laser array, may provide the global temperature and individual heaters, such as resistors adjacent respective lasers, may provide the local temperatures. The optical transceiver may be used in a wavelength division multiplexed (WDM) optical system, for example, in an optical line terminal (OLT) in a WDM passive optical network (PON). | 08-28-2014 |
20140341580 | COMPACT MULTI-CHANNEL OPTICAL TRANSCEIVER MODULE - A compact multi-channel optical may include a multi-channel transmitter optical subassembly (TOSA), a multi-channel receiver optical subassembly (ROSA) and a circuit board configured and arranged to fit within a relatively small space. The multi-channel ROSA is spaced from the circuit board to allow circuit components to be mounted between the circuit board and the ROSA. The multi-channel ROSA may also be inverted and mounted proximate a transceiver top housing portion, for example, using an L-shaped ROSA support, to transfer heat from the ROSA to the transceiver housing portion. The optical transceiver may be used in a wavelength division multiplexed (WDM) optical system, for example, in an optical line terminal (OLT) in a WDM passive optical network (PON). | 11-20-2014 |
Patent application number | Description | Published |
20120064686 | Lateral Uniformity in Silicon Recess Etch - A method of etching recesses into silicon prior to formation of embedded silicon alloy source/drain regions. The recess etch includes a plasma etch component, using an etch chemistry of a primary fluorine-based or chlorine-based etchant, in combination with a similar concentration of hydrogen bromide. The concentration of both the primary etchant and the hydrogen bromide is relatively low; a diluent of an inert gas or oxygen is added to the reactive species. Loading effects on the undercut of the recess etch are greatly reduced, resulting in reduced transistor performance variation. | 03-15-2012 |
20120100717 | TRENCH LITHOGRAPHY PROCESS - A process of forming an integrated circuit using a dual damascene interconnect process by etching a via hole in an ILD and filling the via hole with a sacrificial via fill material. A trench etch hard mask layer is formed over the ILD. An inorganic hard mask layer is formed over the trench etch hard mask layer. The inorganic hard mask layer is etched to form an etch mask for the trench etch hard mask layer, which is subsequently etched to form an etch mask for the trench etch process. The sacrificial via fill material etches at a comparable rate to the ILD layer. The trench etch hard mask layer is removed and the sacrificial via fill material is removed from the via hole. | 04-26-2012 |
20140021556 | SPACER SHAPER FORMATION WITH CONFORMAL DIELECTRIC FILM FOR VOID FREE PMD GAP FILL - An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer (CESL) spacer layer on lateral surfaces of the MOS transistor gates, etching back the CESL spacer layer to form sloped CESL spacers on the lateral surfaces of the MOS transistor gates with heights of ¼ to ¾ of the MOS transistor gates, forming a CESL over the sloped CESL spacers, the MOS transistor gates and the intervening substrate, and forming a PMD layer over the CESL. | 01-23-2014 |
20140187009 | UNIFORM, DAMAGE FREE NITRIDE ETCH - An integrated circuit may be formed by forming a sacrificial silicon nitride feature. At least a portion of the sacrificial silicon nitride feature may be removed by placing the integrated circuit in a two-step oxidized layer etch tool and removing a surface layer of oxidized silicon from the sacrificial silicon nitride feature using a two-step etch process. The two-step etch process exposes the integrated circuits to reactants from a plasma source at a temperature less than 40° C. and subsequently heating the integrated circuit to 80° C. to 120° C. while in the two-step oxidized layer etch tool. While the integrated circuit is in the two-step oxidized layer etch tool, without exposing the integrated circuit to an ambient containing more than 1 torr of oxygen, at least a portion of the sacrificial silicon nitride feature is removed using fluorine-containing etch reagents, substantially free of ammonia. | 07-03-2014 |
20140187010 | REPLACEMENT GATE PROCESS - An integrated circuit containing metal replacement gates may be formed by forming a CMP stop layer over sacrificial gates, and forming a dielectric fill layer over the CMP stop layer. Dielectric material from the dielectric fill layer is removed from over the sacrificial gates using a CMP process which exposes the CMP stop layer over the sacrificial gates but does not expose the sacrificial gates. The CMP stop layer is removed from over the sacrificial gates using a plasma etch process. In one version, the plasma etch process may be selective to the CMP stop layer. In another version, the plasma etch process may be a non-selective etch process. After the sacrificial gates are exposed by the plasma etch process, the sacrificial gates are removed and the metal replacement gates are formed. | 07-03-2014 |
20140361376 | DIELECTRIC LINER ADDED AFTER CONTACT ETCH BEFORE SILICIDE FORMATION - A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon, dielectric spacers on sidewalls of the gate electrode, a source and drain in the semiconductor surface on opposing sides of the gate electrode, and a pre-metal dielectric (PMD) layer over the gate electrode and over the source and drain regions. Contact holes are formed through the PMD layer to form a contact to the gate electrode and contacts to the source and drain. A post contact etch dielectric layer is then deposited on the contacts to source and drain and on sidewalls of the PMD layer. The post contact etch dielectric layer is selectively removed from the contacts to leave a dielectric liner on sidewalls of the PMD layer. A metal silicide layer is formed on the contacts to the source and drain. | 12-11-2014 |
20150044830 | HARD MASK FOR SOURCE/DRAIN EPITAXY CONTROL - An integrated circuit is formed to include a first polarity MOS transistor and a second, opposite, polarity MOS transistor. A hard mask of silicon-doped boron nitride (Si | 02-12-2015 |