Patent application number | Description | Published |
20090045817 | ELECTRICAL TESTING DEVICE - The present invention is directed to an electrical testing device for use in an AC electrical power distribution circuit including a plurality of AC electric power transmitting wires coupled between an AC power distribution point and a device box. The device includes a plurality of electrical probes configured for insertion into an outlet receptacle. A plug test connection arrangement is configured to receive a plug connector when inserted therein. The plug connector includes a plurality of plug contacts and a termination arrangement configured to terminate the plurality of AC electric power transmitting wires such that electrical continuity is established between the AC power distribution point and the plurality of plug contacts. The plug test connection arrangement includes a plurality of test contacts configured to mate with the plurality of plug contacts when the plug connector is inserted into the plug test connection arrangement. The termination arrangement being in a detached relationship from the device box after the plurality of AC electric power transmitting wires are terminated. An electrical test circuit is configured to perform at least one electrical test. The electrical test circuit includes a switch mechanism configured to connect the electrical test circuit to the plurality of electrical probes at a first switch setting or connect the electrical test circuit to the plurality of test contacts at a second switch setting. At least one shock mitigation structure is coupled to the plurality of electrical probes or the plug test connection arrangement and is configured to prevent user access to the plurality of electrical probes or the plug test connection arrangement. | 02-19-2009 |
20090284880 | Protection Device with Lockout Test - The present invention is directed to a protective device the includes a plurality of line terminals and a plurality of load terminals. A detection circuit is coupled to the plurality of line terminals. The detection circuit is configured to generate a sensor signal in response to an electrical perturbation propagating on the plurality of line terminals and/or the plurality of load terminals. A fault detection circuit is coupled to detection circuit. The fault detection circuit is configured to generate a fault detection signal when the electrical perturbation exceeds a predetermined level. An actuation assembly is coupled to the fault detection circuit. The actuation assembly is configured to generate a trip actuation in response to the fault detection signal. A circuit interrupter assembly is coupled to the fault detection circuit. The circuit interrupter assembly includes a set of movable contacts configured to be driven into a tripped state in response to the trip actuation and driven into a reset state in response to a reset actuation. A reset mechanism is coupled to the circuit interrupter assembly. The reset mechanism is configured to provide the reset actuation in response to a user reset input. A test assembly is coupled to the plurality of line terminals and the plurality of load terminals, the detection circuit, the actuation circuit and the reset mechanism. The test assembly includes a test circuit configured to generate a simulated electrical perturbation exceeding the predetermined level in response to a user test input. The test assembly also includes a test timing mechanism coupled to the reset mechanism. The test timing mechanism is configured to drive the circuit interrupter into the tripped state and disable the reset mechanism if any one of the detection circuit, fault detection circuit, actuation assembly, or circuit interrupter assembly fail before a predetermined time elapses such that the device is permanently inoperable. | 11-19-2009 |
20110080677 | PROTECTIVE DEVICE - The present invention is directed to a protective device that includes a plurality of line terminals and a plurality of load terminals, the plurality of load terminals including a plurality of hot load terminals and a plurality of neutral load terminals. The device also includes a circuit interrupter having four sets of moveable contacts, the four sets of moveable contacts being configured to couple the plurality of line terminal to the plurality of load terminals in a reset state and to decouple the plurality of line terminals from the plurality of load terminals in a tripped state. A test circuit includes an end of life detection circuit coupled to the plurality of line terminals or the plurality of load terminals by a switch mechanism associated with the four sets of moveable contacts. The test circuit includes a manually actuatable button and a fusible element, the fusible element assuming a permanently open state if the circuit interrupter does not enter the tripped state within a predetermined period after the manually actuatable button has been actuated. | 04-07-2011 |
20120140369 | PROTECTIVE DEVICE - The present invention is directed to an electrical wiring device that includes at least one user accessible input mechanism and a test assembly configured to initiate a self-test in response to stimulus signal. The self test determines whether a sensor, a fault detection circuit or a circuit interrupter assembly are in an operational mode or are in a failure mode, the reset stimulus being provided in the operational mode and a reset lockout stimulus being provided in the failure mode. The device also including a reset lockout mechanism coupled to the circuit interrupter assembly and the test assembly. The reset lockout mechanism is configured to disable the reset stimulus in response to the reset lockout stimulus if any one of the at least one sensor, at least one fault detection circuit, or circuit interrupter assembly is determined to be in the failure mode after a predetermined time elapses. | 06-07-2012 |
20130293990 | PROTECTIVE DEVICE WITH AUTOMATED SELF TEST - The present invention is directed to a circuit interrupting device including an actuator that provides an actuator stimulus upon the occurrence of the fault actuation signal. A circuit interrupter is positioned to electrically disconnect the first, second and third electrical conductors from each other upon the occurrence of the actuator stimulus. An automated test circuit is coupled to the circuit interrupting assembly. The automated test circuit is configured to automatically produce the simulated fault condition during a predetermined portion of an AC line cycle to determine whether the fault detection assembly is operational such that the fault detection assembly provides a fault detection signal without the circuit interrupter electrically disconnecting the first, second and third electrical conductors from each other. The automated test circuit is further configured to provide a device failure mode signal such that a plurality of the first, second or third electrical conductors are disconnected from each other if the fault detection signal is not detected within a predetermined time frame. | 11-07-2013 |
Patent application number | Description | Published |
20090283496 | DIRECTING CARBON NANOTUBE GROWTH - Embodiments of the invention include apparatuses and methods relating to directed carbon nanotube growth using a patterned layer. In some embodiments, the patterned layer includes an inhibitor material that directs the growth of carbon nanotubes. | 11-19-2009 |
20110147712 | QUANTUM WELL TRANSISTORS WITH REMOTE COUNTER DOPING - A quantum well device and a method for manufacturing the same are disclosed. In an embodiment, a quantum well structure comprises a quantum well region overlying a substrate and a remote counter doping comprising dopants of conductivity opposite to the conductivity of the charge carriers of the quantum well region. The remote counter doping is incorporated in a vicinity of the quantum well region for exchange mobile carriers with the quantum well channel, reducing the off-state leakage current. In another embodiment, a quantum well device comprises a quantum well structure including a remote counter doping, a gate region overlying a portion of the quantum well structure, and a source and drain region adjacent to the gate region. The quantum well device can also comprise a remote delta doping comprising dopants of the same conductivity as the quantum well channel. | 06-23-2011 |
20140091361 | METHODS OF CONTAINING DEFECTS FOR NON-SILICON DEVICE ENGINEERING - An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor. | 04-03-2014 |
20140170998 | GROUP III-N TRANSISTORS ON NANOSCALE TEMPLATE STRUCTURES - A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin. | 06-19-2014 |
20140175515 | NONPLANAR III-N TRANSISTORS WITH COMPOSITIONALLY GRADED SEMICONDUCTOR CHANNELS - A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage. | 06-26-2014 |
20140231871 | METHODS OF CONTAINING DEFECTS FOR NON-SILICON DEVICE ENGINEERING - An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor. | 08-21-2014 |
20140291693 | GROUP III-N TRANSISTORS ON NANOSCALE TEMPLATE STRUCTURES - A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin. | 10-02-2014 |
20150064859 | NONPLANAR III-N TRANSISTORS WITH COMPOSITIONALLY GRADED SEMICONDUCTOR CHANNELS - A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage. | 03-05-2015 |
20150108496 | GROUP III-N TRANSISTOR ON NANOSCALE TEMPLATE STRUCTURES - A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin. | 04-23-2015 |
20150270265 | METHODS OF CONTAINING DEFECTS FOR NON-SILICON DEVICE ENGINEERING - An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor. | 09-24-2015 |
Patent application number | Description | Published |
20090113256 | Method, computer program product, apparatus and device providing scalable structured high throughput LDPC decoding - The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Decoding is performed in a pipelined manner using a layered belief propagation technique and scalable resources, which are configurable to accommodate at least two codeword lengths and at least two code rates. A computer program product, apparatus and device are also described. | 04-30-2009 |
20090113276 | Method, apparatus, computer program product and device providing semi-parallel low density parity check decoding using a block structured parity check matrix - The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Encoded data block comprising data sub-blocks are stored. Decoding is performed in a pipelined manner using an irregular, block-structured parity check matrix, where at least two data sub-block matrices of the parity check matrix are read from and written in each of a plurality of clock cycles. The reading and writing of the data sub-blocks is evenly distributed between at least two area of a memory. The decoding is performed with shift values which eliminate cycles at or below a predetermined threshold length. An apparatus, computer program product and device are also described. | 04-30-2009 |
20090154600 | QRD-QLD searching based sphere detector for MIMO receiver - An apparatus includes a receiver configurable to receive signals from y pairs of antennas, where y is greater than one, and where the received signals convey coded bits of information. The apparatus further includes a detection block that includes a plurality of search modules configurable to process signals received from pairs of the antennas in parallel to find partial Euclidian distances and determine valid partial candidates for individual antennas; and a plurality of sort modules configurable to sort the valid partial candidates to find M best partial candidates to be combined into M | 06-18-2009 |
20120240003 | Method, Apparatus, Computer Program Product and Device Providing Semi-Parallel Low Density Parity Check Decoding Using a Block Structured Parity Check Matrix - The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Encoded data block comprising data sub-blocks are stored. Decoding is performed in a pipelined manner using an irregular, block-structured parity check matrix, where at least two data sub-block matrices of the parity check matrix are read from and written in each of a plurality of clock cycles. The reading and writing of the data sub-blocks is evenly distributed between at least two area of a memory. The decoding is performed with shift values which eliminate cycles at or below a predetermined threshold length. An apparatus, computer program product and device are also described. | 09-20-2012 |