Patent application number | Description | Published |
20090113194 | Persisting value relevant to debugging of computer system during reset of computer system - The last value of an element of a computing system is continually stored within a first register. The element is cleared during any restart or reset of the computing system. The last value is relevant to debugging of the computing system when the computing system fails to perform as expected and/or as desired. Upon receiving an instruction to reset the computing system via a first reset signal corresponding to pressing of a reset button or a second reset signal corresponding to a baseboard management controller issuing a reset command, the last value of the element as stored within the first register is copied to a second register. The computing system is then reset. The last value of the element as stored within the second register persists within the second register during this type of reset, but is cleared during any other reset or restart of the computing system. | 04-30-2009 |
20090327764 | Managing Power Consumption Of A Computer - Methods, computers, and products for managing power consumption of a computer, the computer including a computer processor and managing power consumption of a computer includes: dynamically during operation of the computer, setting, by an in-band power manager in dependence upon performance metrics of the computer processor, a current performance state (‘p-state’) of the computer processor; and providing, by the in-band power manager to an out-of-band power manager, the current p-state of the computer processor. | 12-31-2009 |
20090327765 | Managing Power Consumption Of A Computer - Methods and products for managing power consumption of a computer and computers for which power consumption is managed. The computer includes the computer including a computer processor and embodiments of the present invention include providing, by an in-band power manger to an out-of-band power manager, a proposed performance state (‘p-state’) for the computer processor; determining, by the out-of-band power manager, in dependence upon a power setpoint and currently-measured operating metrics of the computer processor, whether to approve the proposed p-state; and if the out-of-band power manager approves the proposed p-state, setting operating parameters of the computer processor according to the approved p-state. | 12-31-2009 |
20100064080 | MANAGING PCI-EXPRESS MAX PAYLOAD SIZE FOR LEGACY OPERATING SYSTEMS - The present disclosure is directed to a method for balancing latency versus bandwidth trade-offs in packet transmission utilizing PCI-Express. The method may comprise identifying at least one system element along a path of a packet to be transmitted; determining and storing an optimum payload size for each one of the at least one system element; configuring a Max Payload Size parameter for each one of the at least one system element, wherein the Max Payload Size parameter is configured based on the optimum payload size for each one of the at least one system element. | 03-11-2010 |
20110161736 | Debugging module to load error decoding logic from firmware and to execute logic in response to an error - A computing device includes a processor, firmware, a hardware component, and a debugging module. The firmware stores error decoding logic particular to the computing device. The hardware component detects an error in the computing device, and responsively issues an interrupt and halts the processor such that the processor cannot execute any more computer-readable code. The debugging module loads the logic from the firmware at reset and executes the logic responsive to the interrupt. The debugging module does not use the processor to execute the logic, the firmware is not part of the debugging module, and the debugging module is not part of the hardware component. The firmware may also store a mapping between registers of the hardware component and field-replaceable hardware units of the computing device, which the debugging module loads at reset and uses when executing the error decoding logic to determine which unit has caused the error. | 06-30-2011 |
20120284540 | Managing Power Consumption Of A Computer - Methods, computers, and products for managing power consumption of a computer, the computer including a computer processor and managing power consumption of a computer includes: dynamically during operation of the computer, setting, by an in-band power manager in dependence upon performance metrics of the computer processor, a current performance state (‘p-state’) of the computer processor; and providing, by the in-band power manager to an out-of-band power manager, the current p-state of the computer processor. | 11-08-2012 |
20150234768 | HOT REMOVING AN I/O MODULE WITH MULTIPLE HOT PLUG SLOTS - In a method for ejecting a plurality of hot plug slots sharing a power controller, a processor receives a request to eject a plurality of hot plug slots, wherein the plurality of hot plug slots share a power controller and have at least two adapters present. A processor causes an OS to incrementally eject the at least two adapters, wherein ejecting an adapter comprises the OS stopping at least one driver of the adapter, and the OS generating a request to remove power from a hot plug slot. Responsive to a request by the OS to remove power from a hot plug slot, a processor generates a signal that prevents the OS from recognizing the adapter is present in the hot plug slot. Responsive to all device drivers for the at least two adapters being stopped, a processor causes power to be removed from the plurality of hot plug slots. | 08-20-2015 |