Patent application number | Description | Published |
20080259515 | Power Switching Apparatus With Open-Load Detection - Power switching apparatus comprising switch means having a control terminal and output terminals for connection in series between a power supply and a load. The switch means is responsive to a control signal applied to the control terminal to switch between an ON-state in which it supplies power supply current from the power supply through the output terminals to the load and an OFF-state in which it interrupts the supply of power through the output terminals to the load. The apparatus includes detection means for detecting an open-load condition of the load at least during the ON-state of the switch means, comprising detection control means operable in the ON-state of the switch means for modifying the control signal so as to start switching the switch means to the OFF-state during a lapse of time substantially less than the time required for the switch means to reach the OFF-state and for restoring the control signal to a value corresponding to the ON-state at or before the end of the lapse of time, and comparator means responsive to variation of voltage at the output terminals during the lapse of time. The duration of the variation of voltage during the open-load detection is too short and its magnitude too small for the variation of load current to be perceptible, notably in the case where the load is a lamp. | 10-23-2008 |
20090102400 | METHOD FOR DRIVING A PTC ELECTRICAL LOAD ELEMENT - A method is intended to make it possible to drive a PTC electrical load element with a switching unit with the highest possible operational reliability. For this purpose, the electric current is switched off if a predetermined current threshold value is exceeded, the magnitude of the current threshold value being determined from the operating parameters of the load element. | 04-23-2009 |
20100141032 | Control Unit and Method for Pulse Width Modulated Control - A control unit for triggering a plurality of electric loads with a plurality of input signals, wherein the electric loads are triggered by pulse width modulated signals, and the input signals are PWM signals. A method is described with which the control unit triggers a plurality of electric loads with a plurality of input signals. The control unit includes controllable switching provisions, wherein these switching provisions connect at least one load respectively with one of at least two different PWM inputs. A method is described for triggering a plurality of electric loads with the aid of the control unit. | 06-10-2010 |
20100308786 | METHOD FOR DRIVING NON-LINEAR LOAD ELEMENTS - A method for driving a non-linear load element. On account of the non-linear interrelationship between the voltage and the current at the load element and the related non-linear dependence of the power loss on the quantities “voltage” and “current”, an adjustment of the switching speed only on the basis of the power loss in the switching element cannot be carried out with non-linear load elements without being confronted with undesirable switching losses and related electromagnetic noise fields. Therefore, the load current currently flowing in the load element is picked up in addition to the currently determined power loss in the switching element, and the switching speed of the switching element is controlled in dependence on the determined power loss and on the current picked up. The switching speed can be optimally adjusted when driving the non-linear load elements by means of PWM. | 12-09-2010 |
20110140636 | SYSTEM AND METHOD FOR PROVIDING A CONTROL SIGNAL - The system, which provides a control signal, includes an over-current control unit, a time clock that provides a periodic time signal, and a clock generator unit that includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the time clock and the output terminal is coupled to the over-current control unit. The first input terminal of the clock generator unit receives the periodic time signal and the second input terminal of the clock generator unit receives a modification signal. The clock generator unit generates a clock signal based on the periodic time signal and the modification signal. The output terminal of the clock generator unit provides the clock signal to the over-current control unit, and the over-current control unit provides a control signal based on the clock signal. | 06-16-2011 |
20120119678 | METHOD FOR DRIVING A PTC ELECTRICAL LOAD ELEMENT - A method is intended to make it possible to drive a PTC electrical load element with a switching unit with the highest possible operational reliability. For this purpose, the electric current is switched off if a predetermined current threshold value is exceeded, the magnitude of the current threshold value being determined from the operating parameters of the load element. | 05-17-2012 |
Patent application number | Description | Published |
20080313494 | MEMORY REFRESH SYSTEM AND METHOD - A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors. | 12-18-2008 |
20090079055 | METHOD AND STRUCTURE OF EXPANDING, UPGRADING, OR FIXING MULTI-CHIP PACKAGE - Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP. | 03-26-2009 |
20090080279 | STRUCTURE TO SHARE INTERNALLY GENERATED VOLTAGES BETWEEN CHIPS IN MCP - Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage. | 03-26-2009 |
20090113078 | METHOD AND APPARATUS FOR IMPLEMENTING MEMORY ENABLED SYSTEMS USING MASTER-SLAVE ARCHITECTURE - Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory device, while command decoding logic of the second memory device is bypassed. | 04-30-2009 |
20090113158 | METHOD AND APPARATUS FOR SYNCHRONIZING MEMORY ENABLED SYSTEMS WITH MASTER-SLAVE ARCHITECTURE - Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew. | 04-30-2009 |
20090129186 | SELF-DIAGNOSTIC SCHEME FOR DETECTING ERRORS - The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least one non-volatile memory chip, and at least one fail signature register for storing fail signature data related to memory errors detected in the MCP. The controller can poll the fail signature register for fail signature data related to memory errors stored therein. Upon detection of fail signature data, the controller can store the fail signature data on a fail signature register located on a non-volatile memory. | 05-21-2009 |
20090200652 | METHOD FOR STACKING CHIPS IN A MULTI-CHIP PACKAGE - A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip. | 08-13-2009 |