Patent application number | Description | Published |
20110270963 | SYSTEM AND METHOD FOR EVALUATING APPLICATION SUITABILITY IN EXECUTION ENVIRONMENT - An evaluation system evaluates the suitability of an application in a plurality of types of application execution environments based on the characteristics of this application and the usage of this application by a user. The evaluation system displays information denoting the result of this evaluation. | 11-03-2011 |
20130312055 | SECURITY MANAGEMENT DEVICE AND METHOD - In a case where a master virtual machine, which is constructed on the basis of master information for configuring either part or all of a virtual machine, and an individual virtual machine, which is constructed on the basis of individual information that is configured partially or entirely in accordance with the master information, exist as the types of virtual machines that a physical client provides to a user terminal, a security check of a plurality of virtual machines is selectively executed, with respect to each check item, for a virtual machine of the type corresponding to the contents of the check item. | 11-21-2013 |
20150212848 | SECURITY MANAGEMENT DEVICE AND METHOD - In a case where a master virtual machine, which is constructed on the basis of master information for configuring either part or all of a virtual machine, and an individual virtual machine, which is constructed on the basis of individual information that is configured partially or entirely in accordance with the master information, exist as the types of virtual machines that a physical client provides to a user terminal, a security check of a plurality of virtual machines is selectively executed, with respect to each check item, for a virtual machine of the type corresponding to the contents of the check item. | 07-30-2015 |
Patent application number | Description | Published |
20110101434 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor storage device includes: memory cells including a transistor and a capacitor; bit lines; word lines; and sense amplifiers including first and second sense amplifiers, wherein the memory cells includes: a first memory cell group sharing a first auxiliary word line; and a second memory cell group sharing a second auxiliary word line, wherein the word lines includes a first word line coupled to the first auxiliary word line and a second word line coupled to the second auxiliary word line, the first word line is coupled to the first auxiliary word line in a first word line contact region, the second word line is coupled to the second auxiliary word line in a second word line contact region, the bit lines includes first and second bit lines coupled to the first sense amplifier on both sides of the first word line contact region. | 05-05-2011 |
20120032272 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT, SRAM, AND METHOD FOR PRODUCING Dt-MOS TRANSISTOR - A semiconductor device includes a silicon substrate; an element isolation region; an element region including a first well; a contact region; a gate electrode extending from the element region to a sub-region of the element isolation region between the element region and the contact region; a source diffusion region; a drain diffusion region; a first insulating region contacting a lower end of the source diffusion region; a second insulating region contacting a lower end of the drain diffusion region; and a via plug configured to electrically connect the gate electrode with the contact region. The first well is disposed below the gate electrode and is electrically connected with the contact region via the silicon substrate under the sub-region. The lower end of the element isolation region except the sub-region is located lower than the lower end of the first well. | 02-09-2012 |
20130088908 | SEMICONDUCTOR DEVICE - Memory cells adjacent to each other in a second direction are formed in a first p-type well region, a first n-type well region, and a second p-type well region arranged in a first direction. Each memory cell includes a first transfer transistor and a first driver transistor formed in the first p-type well region, a second transfer transistor and a second driver transistor formed in the second p-type well region, and first and second load transistors formed in the first n-type well region. In an SRAM, gate electrodes of the first and second transfer transistors of the memory cells adjacent to each other in the second direction are electrically connected to first and second word lines, respectively. The first and second word lines are electrically connected to the first and second p-type well regions, respectively. | 04-11-2013 |
20130137239 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor storage device includes: memory cells including a transistor and a capacitor; bit lines; word lines; and sense amplifiers including first and second sense amplifiers, wherein the memory cells includes: a first memory cell group sharing a first auxiliary word line; and a second memory cell group sharing a second auxiliary word line, wherein the word lines includes a first word line coupled to the first auxiliary word line and a second word line coupled to the second auxiliary word line, the first word line is coupled to the first auxiliary word line in a first word line contact region, the second word line is coupled to the second auxiliary word line in a second word line contact region, the bit lines includes first and second bit lines coupled to the first sense amplifier on both sides of the first word line contact region. | 05-30-2013 |
20130154023 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT, SRAM, AND METHOD FOR PRODUCING Dt-MOS TRANSISTOR - A semiconductor device includes a silicon substrate; an element isolation region; an element region including a first well; a contact region; a gate electrode extending from the element region to a sub-region of the element isolation region between the element region and the contact region; a source diffusion region; a drain diffusion region; a first insulating region contacting a lower end of the source diffusion region; a second insulating region contacting a lower end of the drain diffusion region; and a via plug configured to electrically connect the gate electrode with the contact region. The first well is disposed below the gate electrode and is electrically connected with the contact region via the silicon substrate under the sub-region. The lower end of the element isolation region except the sub-region is located lower than the lower end of the first well. | 06-20-2013 |
Patent application number | Description | Published |
20090289254 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film. | 11-26-2009 |
20100068860 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region. | 03-18-2010 |
20110068339 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film. | 03-24-2011 |
Patent application number | Description | Published |
20140106128 | Die and Process for Extrusion - The present disclosure is related to a die suitable for extrusion of thermoplastic vulcanizate, in particular for co-extrusion of multiple materials comprising a thermoplastic vulcanizate. The die comprises a pool die plate, an orifice die plate, and a profile die plate. By utilizing the die according to the present disclosure in extrusion, the flow of extrudate can be well controlled and balanced due to the design of flow pool and through orifice, thereby an extruded article achieves good shape performance, for example, good surface smoothness, and an undesired effect like edge tear, warpage, die moustache, silver line in the extrusion can be avoided. | 04-17-2014 |
20150056457 | Compositions and Methods for Making Them - Provided are compositions comprising: (i) a dispersed phase of rubber that is at least partially cured; (ii) a continuous thermoplastic phase including at least one thermoplastic polymer; (iii) a first polysiloxane having a number average molecular weight greater than 100 kg/mole; and (iv) a second polysiloxane having a number average molecular weight less than 100 kg/mole, and methods for making such compositions. Also provided are laminates including such compositions, weatherseals made therefrom, and methods for making them. | 02-26-2015 |
Patent application number | Description | Published |
20090111062 | Pattern Formation Method - The present invention provides a pattern formation method comprising a step of forming on a substrate a film of a first photosensitive material having low sensitivity to a light beam with a main wavelength at h-line emitted from a mask-less drawing exposure apparatus but having high sensitivity to an energy light beam containing ultraviolet light; a step of forming on the first photosensitive material a film of a second photosensitive material having higher sensitivity to a light beam with the main wavelength at h-line; a step of drawing a second pattern on the second photosensitive material with the mask-less direct drawing exposure apparatus; a step of developing the second photosensitive material; and a step of exposing to a light beam the second photosensitive material with the second pattern formed thereon and the first photosensitive material in batch to form a target first pattern on the first photosensitive material. | 04-30-2009 |
20100172116 | SHIELDED ELECTRONIC COMPONENTS AND METHOD OF MANUFACTURING THE SAME - A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant is provided. The Ni plating film is formed on a palladium (Pd) pretreatment layer formed on the upper surface of the sealant with using high-pressure CO | 07-08-2010 |
20110237001 | SEMICONDUCTOR CHIP USED FOR EVALUATION, EVALUATION SYSTEM, AND REPAIRING METHOD THEREOF - A technique for evaluating a semiconductor chip is provided. The semiconductor chip is mounted on a mount substrate, the semiconductor chip laminating on one surface of a silicone substrate, at least any of a metal wiring film | 09-29-2011 |
20120292772 | SHIELDED ELECTRONIC COMPONENTS AND METHOD OF MANUFACTURING THE SAME - A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant is provided. The Ni plating film is formed on a palladium (Pd) pretreatment layer formed on the upper surface of the sealant with using high-pressure CO | 11-22-2012 |
20120312126 | Metal Recovery Method and Dialysis Device - Provided is a valuable-metal recovery method for recovering metals from lithium ion batteries using comparatively simple equipment and without using a cumbersome process. In said method, a positive electrode material from lithium ion batteries, containing lithium and a transition metal, is dissolved in an acidic solution, thereby generating lithium ions and ions of the transition metal in the acidic solution. Said acidic solution and a recovery liquid are then made to flow with an anion-permeable membrane interposed therebetween, causing the lithium ions to permeate from the acidic solution to recovery solution. Lithium ions are then recovered from the recovery liquid containing dissolved lithium ions. | 12-13-2012 |
20130206607 | Lithium Extraction Method, and Metal Recovery Method - To provided a method for recovering lithium from a lithium ion battery using comparatively simple equipment and without using a cumbersome process. A lithium extraction method for extracting lithium from the positive electrode material of a lithium ion battery containing lithium and cobalt, the method being characterized in that the positive electrode material is immersed into an acidic solution at 50° C. or less, lithium ions are selectively leached into the acidic solution while inhibiting the leaching of cobalt ions, and the leaching of lithium ions is stopped while the amount of lithium contained in the positive electrode material is sufficient. | 08-15-2013 |
20130287654 | LEACHING SOLUTION AND METAL RECOVERY METHOD - A valuable metal recovery method of recovering metals from a lithium ion battery without using complicate steps and by a relatively simple and convenient facility is intended to be provided. | 10-31-2013 |