Patent application number | Description | Published |
20090010040 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device includes: a memory chip having memory cells of a resistance change type; and a heater so attached to the memory chip as to apply a temperature bias to the memory chip. | 01-08-2009 |
20090020785 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes: a semiconductor substrate, on which diffusion layers are formed; and multilayered wirings stacked above the semiconductor substrate to be connected to the diffusion layers via contact plugs, wherein a first wring and a second wiring formed thereabove are connected to the diffusion layers via first contact plug(s) and second contact plugs, respectively, and the number of the second contact plugs arrayed in parallel is set to be greater than that of the first contact plug(s). | 01-22-2009 |
20090067243 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - This disclosure concerns a memory including memory cell arrays including word lines extending in a first direction, bit lines extending in a second direction crossing the first direction, and memory cells provided to respectively correspond to cross-points in form of a lattice constituted by the word lines and the bit lines; sense amplifiers provided to respectively correspond to the bit lines and reading data stored in the memory cells; and bit line drivers provided to the bit lines and operating the bit lines when data is written to the memory cells, wherein the bit line drivers access the memory cells adjacent to a first memory cell diagonally with respect to the form of the lattice for writing the data to the adjacent memory cells during a data write operation without changing data stored in the memory cells adjacent to the first memory cell in the first and the second directions. | 03-12-2009 |
20090109728 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device including memory cells arranged, the memory cell having a stable state with a high resistance value and storing in a non-volatile manner such multi-level data that at least three resistance values, R | 04-30-2009 |
20090135637 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device including: a cell array having a resistance change type of memory cells disposed at the cross-points of word lines and bit lines, the resistance value of the memory cell being reversibly settable; a word line driver circuit configured to apply a selecting drive voltage to one selected in the word lines; and a bit line driver circuit configured to drive multiple bit lines in such a manner that a set mode and a reset mode are set simultaneously for multiple memory cells selected by the selected word line, the set mode being for changing a selected memory cell from a first resistance state into a second resistance state while the reset mode is for changing a selected memory cell from the second resistance state into the first resistance state. | 05-28-2009 |
20090175077 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - This disclosure concerns a memory including: word lines extending to a first direction; bit lines extending to a second direction crossing the first direction; a memory cell array including cell blocks each including memory cells respectively provided corresponding to intersection points of the word lines and the bit lines; and sense amplifiers provided corresponding to the bit lines, wherein the sense amplifiers copies existing data stored in a first cell block within the memory cell array to a plurality of memory cells, the memory cells being included in second and third cell blocks different from the first cell block, and alternately arranged in an extension direction of the word lines and also alternately arranged in an extension direction of the bit lines, and the sense amplifiers reads data from the second cell block or the third cell block, at a time of outputting data to outside of the sense amplifiers. | 07-09-2009 |
20090237979 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM - A semiconduct or memory device comprises a memory cell array including a plurality of memory cells arranged at intersections of word lines and bit lines; a read/write circuit operative to execute data read/write to the memory cell; and an operational circuit operative to compare certain length data read out by the read/write circuit from plural ones of the memory cells with certain length data to be written in the plural memory cells to make a decision, and create a flag representing the decision result. The read/write circuit inverts each bit in the certain length data to be written in the memory cells in accordance with the flag, and writes only rewrite-intended data of the certain length data and the flag. The read/write circuit reads the certain length data together with the flag corresponding thereto, and inverts each bit in the certain length data in accordance with the flag. | 09-24-2009 |
20100091551 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a memory cell array having memory cells; and a control circuit configured to apply a first voltage to a selected one of first wirings as well as a second voltage to a selected one of second wirings. The control circuit includes: a signal output circuit configured to output a first signal based on a first current flowing through a selected memory cell and a reference current; and a current retaining circuit configured to retain a second current flowing through the first wirings or a wiring electrically connected to the first wirings during a certain period of time. The signal output circuit is configured to determine the first current based on the second current retained by the current retaining circuit. The control circuit is configured to stop application of the first voltage to the first wirings based on the first signal. | 04-15-2010 |
20100124097 | SEMICONDUCTOR STORAGE DEVICE - Plural memory cell arrays laminated on the semiconductor substrate each includes a plurality of first wirings and second wirings formed to intersect with each other. The control circuit provides, in a non-selected second memory cell array that shares the first wiring with a selected first memory cell array, and a non-selected third memory cell array located more distant from the first memory cell array than the second memory cell array, the first potential to all of the first wirings and all of the second wirings. It also provides, in a non-selected fourth memory cell array that shares the second wiring with the first memory cell array and a non-selected fifth memory cell array located more distant from the first memory cell array than the fourth memory cell array, the second potential to all of the first wirings and all of the second wirings. | 05-20-2010 |
20100237512 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a cell array layer including a first and a second wiring, which cross each other; a third wiring formed on a first wiring layer below the cell array layer; a fourth wiring formed on a second wiring layer above the cell array layer; and a contact extending in a stacking direction for connecting the third and the fourth wiring, wherein the device further comprises a redundant wiring layer being formed between the first and the second wiring layer, the redundant wiring layer being formed with a redundant wiring having a portion extending in the same direction as at least one of the third and the fourth wiring, and the third and the redundant wiring, and the fourth and the redundant wiring being connected by a plurality of contacts arranged along the portion extending in the same direction as the third or the fourth wiring. | 09-23-2010 |
20110103130 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device including: a cell array having a resistance change type of memory cells disposed at the cross-points of word lines and bit lines, the resistance value of the memory cell being reversibly settable; a word line driver circuit configured to apply a selecting drive voltage to one selected in the word lines; and a bit line driver circuit configured to drive multiple bit lines in such a manner that a set mode and a reset mode are set simultaneously for multiple memory cells selected by the selected word line, the set mode being for changing a selected memory cell from a first resistance state into a second resistance state while the reset mode is for changing a selected memory cell from the second resistance state into the first resistance state. | 05-05-2011 |
20120033480 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to the embodiment comprises a memory cell array including first line, second line crossing the first line, and memory cell containing variable resistance element provided on the intersection of the first and second lines; a data write unit operative to cause the variable resistance element to make a transition from a first resistance to a second resistance different from the first resistance; and a resistance state detection unit including an abnormality detection circuit operative to detect a transition of the resistance of the variable resistance element to a third resistance when the data write unit causes the variable resistance element to make the transition from the first resistance to the second resistance (where the third resistancethe first resistance>the second resistance). | 02-09-2012 |
20120033512 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes first cells, first lines, second lines, a first cell array, and a signal driver. The first cell has in either a first state or a second state. Retention time in the second state is longer than in the first state. The first cell array has the first cells formed in a matrix the individuals. The first cells are electrically connected by the first, second lines. The signal driver drives the first cells. The signal driver causes the first cells to transition to either the first state or the second state by controlling any one of a voltage, a current, and a charge amount applied to the first cells, or a combination of these, and waveforms of the voltage, current, and charge amount and/or the length of transfer time of at least one of the voltage, current, and charge amount. | 02-09-2012 |
20120155148 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device including: a cell array having a resistance change type of memory cells disposed at the cross-points of word lines and bit lines, the resistance value of the memory cell being reversibly settable; a word line driver circuit configured to apply a selecting drive voltage to one selected in the word lines; and a bit line driver circuit configured to drive multiple bit lines in such a manner that a set mode and a reset mode are set simultaneously for multiple memory cells selected by the selected word line, the set mode being for changing a selected memory cell from a first resistance state into a second resistance state while the reset mode is for changing a selected memory cell from the second resistance state into the first resistance state. | 06-21-2012 |
20130223173 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a semiconductor memory device includes a memory cell array including blocks, each block being capable of executing a write, read, or erase operation independently of other blocks. A control portion is configured to execute the operation of a first block among the blocks in a first cycle, set a selection inhibited region within a range of a predetermined distance from the first block, until a temperature relaxation time for relaxing a temperature of the first block has elapsed, set a region except the selection inhibited region among the blocks as a second block, and execute the operation of the second block in a second cycle. | 08-29-2013 |