Patent application number | Description | Published |
20100110744 | TERNARY CONTENT ADDRESSABLE MAGNETORESISTIVE RANDOM ACCESS MEMORY CELL - A method for writing a magnetic random access memory-based ternary content addressable memory cell comprising a first magnetic tunnel junction being formed from a storage layer, a sense layer having a magnetization direction adjustable relative to the magnetization of the storage layer, and an insulating layer between the storage and sense layers; a sense line coupled with the storage layer; a first field line and a second field line, and the first field line being orthogonal to the second field line; comprising: providing a first write data to said storage layer via the second field line to store a first stored data with a high or low logic state; characterized in that, the method further comprises providing the first write data to said storage layer via the first field line to store the first stored data with a masked logic state. | 05-06-2010 |
20100208516 | ACTIVE STRAP MAGNETIC RANDOM ACCESS MEMORY CELLS - A magnetic random access memory (MRAM) cell with a thermally assisted writing procedure comprising a magnetic tunnel junction formed from a magnetic storage layer, a reference layer, and an insulating layer inserted between the reference layer and the storage layer; and a first strap portion laterally connecting one end of the magnetic tunnel junction to a first selection transistor; wherein the cell further comprises a second strap portion extending opposite to the first strap portion and connecting laterally said one end of the magnetic tunnel junction to a second selection transistor, and in that said first and second strap portions being adapted for passing a portion of current via the first and second selection transistors. The disclosed cell has lower power consumption than conventional MRAM cells. | 08-19-2010 |
20110002151 | ULTIMATE MAGNETIC RANDOM ACCESS MEMORY-BASED TERNARY CAM - The present disclosure concerns a magnetic random access memory-based ternary content addressable memory cell, comprising a first and second magnetic tunnel junction respectively connected to a first and second straps extending on each side of the first and second magnetic tunnel junctions, respectively; a first and second selection transistors, respectively connected to one extremity of the first and second straps; a first and second current lines; and a conductive line electrically connecting in series the first and second magnetic tunnel junctions at their ends opposed to the ones connecting the first and second straps. The cell disclosed herein has smaller size and can be advantageously used in memory devices having a high cell density array. | 01-06-2011 |
20110291731 | Integrated circuit with timing adjustment mechanism - An integrated circuit | 12-01-2011 |
20130094283 | Apparatus, System, and Method for Writing Multiple Magnetic Random Access Memory Cells with a Single Field Line - A memory device includes a plurality of magnetic random access memory (MRAM) cells, a field line, and a field line controller configured to generate a write sequence that traverses the field line. The write sequence is for writing a multi-bit word to the plurality of MRAM cells. The multi-bit word includes a first subset of bits having a first polarity and a second subset of bits having a second polarity. The write sequence writes concurrently to at least a subset of the plurality of MRAM cells corresponding to the first subset of bits having the first polarity, then subsequently writes concurrently to a remaining subset of the plurality of MRAM cells corresponding to the second subset of bits having the second polarity. | 04-18-2013 |
20140125392 | LOW POWER LATCHING CIRCUITS - A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop. | 05-08-2014 |
20140218089 | LOW POWER LATCHING CIRCUITS - A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop. | 08-07-2014 |
Patent application number | Description | Published |
20090109719 | System and Method for Providing Content-Addressable Magnetoresistive Random Access Memory Cells - A content-addressable random access memory having magnetic tunnel junction-based memory cells and methods for making and using same. The magnetic tunnel junction has first and second magnetic layers and can act as a data store and a data sense. Within each cell, registered data is written by setting a magnetic orientation of the first magnetic layer in the magnetic tunnel junction via current pulses in one or more current lines. Input data for comparison with the registered data can be similarly set through the magnetic orientation of the second magnetic layer via the current lines. The data sense is performed by measuring cell resistance, which depends upon the relative magnetic orientation of the magnetic layers. Since data storage, data input, and data sense are integrated into one cell, the memory combines higher densities with non-volatility. The memory can support high speed, reduced power consumption, and data masking. | 04-30-2009 |
20090213632 | System and Method for Providing Content-Addressable Magnetoresistive Random Access Memory Cells - A content-addressable random access memory having magnetic tunnel junction-based memory cells and methods for making and using same. The magnetic tunnel junction has first and second magnetic layers and can act as a data store and a data sense. Within each cell, registered data is written by setting a magnetic orientation of the first magnetic layer in the magnetic tunnel junction via current pulses in one or more current lines. Input data for comparison with the registered data can be similarly set through the magnetic orientation of the second magnetic layer via the current lines. The data sense is performed by measuring cell resistance, which depends upon the relative magnetic orientation of the magnetic layers. Since data storage, data input, and data sense are integrated into one cell, the memory combines higher densities with non-volatility. The memory can support high speed, reduced power consumption, and data masking. | 08-27-2009 |
20090251957 | SYSTEM AND METHOD FOR WRITING DATA TO MAGNETORESISTIVE RANDOM ACCESS MEMORY CELLS - Magnetic random access memory (MRAM) cell with a thermally assisted switching writing procedure and methods for manufacturing and using same. The MRAM cell includes a magnetic tunnel junction that has at least a first magnetic layer, a second magnetic layer, and an insulating layer disposed between the first and a second magnetic layers. The MRAM cell further includes a select transistor and a current line electrically connected to the junction. The current line advantageously can support a plurality of MRAM operational functions. The current line can fulfill a first function for passing a first portion of current for heating the junction and a second function for passing a second portion of current in order to switch the magnetization of the first magnetic layer. | 10-08-2009 |
20090316476 | SHARED LINE MAGNETIC RANDOM ACCESS MEMORY CELLS - A memory unit with one field line; at least two thermally-assisted switching magnetic tunnel junction-based magnetic random access memory cells, each cell comprising a magnetic tunnel junction having an insulating layer disposed between a magnetic storage layer and a magnetic reference layer; wherein a selection transistor is connected to the magnetic tunnel junction; the one field line is used for passing a field current for switching a magnetization of the storage layer of the magnetic tunnel junctions of the cells. A magnetic memory device can be formed by assembling an array of the memory units, wherein at least two adjacent magnetic tunnel junctions of the cells can be addressed simultaneously by the field line. The memory unit and magnetic memory device have a reduced surface area. Magnetic memory devices with an increased density of memory units can be fabricated resulting in lower die fabrication cost and lower power consumption. | 12-24-2009 |
Patent application number | Description | Published |
20080232479 | ELECTRONIC DEVICE FOR THE TRANSPORT OF NUMERICAL INFORMATION - An electronic device designed to transport digital information (“0”, “1”) over long distances, including a transmitter generating current pulses and at least one assembly of receivers converting the received current pulses into logic pulses which are compatible with the operation of standard electronic logic circuits. Each receiver includes a pair of magnetoresistive stacks containing at least one hard ferromagnetic layer and one soft ferromagnetic layer separated by a non-ferromagnetic interlayer, the hard layer of each of the magnetoresistive stacks being pinned in a magnetic orientation perpendicular to an easy-magnetization axis which is used as a reference for the soft layer of the same stack. The soft layer of each magnetoresistive stack has a magnetic orientation which can be modulated by the magnetic field generated by current pulses delivered by the transmitter so as to cause modification of the transverse resistance of the stack sufficient to trigger an electrical signal. | 09-25-2008 |
20110115522 | MAGNETIC DEVICE FOR PERFORMING A LOGIC FUNCTION - A device for performing a “logic function” consisting of a magnetic structure including at least a first magnetoresistive stack including a first ferromagnetic layer and a second ferromagnetic layer separated by a non-ferromagnetic interlayer and at least one first line of current situated in the vicinity of the first magnetoresistive stack and generating in the vicinity of the first stack a magnetic field when an electric current passes through it. The first line includes at least two current input points so that two currents can be added together in the first line, with the sum of the two currents being determined by the logic function. | 05-19-2011 |
20110221470 | MAGNETIC DEVICE FOR PERFORMING A "LOGIC FUNCTION" - A device for performing a “logic function” including a magnetic structure including at least one first magnetoresistive stack including a first ferromagnetic layer and a second ferromagnetic layer separated by a non-ferromagnetic interlayer, the ferromagnetic hard layer being pinned in a fixed magnetic state which serves as a reference and at least one first and one second current line belonging to a first and a second level of metallization respectively, each of the two lines generating a magnetic field in the vicinity of the first stack when a current flows therethrough. The first and second lines are disposed at various distances of the second ferromagnetic layer, the various distances being determined by the “logic function”. | 09-15-2011 |