Patent application number | Description | Published |
20130244663 | VIRTUAL NEIGHBOR OBJECTS FOR MANAGING IDLE MODE MOBILITY IN A WIRELESS NETWORK - Idle mode reselection is presented herein. A virtual neighbor component can create at least one virtual neighbor object and associate the at least one virtual neighbor object with wireless access points. Further, a reselection component can facilitate idle mode reselection between a base station and a wireless access point of the wireless access points based on the at least one virtual neighbor object. | 09-19-2013 |
20150141018 | METHOD AND APPARATUS FOR MANAGING HANDOVERS IN A WIRELESS NETWORK - A system that incorporates the subject disclosure may include, for example, monitoring a speed and an acceleration of a mobile communication device in a serving cell of a wireless network where the mobile communication device has a radio resource control connection with the wireless network, and selecting a first mobility speed group from among a plurality of mobility speed groups based on the speed and the acceleration of the mobile communication device, where handover parameter values are assigned to each speed group of the plurality of mobility speed groups, and where the handover parameters and their associated values are utilized for a handover by the wireless network from the serving cell to a target cell. Other embodiments are disclosed. | 05-21-2015 |
20150141021 | METHOD AND APPARATUS FOR MANAGING HANDOVERS IN A WIRELESS NETWORK BASED ON SPEED GROUP ASSIGNMENTS - A system that incorporates the subject disclosure may include, for example, determining a mobility speed group assignment for a mobile communication device having a radio resource control connection with a wireless network where the mobility speed group assignment is selected from among a plurality of mobility speed groups according to a speed of the mobile communication device, determining a cell size for a serving cell of the wireless network that is providing the radio resource control connection, and selecting a handover policy based on the mobility speed group assignment and the cell size. Other embodiments are disclosed. | 05-21-2015 |
20150249939 | VIRTUAL NEIGHBOR OBJECTS FOR MANAGING IDLE MODE MOBILITY IN A WIRELESS NETWORK - Idle mode reselection is presented herein. A virtual neighbor component can create at least one virtual neighbor object and associate the at least one virtual neighbor object with wireless access points. Further, a reselection component can facilitate idle mode reselection between a base station and a wireless access point of the wireless access points based on the at least one virtual neighbor object. | 09-03-2015 |
Patent application number | Description | Published |
20100270026 | Spectral Shaping Inversion And Migration of Seismic Data - A geophysical model of a subsurface region is generated based on seismic data, e.g., seismic reflection data. Migration and seismic inversion are applied to the seismic data to generate estimates of one or more physical or seismic properties of the subsurface region. Seismic inversion, such as spectral shaping inversion, is applied before or after migrating the seismic data through a variety of techniques that each avoid the amplification of dipping energy while optimizing computational efficiency and/or accuracy. | 10-28-2010 |
20120073824 | Hybride Method For Full Waveform Inversion Using Simultaneous and Sequential Source Method - Method for simultaneous full-wavefield inversion of gathers of source (or receiver) encoded geophysical data to determine a physical properties model for a subsurface region, especially suitable for surveys where fixed receiver geometry conditions were not satisfied in the data acquisition. First, a shallow time window of the data ( | 03-29-2012 |
20120073825 | Simultaneous Source Encoding and Source Separation As A Practical Solution For Full Wavefield Inversion - Method for simultaneous full-wavefield inversion of gathers of source (or receiver) encoded geophysical data to determine a physical properties model ( | 03-29-2012 |
20120143506 | Simultaneous Source Inversion for Marine Streamer Data With Cross-Correlation Objective Function - Method for simultaneous full-wavefield inversion of gathers of source (or receiver) encoded ( | 06-07-2012 |
20140350861 | MULTI-PARAMETER INVERSION THROUGH OFFSET DEPENDENT ELASTIC FWI - Method for multi-parameter inversion using elastic inversion. This method decomposes data into offset/angle groups and performs inversion on them in sequential order. This method can significantly speed up convergence of the iterative inversion process, and is therefore most advantageous when used for full waveform inversion (FWI). The present inventive approach draws upon relationships between reflection energy and reflection angle, or equivalently, offset dependence in elastic FWI. The invention uses recognition that the amplitudes of small angle (near offset) reflections are largely determined by acoustic impedance alone ( | 11-27-2014 |
Patent application number | Description | Published |
20090247507 | Enzyme Inhibitors - Compounds of formula (I), are aurora kinase inhibitors: wherein X is —N—, —CH2—N—, —CH2—CH—, or —CH—; R1 is a radical of formula (IA) wherein Z is —CH2—, —NH—, -0-, —S(O)— —S—, —S(O)2 or a divalent monocyclic carbocyclic or heterocyclic radical having 3-7 ring atoms; Alk is an optionally substituted divalent C1-C6 alkylene radical; A is hydrogen or an optionally substituted monocyclic carbocyclic or heterocyclic ring having 5-7 ring atoms; r, s and t are independently 0 or 1, provided that when A is hydrogen then at least one of r and s is 1; R2 is halogen, —CN, —CF3, —OCH3, or cyclopropyl; and R3 is a radical of formula (IB) wherein Q is hydrogen or an optionally substituted phenyl or monocyclic heterocyclic ring with 5 or 6 ring atoms; Z&It;1> is —S—, —S(O)—, —S(O)2—, —O—, —SO2NH—, —NHSO2—, NHC(═O)NH, —NH(C═S)NH—, Or —N(R4)—wherein R4 is hydrogen, C1-C3 alkyl, cycloalkyl, or benzyl; and Alk&It;1> and Alk&It;2> are, independently, optionally substituted divalent C1-C3 alkylene radicals; and m, n and p are independently 0 or 1. Data supplied from the esp@cenet datatbase—Worldwide d77 | 10-01-2009 |
Patent application number | Description | Published |
20130065800 | COATED AND CURED PROPPANTS - Solid proppants are coated with a coating that exhibits the handling characteristics of a pre-cured coating while also exhibiting the ability to form particle-to-particle bonds at the elevated temperatures and pressures within a wellbore. The coating includes a substantially homogeneous mixture of (i) at least one isocyanate component having at least 2 isocyanate groups, and (ii) a curing agent comprising a monofunctional alcohol, amine or amide. The coating process can be performed with short cycle times, e.g., less than about 4 minutes, and still produce a dry, free-flowing, coated proppant that exhibits low dust characteristics during pneumatic handling but also proppant consolidation downhole for reduced washout and good conductivity. Such proppants also form good unconfined compressive strength without use of an bond activator, are substantially unaffected in bond formation characteristics under downhole conditions despite prior heat exposure, and are resistant to leaching with hot water. | 03-14-2013 |
20140162911 | PROPPANT WITH COMPOSITE COATING - Proppants for hydraulic fracturing of oil and gas wells have a polymeric coating that is strengthened with reinforcing particulates that are reactive with, or chemically bonded to, the polymeric proppant coating. Preferably, these particulates are added into the coating during the coating process. In one embodiment, functionalized particulates are used that become grafted into the polymer of the proppant coating through the chemical functionality imparted to the particulates. If non-functionalized particulates are used, a coupling agent is preferably added to enhance the bond strength between the added particulates and the polymeric matrix of the proppant coating. | 06-12-2014 |
20140274819 | Proppant With Polyurea-Type Coating - Proppants for hydraulic fracturing of oil and gas wells are coated with a polyurea-type coating. In a preferred embodiment, the polyurea-type coating is formed by contacting a polymeric isocyanate with an amount of water and a blowing catalyst at a rate and quantity sufficient to generate a reactive amine in situ on the outer surface of the proppant which thereby reacts with unconverted polymeric isocyanate to form a thin polyurea-type surface coating that is substantially solid and lacks foam or substantial porosity. Alternatively, the polyurea-type can be produced by selecting reactive amine compounds and isocyanates to develop the coated proppant. The coated proppants retain the discrete, free-flowing character of the original core solids but with the beneficial effects of the polyurea-type coating of the present invention. | 09-18-2014 |
20140338906 | Proppant With Enhanced Interparticle Bonding - Polymer-coated proppants for hydraulic fracturing of oil and gas wells have an outer layer portion that comprises an organofunctional coupling agent, preferably an organofunctional silane coupling agent. The use of an organofunctional silane coupling agent in the outer layer portion of the proppant coating is preferably chosen to expose functionalities that will be reactive towards similar functionalities of adjacent and similarly coated proppants so that, when introduced downhole, these proppants form interparticle bonds at the temperatures and crack closure pressures found downhole in fractured strata. Such enhanced interparticle bonding helps keep the proppant in the fracture and maintains conductivity with reduced flowback. The invention also helps proppants designed for low temperature well to bond more firmly and allows proppants designed for high temperature wells to bond well even at lower downhole temperatures, thereby extending their useful range. | 11-20-2014 |
Patent application number | Description | Published |
20120021609 | DEPOSITION OF VISCOUS MATERIAL - Embodiments of the invention provide methods and systems for depositing a viscous material on a substrate surface. In one embodiment, the invention provides a method of depositing a viscous material on a substrate surface, the method comprising: applying a pre-wet material to a surface of a substrate; depositing a viscous material atop the pre-wet material; rotating the substrate about an axis to spread the viscous material along the surface of the substrate toward a substrate edge; and depositing additional pre-wet material in a path along the surface and adjacent the spreading viscous material. | 01-26-2012 |
20120146175 | INSULATING REGION FOR A SEMICONDUCTOR SUBSTRATE - An insulating region for a semiconductor wafer and a method of forming same. The insulating region can include a tri-layer structure of silicon oxide, boron nitride and silicon oxide. The insulating region may be used to insulate a semiconductor device layer from an underlying bulk semiconductor substrate. The insulating region can be formed by coating the sides of a very thin cavity with silicon oxide, and filling the remainder of the cavity between the silicon oxide regions with boron nitride. | 06-14-2012 |
20120186514 | DEPOSITION OF VISCOUS MATERIAL - Embodiments of the invention provide methods and systems for depositing a viscous material on a substrate surface. In one embodiment, the invention provides a method of depositing a viscous material on a substrate surface, the method comprising: applying a pre-wet material to a surface of a substrate; depositing a viscous material atop the pre-wet material; rotating the substrate about an axis to spread the viscous material along the surface of the substrate toward a substrate edge; and depositing additional pre-wet material in a path along the surface and adjacent the spreading viscous material. | 07-26-2012 |
20130307160 | Via Structure For Three-Dimensional Circuit Integration - Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount. | 11-21-2013 |
20140356981 | WAFER BONDING MISALIGNMENT REDUCTION - A method for wafer bonding includes measuring grid distortion for a mated pairing of wafers to be bonded to determine if misalignment exists between the wafers. During processing of subsequent wafers, magnification of one or more lithographic patterns is adjusted to account for the misalignment. The subsequent wafers are bonded with reduced misalignment. | 12-04-2014 |
20150035169 | VIA STRUCTURE FOR THREE-DIMENSIONAL CIRCUIT INTEGRATION - Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount. | 02-05-2015 |
20150221610 | SEPARATING BONDED WAFERS - Separating bonded wafers. A bonded wafer pair is mounted between first and second bonding chucks having flat chuck faces, the first bonding chuck face including adjustable zones capable of movement relative to each other, at least a component of the relative movement is along an axis that is perpendicular to the flat first bonding chuck face. The adjustable zones of the first face are moved relative to each other in a coordinated manner such that a widening gap is formed between the bonding faces of the wafer pair. | 08-06-2015 |
20150318260 | GAS-CONTROLLED BONDING PLATFORM FOR EDGE DEFECT REDUCTION DURING WAFER BONDING - A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework. A bottom wafer is placed on a bottom bonding framework that includes a plurality of inlet holes around a periphery of the bottom bonding framework. The top bonding framework is in overlapping relation to the bottom bonding framework such that a gap exist between the top wafer and the bottom wafer. A gas stream is circulated through the gap between the top wafer and the bottom wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the top wafer and the bottom wafer. | 11-05-2015 |
20150357197 | SELECTIVE ETCHING OF SILICON WAFER - A method of preparing an etch solution and thinning semiconductor wafers using the etch solution is proposed. The method includes steps of creating a mixture of hydrofluoric acid, nitric acid, and acetic acid in a solution container in an approximate 1:3:5 ratio; causing the mixture to react with portions of one or more silicon wafers, the portions of the one or more silicon wafers are doped with boron in a level no less than 1×10 | 12-10-2015 |
20150357207 | SELECTIVE ETCHING OF SILICON WAFER - An apparatus that includes a solution bath of a seasoned solution, the seasoned solution containing a mixture of hydrofluoric acid, nitric acid, and acetic acid; and one or more silicon wafers being suspended in a position above the solution bath, wherein at least a portion of the mixture having been used in thinning the one or more silicon wafers. | 12-10-2015 |
20160035616 | HANDLER WAFER REMOVAL BY USE OF SACRIFICIAL INERT LAYER - The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to the temporary bonding of a semiconductor wafer to handler wafer during processing. The semiconductor wafer may be temporarily bonded to the handler wafer by forming a sacrificial layer on a surface of a handler wafer, forming a first dielectric layer on a surface of the sacrificial layer, forming a second dielectric layer on a surface of a semiconductor wafer, and directly bonding the first dielectric layer and the second dielectric layer to form a bonding layer. After the semiconductor wafer is processed, it may be removed from the handler wafer along with the bonding layer by degrading the sacrificial layer with infrared radiation transmitted through the handler wafer. | 02-04-2016 |
20160141263 | SEMICONDUCTOR DEVICE INCLUDING BUILT-IN CRACK-ARRESTING FILM STRUCTURE - According to at least one embodiment of the present invention, a wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface. | 05-19-2016 |
Patent application number | Description | Published |
20090139451 | PROCESS OF MONITORING DISPENSING OF PROCESS FLUIDS IN PRECISION PROCESSING OPERATIONS - A process of monitoring the dispensing of process fluids in precision processing operations. A precision measuring instrument measures a cumulative amount of a process fluid dispensed to at least one dispensing station and compares that amount with a predetermined amount. An alarm is provided to an operator when the cumulative actual required amount of process fluid dispensed after a preset number of dispensations differs from the cumulative predetermined dispensed amount of that fluid by more than a preset percentage. | 06-04-2009 |
20110254138 | LOW-TEMPERATURE ABSORBER FILM AND METHOD OF FABRICATION - An improved low-temperature absorber, amorphous carbonitride (ACN) with an extinction coefficient (k) of greater than 0.15, and an emissivity of greater than 0.8 is disclosed. The ACN film can also be characterized as having a minimum of hydrocarbon content as observed by FTIR. The ACN film can be used as an effective absorbing layer that absorbs a wide range of electromagnetic radiation from different sources including lasers or flash lamps. A method of forming such an ACN film at a deposition temperature of less than, or equal to, 450° C. is also provided. | 10-20-2011 |
20130328174 | Edge Protection of Bonded Wafers During Wafer Thinning - A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers. | 12-12-2013 |
20140261960 | WAFER-TO-WAFER OXIDE FUSION BONDING - Oxide-oxide fusion bonding of wafers that includes performing a van der Waals force bonding process with a chuck having at least a flat central zone and an outer annular zone lower than the central zone, an edge portion of a mounted wafer is biased towards the outer annular zone. The van der Waals bonding wave is disrupted at the outer annular zone, causing an edge gap. A thermocompression bonding process is performed that includes heating the bonded wafers to a temperature sufficient to initiate condensation of silanol groups between the bonding surfaces, reducing the atmospheric pressure to cause degassing from between the wafers, applying a compression force to the wafers with flat chucks so as to substantially eliminate the edge gap, and performing a permanent anneal bonding process. | 09-18-2014 |
20140265165 | WAFER-TO-WAFER FUSION BONDING CHUCK - A chuck face of a wafer bonding chuck that includes a flat central zone and an outer annular zone contiguous to the central zone, the outer annular zone being lower than the flat central zone such that an annular edge portion of a wafer that is mounted to the chuck face has a convex profile with respect to the chuck face of the bonding chuck. The outer annular zone may move along an axis that is perpendicular to the central zone. The chuck face may include a plurality of contiguous zones, with at least one of the zones moveable with respect to another of the zones. | 09-18-2014 |
20140353828 | SUBSTRATE BONDING WITH DIFFUSION BARRIER STRUCTURES - A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer. | 12-04-2014 |
20140353839 | MANGANESE OXIDE HARD MASK FOR ETCHING DIELECTRIC MATERIALS - A manganese oxide layer is deposited as a hard mask layer on substrate including at least a dielectric material layer. An optional silicon oxide layer may be formed over the manganese oxide layer. A patterned photoresist layer can be employed to etch the optional silicon oxide layer and the manganese oxide layer. An anisotropic etch process is employed to etch the dielectric material layer within the substrate. The dielectric material layer can include silicon oxide and/or silicon nitride, and the manganese oxide layer can be employed as an effective etch mask that minimizes hard mask erosion and widening of the etched trench. The manganese oxide layer may be employed as an etch mask for a substrate bonding process. | 12-04-2014 |
20140356983 | DISTORTING DONOR WAFER TO CORRESPONDING DISTORTION OF HOST WAFER - A method generally for improving wafer-to-wafer bonding alignment. Planar distortions of the bonding surface of a host wafer are determined. The bonding surface of a donor wafer is distorted such that the distortions of the donor wafer bonding surface correspond to the determined planar distortions of the host wafer bonding surface. Also, a method to separate bonded wafers. A bonded wafer pair is mounted between first and second bonding chucks having flat chuck faces, the first bonding chuck face including adjustable zones capable of movement relative to each other, at least a component of the relative movement is along an axis that is perpendicular to the flat first bonding chuck face. The adjustable zones of the first face are moved relative to each other in a coordinated manner such that a widening gap is formed between the bonding faces of the wafer pair. | 12-04-2014 |
20150069421 | WAFER TO WAFER ALIGNMENT BY LED/LSD DEVICES - A method for wafer alignment includes forming a first alignment circuit within a first semiconductor wafer; the first alignment circuit is configured to emit an optical signal. Next, the first alignment circuit is activated upon receiving a first activation signal from a wafer bonding tool then the optical signal is sent to a second alignment circuit in a second semiconductor wafer in overlapping relation to the first semiconductor wafer. The second alignment circuit transmits a second activation signal to the wafer bonding tool and consequently the wafer bonding tool initiates an alignment technique between the first and second semiconductor wafers. The alignment technique uses the first and second alignment circuits for optical alignment. | 03-12-2015 |
20150072444 | Reducing Wafer Bonding Misalignment By Varying Thermal Treatment Prior To Bonding - A bonding layer of the first wafer article is thermally treated and a bonding layer of a second wafer article is thermally treated in accordance with first and second process parameters, respectively prior to bonding the first wafer article with the second wafer article. First and second grid distortion in the first and second wafer articles is measured and a difference is determined between the first and second grid distortions. A prediction is made for maintaining the difference within a prescribed tolerance. At least one of the first process parameters and the second process parameters can be conditionally varied in accordance with the prediction. The thermally treating of the first wafer article and the thermally treating of the second wafer article can then be performed with respect to another pair of the first and second wafer articles prior to bonding the another pair of wafer articles to one another through their respective bonding layers. | 03-12-2015 |
20150132924 | HANDLER WAFER REMOVAL - A method of removing a handler wafer. There is provided a handler wafer and a semiconductor device wafer having a plurality of semiconductor devices, the semiconductor device wafer having an active surface side and an inactive surface side. An amorphous carbon layer is applied to a surface of the handler wafer. An adhesive layer is applied to at least one of the amorphous carbon layer of the handler wafer and the active surface side of the semiconductor device wafer. The handler wafer is joined to the semiconductor device wafer through the adhesive layer or layers. Laser radiation is applied to the handler wafer to cause heating of the amorphous carbon layer that in turn causes heating of the adhesive layer or layers. The plurality of semiconductor devices of the semiconductor device wafer are then separated from the handler wafer. | 05-14-2015 |
20150155263 | FACILITATING CHIP DICING FOR METAL-METAL BONDING AND HYBRID WAFER BONDING - A method of forming a stacked assembly of semiconductor chips can include juxtaposing and metallurgically joining kerf metal elements exposed in kerf regions of a first wafer with corresponding kerf metal elements exposed in kerf regions of a second wafer, and affixing undiced semiconductor chips of the first wafer with corresponding undiced semiconductor chips of the second wafer. The assembled wafers are then cut along the dicing lanes thereof into a plurality of individual assemblies of stacked semiconductor chips, each assembly including an undiced semiconductor chip of the first wafer and an undiced semiconductor chip of the second wafer affixed therewith. | 06-04-2015 |
20150187733 | COMBINATION OF TSV AND BACK SIDE WIRING IN 3D INTEGRATION - The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip. | 07-02-2015 |
20150255417 | FACILITATING CHIP DICING FOR METAL-METAL BONDING AND HYBRID WAFER BONDING - A method of forming a stacked assembly of semiconductor chips can include juxtaposing and metallurgically joining kerf metal elements exposed in kerf regions of a first wafer with corresponding kerf metal elements exposed in kerf regions of a second wafer, and affixing undiced semiconductor chips of the first wafer with corresponding undiced semiconductor chips of the second wafer. The assembled wafers are then cut along the dicing lanes thereof into a plurality of individual assemblies of stacked semiconductor chips, each assembly including an undiced semiconductor chip of the first wafer and an undiced semiconductor chip of the second wafer affixed therewith. | 09-10-2015 |
20150262976 | SUBSTRATE BONDING WITH DIFFUSION BARRIER STRUCTURES - A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer. | 09-17-2015 |
20150279709 | REDUCING WAFER BONDING MISALIGNMENT BY VARYING THERMAL TREATMENT PRIOR TO BONDING - A bonding layer of a first wafer article is thermally treated and a bonding layer of a second wafer article is thermally treated in accordance with first and second process parameters, respectively prior to bonding the first wafer article with the second wafer article. First and second grid distortion in the first and second wafer articles is measured and a difference is determined between the first and second grid distortions. A prediction is made for maintaining the difference within a prescribed tolerance. At least one of the first process parameters and the second process parameters is conditionally varied in accordance with the prediction. The thermal treating of the first and second wafer articles can then be performed with respect to another pair of the first and second wafer articles prior to bonding to one another through their respective bonding layers. | 10-01-2015 |
20150348842 | MANGANESE OXIDE HARD MASK FOR ETCHING DIELECTRIC MATERIALS - A manganese oxide layer is deposited as a hard mask layer on substrate including at least a dielectric material layer. An optional silicon oxide layer may be formed over the manganese oxide layer. A patterned photoresist layer can be employed to etch the optional silicon oxide layer and the manganese oxide layer. An anisotropic etch process is employed to etch the dielectric material layer within the substrate. The dielectric material layer can include silicon oxide and/or silicon nitride, and the manganese oxide layer can be employed as an effective etch mask that minimizes hard mask erosion and widening of the etched trench. The manganese oxide layer may be employed as an etch mask for a substrate bonding process. | 12-03-2015 |
20150371927 | COMBINATION OF TSV AND BACK SIDE WIRING IN 3D INTEGRATION - The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip. | 12-24-2015 |
20160118348 | STRAIN DETECTION STRUCTURES FOR BONDED WAFERS AND CHIPS - Strain detection structures used with bonded wafers and chips and methods of manufacture are disclosed. The method includes forming lower metal wiring structures associated with a lower wafer structure. The method further includes bonding the lower wafer structure to an upper wafer structure and thinning the upper wafer, and forming upper metal wiring structures. The method further includes electrically linking the lower metal wiring structures to the upper metal wiring structures by formation of through silicon via structures to form an electrically connected chain extending between multiple wafer structures. The method further includes forming contacts to an outside environment which electrically contact two of the lower metal wiring structures. | 04-28-2016 |