Patent application number | Description | Published |
20080263495 | Software product for semiconductor device design - A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection; and by producing a library configured to store parameters indicating the parasitic resistance and the parasitic capacitance in relation to the target interconnection to each of the plurality of patterns. The producing is achieved by calculating the parameters to a plurality of conditions corresponding to deviation in manufacture of the wiring structure for each of the plurality of patterns. | 10-23-2008 |
20090024968 | Method of designing semiconductor integrated circuit and mask data generation program - A method of designing a semiconductor integrated circuit includes: generating a layout data indicating a layout; and generating a mask data based on the layout data. The generating the mask data includes: referring to the layout data to extract a parameter that specifies a layout pattern around a target transistor included in the semiconductor integrated circuit, wherein the parameter includes at least a width of a device isolation structure around the target transistor; correcting a gate length and a gate width of the target transistor to offset a variation of a characteristic of the target transistor from a design value, the variation depending on the extracted parameter; and generating the mask data from the layout data in which the gate length and the gate width are corrected. | 01-22-2009 |
20090024973 | Method and program for designing semiconductor integrated circuit - A method of designing a semiconductor integrated circuit includes: performing a circuit simulation of a cell with changing a parameter that specifies a layout pattern around the cell; and generating a delay function expressing a delay value of the cell as a function of the parameter, based on a result of the circuit simulation. The method further includes: generating a layout data indicating a layout of the semiconductor integrated circuit, based on a cell-based design technique. The method further includes: referring to the generated layout data to extract the parameter associated with a target cell included in the semiconductor integrated circuit; and calculating a delay value of the target cell by using the extracted parameter and the delay function. | 01-22-2009 |
20090024974 | Method and program for designing semiconductor integrated circuit - A design method for an LSI includes: generating a delay library for use in a statistical STA, wherein the delay library provides a delay function that expresses a cell delay value as a function of model parameters of a transistor; generating a layout data; and calculating a delay value of a target cell based on the delay library and the layout data. The calculating includes: referring to the layout data to extract a parameter specifying a layout pattern around a target transistor; modulating model parameters of the target transistor such that the characteristics corresponding to the extracted parameter is obtained in a circuit simulation; calculating, by using the delay function, a reference delay value of the target cell; and calculating, by using the delay function and the modulation amount of the model parameter, a delay variation from the reference delay value depending on the modulation amount. | 01-22-2009 |
20090070725 | Method and system for manufacturing a semiconductor device having plural wiring layers - A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection; and by producing a library configured to store parameters indicating the parasitic resistance and the parasitic capacitance in relation to the target interconnection to each of the plurality of patterns. The producing is achieved by calculating the parameters to a plurality of conditions corresponding to deviation in manufacture of the wiring structure for each of the plurality of patterns. | 03-12-2009 |
20090089037 | Method and apparatus for circuit simulation in view of stress exerted on MOS transistor - A circuit simulation method includes: generating graphical data indicating dimensions of a subject MOS transistor; calculating a parameter correction amount based on said graphical data; correcting a given transistor model parameter in response to said parameter correction amount; and performing circuit simulation of a circuit that includes said subject MOS transistor by using said corrected transistor model parameter. The parameter correction amount is calculated based on said graphical data by using arithmetic equations. The arithmetic equations include at least one stress model equation expressing a stress exerted on a channel region of a model MOS transistor. The stress model equation is suitably defined to simulate the stress exerted on the channel region. | 04-02-2009 |
20110066410 | CIRCUIT SIMULATION METHOD - A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a well resistor comprising a terminal region and a main body; and a plurality of contacts formed above the terminal region, the simulation method comprising: modeling a parasitic resistance Rt | 03-17-2011 |
20110066418 | CIRCUIT SIMULATION METHOD - A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a semiconductor resistor; a plurality of contacts arranged at regular intervals in a longitudinal direction and in a width direction of the semiconductor resistor on a terminal region of the semiconductor resistor; and a wiring line formed on the plurality of contacts, the simulation method including: defining a ratio of a parasitic-resistance by the semiconductor resistor between two of the contacts neighboring in the longitudinal direction to a resistance of one of the plurality of contacts as a constant k; and modeling a parasitic-resistance net by using the constant k, the parasitic-resistance net including the terminal region of the semiconductor resistor and the plurality of contacts. | 03-17-2011 |
Patent application number | Description | Published |
20090108878 | HIGH-FREQUENCY CLOCK DETECTION CIRCUIT - In order to provide a high frequency clock detection circuit capable to detect a high frequency clock using any period as a threshold, the high frequency clock detection circuit of the present invention includes a delay circuit having a delay time set to be longer than a clock period corresponding to the irregular high frequency state, a first flip-flop circuit for delay flip-flopping according to the clock signal and for being provided with the inverted and feedback inputted output from the first flip-flop circuit, a second flip-flop circuit for delay flip-flopping according to the clock signal and for being provided with the inverted and feedback inputted output from the second flip-flop circuit through the delay circuit, and a detection-result output circuit for detecting a difference between the output signal from the first flip-flop circuit and the output signal from the second flip-flop circuit and for providing the function circuit with the high frequency clock detection signal indicating the irregular high frequency state corresponding to an occurrence of the difference. | 04-30-2009 |
20150235613 | MEDICAL IMAGE DISPLAY CONTROL APPARATUS AND OPERATION METHOD OF THE SAME, AND MEDIUM - Providing a parameter calculation unit that calculates parameters representing medical functional information for pixel positions of the medical image, wherein the upper and lower limit values of the parameter medically represent the same functional information and whose value changes cyclically between these values, an interpolation parameter calculation unit that obtains, for a pixel position for which the parameter is not calculated, a parameter by interpolation, the unit calculating a parameter obtained by the interpolation using a cyclic function in which the interpolation direction differs according to the difference between the parameters calculated for two pixel positions, a display color group storage unit that includes a color group in which the same color corresponds to the upper and lower limit values of the parameter and whose color changes with the magnitude of the parameter, and a mapping unit that maps the parameters based on the color group. | 08-20-2015 |
20150282887 | IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, AND A NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM CONTAINING AN IMAGE PROCESSING PROGRAM - Extracting a tubular structure from volume data, determining a target region which should be reached by an endoscope through the tubular structure, extracting, among plurality on a route of the tubular structure, a point that satisfies a given condition as a target point that should be reached by a distal end portion of the endoscope, and identifying and determining a route of the tubular structure from a predetermined start point in the tubular structure to the extracted target point as a route through which the endoscope should be passed. | 10-08-2015 |
20150286395 | COMPUTER WITH TOUCH PANEL, OPERATION METHOD, AND RECORDING MEDIUM - In a computer with a touch panel, displaying a plurality of images on the touch panel using a display parameter preset to each image, and changing, when a touch gesture associated with changing the display parameter is performed on the touch panel for any one of the plurality of displayed images, the display parameter according to the touch gesture for all of the images other than an image somewhere in the display area of which is being pressed when the touch gesture is performed. | 10-08-2015 |
20160035071 | CURVED LINE CORRECTION APPARATUS, METHOD, AND MEDIUM - A curved line correction apparatus includes a correction target receiving unit that receives selection of a correction target point when an instruction mark is placed on an arbitrary point on a curved line composed of a plurality of arranged points, a correction target range setting unit that sets a certain range of the curved line, including the correction target point, as a correction target range, and a correction unit that corrects a portion of the curved line within the correction target range by moving the correction target point and a point within the correction target range when movement of the instruction mark is received, in which the correction target range setting unit changes the size of the correction target range when an instruction input to change the range is received with the instruction mark being placed on the correction target point. | 02-04-2016 |
20160067008 | IMAGE DISPLAY APPARATUS, METHOD AND PROGRAM - A first tomographic image of a three-dimensional image is displayed on a display screen, and a cursor to be operated by a user is also displayed in the displayed first tomographic image, and at least one second tomographic image intersecting the first tomographic image at a three-dimensional position in the three-dimensional image corresponding to a two-dimensional position pointed by the cursor in the first tomographic image is also displayed. A user input by a button operation giving an instruction to move the cursor is received. The cursor is moved to a two-dimensional position in one of the at least one second tomographic image corresponding to the three-dimensional position in the three-dimensional image corresponding to the two-dimensional position pointed by the cursor in the first tomographic image. | 03-10-2016 |
20160086049 | CONTOUR CORRECTION DEVICE, METHOD, AND PROGRAM - An input to set a correction contour line inside one region from an operator is received, and a contour line of the one region is corrected so that the correction contour line becomes a part of a contour line after correction. In this case, when a start point of the correction contour line is located on a unique contour line of each region and an end point thereof is located on a contour line shared by the two regions, the contour line of the other region is maintained, and when the start point is located on the shared contour line and the end point is located on the unique contour line, the contour line of the other region is also corrected so that the correction contour line becomes the shared contour line in the contour lines of the two regions after the correction. | 03-24-2016 |
Patent application number | Description | Published |
20130312880 | DUPLEX STAINLESS STEEL AND PRODUCTION METHOD THEREFOR - Provided is a duplex stainless steel having a high strength and a high toughness. A stainless steel according to the present invention includes: a chemical composition containing, in mass percent, C: at most 0.030%, Si: 0.20 to 1.00%, Mn: at most 8.00%, P: at most 0.040%, S: at most 0.0100%, Cu: more than 2.00% and at most 4.00%, Ni: 4.00 to 8.00%, Cr: 20.0 to 30.0%, Mo: at least 0.50% and less than 2.00%, N: 0.100 to 0.350%, and sol. Al: at most 0.040%, the balance being Fe and impurities; and a structure, wherein a rate of ferrite in the structure is 30 to 70%, and a hardness of the ferrite in the structure is at least 300 Hv | 11-28-2013 |
20130315776 | DUPLEX STAINLESS STEEL - A duplex stainless steel, which can suppress precipitation of a σ phase under high heat input welding, is excellent in SCC resistance under high-temperature chloride environments and has a high strength. The duplex stainless steel includes a chemical composition containing, in mass percent, C: at most 0.030%, Si: 0.20 to 1.00%, Mn: at most 8.00%, P: at most 0.040%, S: at most 0.0100%, Cu: more than 2.00% and at most 4.00%, Ni: 4.00 to 8.00%, Cr: 20.0 to 28.0%, Mo: 0.50 to 2.00%, N: 0.100 to 0.350%, and sol. Al: at most 0.040%, the balance being Fe and impurities, and satisfying Expression (1) and Expression (2); a structure having a ferrite rate of at least 50%; and a yield strength of at least 550 MPa or more: | 11-28-2013 |
20130316193 | WELDED JOINT OF DUPLEX STAINLESS STEEL - A welded joint of duplex stainless steel, which can suppress precipitation of σ phase under high heat input welding, is excellent in SCC resistance under high-temperature chloride environments. A weld metal of the welded joint contains, in mass percent, C: at most 0.030%, Si: 0.20 to 1.00%, Mn: at most 8.00%, P: at most 0.040%, S: at most 0.0100%, Cu: at most 2.00%, Ni: 7.00 to 12.00%, Cr: 20.0 to 30.0%, Mo: 1 to 4%, N: 0.100 to 0.350%, sol. Al: at most 0.040%, and O: at most 0.035%, the balance being Fe and impurities. The weld metal satisfies Expressions (1) and (3): | 11-28-2013 |
20150056005 | PROCESS FOR PRODUCING WELDED JOINT, AND WELDED JOINT - Provided is a process for producing a welded joint which includes a weld metal having high strength and high toughness, and containing fewer blowholes. The process for producing a welded joint according to the present embodiment includes the steps of: preparing a base material containing, by mass %, not less than 10.5% of Cr; and subjecting the base material to GMA welding using a shielding gas containing 1 to 2 volume % or 35 to 50 volume % of CO | 02-26-2015 |
Patent application number | Description | Published |
20130240974 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a semiconductor substrate, a pair of select gate transistors provided on a first region of the semiconductor substrate, a plurality of memory cell transistors provided on a second region provided between the pair of select gate transistors on the semiconductor substrate, a gate electrode of each of the memory cell transistors, the gate electrode provided on the second region via a first insulating film, and including a charge storage layer, an intermediate insulating film, and a control gate electrode film stacked therein, a groove exposed a sidewall of the semiconductor substrate on the first region; and a gate electrode of each of the select gate transistors, the gate electrode including the control gate electrode film formed on the sidewall via a second insulating film. | 09-19-2013 |
20140070304 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a nonvolatile memory device includes a memory cell string, a control gate, first and second insulating films. The memory cell string includes a semiconductor layer and a plurality of memory cells disposed on the semiconductor layer. The control gate is provided on each of the memory cells. The first insulating film covers each side surface of the memory cells, and a side surface of the control gate. The second insulating film covering an upper portion of the control gate is provided on each of two adjacent memory cells. A first air gap is disposed between the two adjacent memory cells and surround by the first insulating film and the second insulating film, and the semiconductor layer is exposed by the first gap, or thickness of an insulating film between the first gap and the semiconductor layer is thinner than the first insulating film. | 03-13-2014 |
20140070305 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a non-volatile memory device includes a memory cell including a semiconductor layer, a charge storage layer provided on the semiconductor layer, and a first insulating film provided between the semiconductor layer and the charge storage layer. The device also includes a first conductive layer provided on the charge storage layer, a second conductive layer provided between the charge storage layer and the first conductive layer, a second insulating film provided between the charge storage layer and the second conductive layer, and a third insulating film provided between the first conductive layer and the second conductive layer. | 03-13-2014 |