Patent application number | Description | Published |
20080217720 | Dual isolation for image sensors - Methods, methods of making, devices, and systems for image sensors that include isolation regions are disclosed. A semiconductor imager includes a pixel array and peripheral circuitry arranged on at least one side of the pixel array. Array devices are formed as part of the pixel array and periphery devices are formed in the periphery. Array isolation regions are disposed around at least a portion of at least some of the array devices and periphery isolation regions are disposed around at least a portion of at least some of the periphery devices. Within the semiconductor imager, the periphery isolation regions are configured differently from the array isolation regions. The semiconductor image sensor may be included in as part of an imaging system that includes a processor. | 09-11-2008 |
20090046189 | Method and apparatus providing shared pixel straight gate architecture - Methods and apparatuses using four-way-shared readout circuits to increase pixel fill factor. | 02-19-2009 |
20090053848 | Method and apparatus providing imager pixels with shared pixel components - The disclosed embodiments employ shared pixel component architectures that arrange the shared pixel components for a group of pixels within different pixels of the group. | 02-26-2009 |
20090075465 | METHODS OF FORMING A CONDUCTIVE INTERCONNECT IN A PIXEL OF AN IMAGER AND IN OTHER INTEGRATED CIRCUITRY - A method of forming conductive interconnects includes forming a node of a circuit component on a substrate. A conductive metal line is formed at a first metal routing level that is elevationally outward of the circuit component. Insulative material is deposited above the first metal routing level over the conductive metal line and the circuit component. In a common masking step, a first opening is etched through the insulative material to the conductive metal line and a second opening is etched through the insulative material to the node of the circuit component that is received elevationally inward of the conductive metal line. Conductive material is concurrently deposited to within the first and second openings in respective conductive connection with the conductive metal line and the node of the circuit component. A first metal line at a second metal routing level that is above the first metal routing level is formed in conductive connection with the conductive material in the first opening. A second metal line at the second metal routing level is formed in conductive connection with the conductive material in the second opening. | 03-19-2009 |
20090090845 | Method and apparatus providing shared pixel architecture - Methods and apparatuses using pixels with shared readout circuits are used to increase pixel fill factor and operation efficiency. | 04-09-2009 |
20090127437 | METHOD AND APPARATUS FOR REDUCING DARK CURRENT AND HOT PIXELS IN CMOS IMAGE SENSORS - Methods and apparatuses for reducing dark current and hot pixels in CMOS image sensors. A pixel apparatus includes a photosensor capable of generating dark current, a floating diffusion region coupled to the photosensor by way of a charge transfer transistor, a rest transistor connected between the floating diffusion region and an array pixel supply voltage. The array supply voltage varies between first and second voltages when sampling pixel signals from the pixel. | 05-21-2009 |
20090184345 | CONTACTS FOR CMOS IMAGERS AND METHOD OF FORMATION - Low leakage contacts on leakage sensitive areas of a CMOS imager, such as a floating diffusion region or a photodiode, are disclosed. At least one low leakage polysilicon contact is provided over a leakage sensitive area of a CMOS imager. The polysilicon contact comprises a polysilicon region in direct contact with the area of interest (the leakage sensitive area) and a metal region located over the polysilicon region. The polysilicon contact provides an improved ohmic contact with less leakage into the substrate. The polysilicon contact may be provided with other conventional metal contacts, which are employed in areas of the CMOS imager that do not require low leakage. | 07-23-2009 |
20090186473 | Methods of Forming a Conductive Interconnect in a Pixel of an Imager and in Other Integrated Circuitry - A method of forming conductive interconnects includes forming a node of a circuit component on a substrate. A conductive metal line is formed at a first metal routing level that is elevationally outward of the circuit component. Insulative material is deposited above the first metal routing level over the conductive metal line and the circuit component. In a common masking step, a first opening is etched through the insulative material to the conductive metal line and a second opening is etched through the insulative material to the node of the circuit component that is received elevationally inward of the conductive metal line. Conductive material is concurrently deposited to within the first and second openings in respective conductive connection with the conductive metal line and the node of the circuit component. A first metal line at a second metal routing level that is above the first metal routing level is formed in conductive connection with the conductive material in the first opening. A second metal line at the second metal routing level is formed in conductive connection with the conductive material in the second opening. | 07-23-2009 |
20100079646 | Vertical 4-way shared pixel in a single column with internal reset and no row select - A method and apparatus for reducing space and pixel circuit complexity by using a 4-way shared vertically aligned pixels in a same column. The at least four pixels in the pixel circuit share a reset transistor and a source follower transistor, can have a plurality of same colored pixels and a plurality of colors, but do not include a row select transistor. | 04-01-2010 |
20100172059 | OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS FOR INTEGRATED CIRCUITS - Integrated circuits, memories, protection circuits and methods for protecting against an over-limit electrical condition at a node of an integrated circuit. One such protection circuit includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit electrically coupled to a reference voltage and further electrically coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition for the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit. | 07-08-2010 |
20130050886 | OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS AND METHODS - Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected. | 02-28-2013 |
20130050887 | COMBINATION ESD PROTECTION CIRCUITS AND METHODS - Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. In an example method, a thyristor is triggered to conduct current from a signal node to a reference voltage node using leakage currents provided by a transistor formed in a semiconductor doped well shared with the base of the thyristor. The leakage currents are responsive to a noise event (e.g., electrostatic discharge (ESD) event) at the signal node, and increase the voltage of the semiconductor doped well to forward bias the base and the collector of the thyristor. The triggered thyristor conducts the current resulting from the ESD event to the reference voltage node. | 02-28-2013 |
20140218830 | OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS FOR INTEGRATED CIRCUITS - Protection circuits and methods for protecting an integrated circuit against an over-limit electrical condition are provided. One example includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit coupled to a reference voltage and further coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition tot the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit. | 08-07-2014 |
20140240883 | OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS AND METHODS - Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected. | 08-28-2014 |