Patent application number | Description | Published |
20080217665 | SEMICONDUCTOR DEVICE STRUCTURE HAVING ENHANCED PERFORMANCE FET DEVICE - A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate: a first layer below and second layers on a gate with spacers, source and drain regions adjacent to the gate, silicides on the gate and source and drain regions; disposing a stress layer over the structure resulting from the forming step; disposing an insulating layer over the stress layer; removing portions of the insulating layer to expose a top surface of the stress layer; removing the top surface and other portions of the stress layer and portions of the spacers to form a trench, and then disposing a suitable stress material into the trench. | 09-11-2008 |
20080217696 | METHOD AND STRUCTURE FOR CONTROLLING STRESS IN A TRANSISTOR CHANNEL - A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves forming a shallow-trench-isolation oxide (STI) isolating the n-type device from the p-type device. The method further involves adjusting the shallow-trench-isolation oxide corresponding to at least one of the n-type device and the p-type device such that a thickness of the shallow-trench-isolation oxide adjacent to the n-type device is different from a thickness of the shallow-trench-isolation oxide adjacent to the p-type device, and forming a strain layer over the semiconductor substrate. | 09-11-2008 |
20080224213 | PROCESS FOR MAKING FINFET DEVICE WITH BODY CONTACT AND BURIED OXIDE JUNCTION ISOLATION - There is a FinFET device. The device has a silicon substrate, an oxide layer, and a polysilicone gate. The silicon substrate defines a planar body, a medial body, and a fin. The planar body, the medial body, and the fin are integrally connected. The medial body connects the planar body and the fine. The planar body extends generally around the medial body. The fin is situated to extend substantially from a first side of the substrate to an opposing second side of the substrate. The fin is substantially perpendicularly disposed with respect to the planar body. The first oxide layer is situated on the planar body between the planar body and the fine. The oxide layer extends substantially around the medial body. The polysilicone gate is situated on the oxide layer to extend substantially from a third side to an opposing fourth side of the substrate. The gate is situated to extend across the fin proximal to a medial portion of an upper surface of the fine. There is also a process for making a FinFET device. | 09-18-2008 |
20080230848 | STRUCTURE HAVING DUAL SILICIDE REGION AND RELATED METHOD - A structure including a dual silicide region and a related method are disclosed. The structure may include a doped silicon, and a dual silicide region in the doped silicon, the dual silicide region including a first silicide region including a mid band gap metal, and a second silicide region including a near band gap metal, wherein the second silicide region is immediately adjacent to the doped silicon. The method may include forming a first silicide portion in a doped silicon by depositing a first metal over the doped silicon, annealing and removing unreacted first metal; ion implanting a second metal into the doped silicon; and annealing to form a second silicide portion from the second metal, wherein the first metal is different than the second metal. | 09-25-2008 |
20080230906 | CONTACT STRUCTURE HAVING DIELECTRIC SPACER AND METHOD - A contact structure and method of forming same are disclosed. The contact structure may include a metal body surrounded by a dielectric spacer, the metal body and the dielectric spacer positioned within an interlevel dielectric layer, wherein the metal body is electrically coupled to a silicide region below a lowermost portion of the metal body. | 09-25-2008 |
20080237708 | SILICON ON INSULATOR (SOI) FIELD EFFECT TRANSISTORS (FETs) WITH ADJACENT BODY CONTACTS - A field effect transistor (FET) with an adjacent body contact, a SOI IC with circuits including the FETs and a method of fabricating the ICs. Device islands are formed in the silicon surface layer of a SOI wafer. Gates are defined on the wafer. Body contacts are formed in a perimeter conductive region adjacent to the gates. The body contacts may be either a silicide strap along the gate sidewall at one side of the FET or a separate contact separated from the gate by a dielectric stripe at one side of the FET. Separate contacts may be connected to a bias supply. | 10-02-2008 |
20080237737 | OVERLAPPED STRESSED LINERS FOR IMPROVED CONTACTS - A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device. | 10-02-2008 |
20080237749 | CMOS GATE CONDUCTOR HAVING CROSS-DIFFUSION BARRIER - A gate conductor is provided for a transistor pair including an n-type field effect transistor (“NFET”) having an NFET active semiconductor region and a p-type field effect transistor (“PFET”) having a PFET active semiconductor region, where the NFET and PFET active semiconductor regions are separated by an isolation region. An NFET gate extends in a first direction over the NFET active semiconductor region. A PFET gate extends in the first direction over the PFET active semiconductor region. A diffusion barrier is sandwiched between the NFET gate and the PFET gate. A continuous layer extends continuously in the first direction over the NFET gate and the PFET gate. The continuous layer contacts top surfaces of the NFET gate and the PFET gate and the continuous layer includes at least one of a semiconductor, a metal or a conductive compound including a metal. | 10-02-2008 |
20080237786 | NON-PLANAR FUSE STRUCTURE INCLUDING ANGULAR BEND AND METHOD FOR FABRICATION THEREOF - A fuse structure includes a non-planar fuse material layer typically located over and replicating a topographic feature within a substrate. The non-planar fuse material layer includes an angular bend that assists in providing a lower severance current within the non-planar fuse material layer. | 10-02-2008 |
20080237867 | LOW CONTACT RESISTANCE METAL CONTACT - A semiconductor structure and methods of making the same. The semiconductor structure includes a substrate having a suicide region disposed above a doped region, and a metal contact extending through the silicide region and being in direct contact with the doped region. | 10-02-2008 |
20080239792 | METAL SILICIDE ALLOY LOCAL INTERCONNECT - A local interconnect is formed with a gate conductor line that has an exposed sidewall on an active area of a semiconductor substrate. The exposes sidewall comprises a silicon containing material that may form a silicide alloy upon silicidation. During a silicidation process, a gate conductor sidewall silicide alloy forms on the exposed sidewall of the gate conductor line and an active area silicide is formed on the active area. The two silicides are joined to provide an electrical connection between the active area and the gate conductor line. Multiple sidewalls may be exposed on the gate conductor line to make multiple connections to different active area silicides. | 10-02-2008 |
20080246093 | STRUCTURE AND METHOD OF MAKING A SEMICONDUCTOR INTEGRATED CIRCUIT TOLERANT OF MIS-ALIGNMENT OF A METAL CONTACT PATTERN - Disclosed is a method of fabricating a field effect transistor. In the method, a gate stack on a top surface of a semiconductor substrate is formed, and then a first spacer is formed on a sidewall of the gate stack. Next, a silicide self-aligned to the first spacer is deposited in/or on the semiconductor substrate. Subsequently a second spacer covering the surface of the first spacer, and a contact liner over at least the gate stack, the second spacer and the silicide, are formed. Then an interlayer dielectric over the contact liner is deposited. Next, a metal contact opening is formed to expose the contact liner over the silicide. Finally, the opening is extended through the contact liner to expose the silicide without exposing the substrate. | 10-09-2008 |
20080251853 | STRUCTURE AND METHOD TO OPTIMIZE STRAIN IN CMOSFETs - A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N or P) of MOSFET. A strain inducing CA nitride coating having an original full thickness is formed over both the PMOSFETs and the NMOSFETs, wherein the strain inducing coating produces an optimized full strain in one kind of semiconductor device and degrades the performance of the other kind of semiconductor device. The strain inducing CA nitride coating is etched to a reduced thickness over the other kind of semiconductor devices, wherein the reduced thickness of the strain inducing coating relaxes and produces less strain in the other MOSFETs. | 10-16-2008 |
20080268634 | DOPANT DIFFUSION BARRIER LAYER TO PREVENT OUT DIFFUSION - A dopant diffusion barrier layer between silicon and buried oxide is disclosed. In one embodiment, the structure comprises a silicon layer and a substrate separated by an oxide layer; and a diffusion barrier layer located between the oxide layer and the silicon layer. The structure may include an oxide liner between the diffusion barrier layer and the silicon layer. | 10-30-2008 |
20080283824 | METHOD AND STRUCTURE FOR FORMING STRAINED SI FOR CMOS DEVICES - A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device. | 11-20-2008 |
20080283930 | EXTENDED DEPTH INTER-WELL ISOLATION STRUCTURE - By depositing and forming a spacer out of a semiconductor material layer or a dielectric material layer on the edges of an inter-well isolation area while forming a plug over an intra-well isolation area, a narrow intra-well isolation trench having a normal depth is formed in the intra-well isolation area, while a wider inter-well isolation trench having an extended portion is formed in the inter-well isolation area. The extended portion of the inter-well isolation trench provides enhanced inter-well isolation due to the presence of the extended portion beneath the normal depth. The extended portion of the inter-well isolation trench enables reduction of the width of the intra-well isolation trench structure relative to prior art inter-well isolation structures having a normal depth. | 11-20-2008 |
20080283962 | SELF-ALIGNED AND EXTENDED INTER-WELL ISOLATION STRUCTURE - A pedestal is formed out of the pad layer such that two edges of the pedestal coincide with a border of the wells as implanted. An extended pedestal is formed over the pedestal by depositing a conformal dielectric layer. The area of the extended pedestal is exposed the semiconductor surface below is recessed to a recess depth. Other trenches including at least one intra-well isolation trench are lithographically patterned. After a reactive ion etch, both an inter-well isolation trench and at least one intra-well isolation trench are formed. The width of the inter-well isolation trench may be reduced due to the deeper bottom surface compared to the prior art structures. The boundary between the p-well and the n-well below the inter-well isolation structure is self-aligned to the middle of the inter-well isolation structure. | 11-20-2008 |
20080290413 | SOI MOSFET WITH A METAL SEMICONDUCTOR ALLOY GATE-TO-BODY BRIDGE - A body contact region is formed in a portion of the active region. A gate dielectric and a gate conductor layer are formed on the active region and patterned to define a gate electrode. A portion of the gate electrode is removed to expose a top surface of the body contact region adjoining a sidewall of the gate dielectric which adjoins a sidewall of the gate conductor. A substrate metal semiconductor alloy is formed on the top surface of the body contact region, and a gate metal semiconductor alloy is formed on the sidewall of the gate conductor. The substrate metal semiconductor alloy and the gate metal semiconductor alloy are adjoined during formation, providing a gate-to-body bridge of a MOSFET formed on the active region. | 11-27-2008 |
20080308900 | ELECTRICAL FUSE WITH SUBLITHOGRAPHIC DIMENSION - A photolithography mask contains at least one sublithographic assist feature (SLAF) such that the image of the fuselink shape on a photoresist contains a constructive interference portion and two neck portions. The width of the constructive interference portion is substantially the same as a critical dimension of the lithography tool and the widths of the two neck portions are sublithographic dimensions. The image on a photoresist is subsequently transferred into an underlying semiconductor layer to form an electrical fuse. The fuselink contains a constructive interference portion having a first width which is substantially the same as the critical dimension of the lithography tool and two neck portions having sublithographic widths. The inventive electrical fuse may be programmed with less voltage bias, current, and energy compared to prior art electrical fuses. | 12-18-2008 |
20080311714 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - A complimentary metal oxide semiconductor and a method of manufacturing the same using a self-aligning process to form one of the stacks of device. The method includes depositing an oxide layer over a portion of a metal layer over an nFET region of a CMOS structure and etching the metal layer over a pFET region of the CMOS structure. The method further includes etching at the oxide layer over the nFET region and forming gate structures over the nFET region and pFET region. | 12-18-2008 |
20090001045 | METHODS OF PATTERNING SELF-ASSEMBLY NANO-STRUCTURE AND FORMING POROUS DIELECTRIC - Methods of patterning a self-assembly nano-structure and forming a porous dielectric are disclosed. In one aspect, the method includes providing a hardmask over an underlying layer; predefining an area with a photoresist on the hardmask that is to be protected during the patterning; forming a layer of the copolymer over the hardmask and the photoresist; forming the self-assembly nano-structure from the copolymer; and etching to pattern the self-assembly nano-structure. | 01-01-2009 |
20090001466 | METHOD OF FORMING AN SOI SUBSTRATE CONTACT - A method is provided of forming a conductive via for contacting a bulk semiconductor region of a semiconductor-on-insulator (“SOI”) substrate. A first opening is formed in a conformal layer overlying a trench isolation region, where the trench isolation region shares an edge with the SOI layer. A dielectric layer then is deposited atop the conformal layer and the trench isolation region, after which a second opening is formed which is aligned with the first opening, the second opening extending through the dielectric layer to expose the bulk semiconductor region. Finally, the conductive via is formed in the second opening. | 01-01-2009 |
20090001506 | DUAL STRESS LINER EFUSE - A semiconductor fuse structure comprises an anode connected to a first end of a fuse link, a cathode connected to a second end of the fuse link opposite the first end of the fuse link, a compressive (nitride) liner covering the anode, and a tensile (nitride) liner covering the cathode. The compressive liner and the tensile liner are positioned to cause a net stress gradient between the cathode and the anode, wherein the net stress gradient promotes electromigration from the cathode and the fuse link to the anode. | 01-01-2009 |
20090014798 | FINFET SRAM WITH ASYMMETRIC GATE AND METHOD OF MANUFACTURE THEREOF - A FinFET SRAM transistor device includes transistors formed on fins with each transistor including a semiconductor channel region within a fin plus a source region and a drain region extending within the fin from opposite sides of the channel region with fin sidewalls having a gate dielectric formed thereon. Bilateral transistor gates extend from the gate dielectric. An asymmetrically doped FinFET transistor has source/drain regions doped with a first dopant type, but the asymmetrically doped FinFET transistor include at least one of the bilateral transistor gate electrode regions on one side of at least one of the fins counterdoped with respect to the first dopant type. The finFET transistors are connected in a six transistor SRAM circuit including two PFET pull-up transistors, two NFET pull down transistors and two NFET passgate transistors. | 01-15-2009 |
20090021338 | ELECTRICAL FUSE HAVING A CAVITY THEREUPON - An electrical fuse is formed on a semiconductor substrate and a first dielectric layer is formed over the electrical fuse. At least one opening is formed by lithographic methods and a reactive ion etch in the first dielectric layer down to a top surface of the electrical fuse or down to shallow trench isolation. A second dielectric layer is deposited by a non-conformal deposition. Thickness of the second dielectric layer on the sidewalls of the at least one opening increases with height so that at least one cavity encapsulated by the second dielectric layer is formed in the at least one opening. The at least one cavity provides enhanced thermal isolation of the electrical fuse since the cavity provides superior thermal isolation than a dielectric material. | 01-22-2009 |
20090026523 | PARTIALLY GATED FINFET - A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the first sidewall is not controlled by the gate electrode. A partially gated finFET, that is, a finFET with a gate electrode on the first sidewall and without a gate electrode on the second sidewall is thus formed. Conventional dual gate finFETs may be formed with the inventive partially gated finFETs on the same substrate to provide multiple finFETs having different on-current in the same circuit such as an SRAM circuit. | 01-29-2009 |
20090026543 | FINFET WITH SUBLITHOGRAPHIC FIN WIDTH - At least one recessed region having two parallel edges is formed in an insulator layer over a semiconductor layer such that the lengthwise direction of the recessed region coincides with optimal carrier mobility surfaces of the semiconductor material in the semiconductor layer for finFETs to be formed. Self-assembling block copolymers are applied within the at least one recessed region and annealed to form a set of parallel polymer block lines having a sublithographic width and containing a first polymeric block component. The pattern of sublithographic width lines is transferred into the semiconductor layer employing the set of parallel polymer block lines as an etch mask. Sublithographic width semiconductor fins thus formed may have sidewalls for optimal carrier mobility for p-type finFETs and n-type finFETs. | 01-29-2009 |
20090026574 | ELECTRICAL FUSE HAVING SUBLITHOGRAPHIC CAVITIES THEREUPON - An electrical fuse and a first dielectric layer thereupon are formed on a semiconductor substrate. Self-assembling block copolymers containing two or more different polymeric block components are applied into a recessed region surrounded by a dielectric template layer. The self-assembling block copolymers are then annealed to form a pattern of multiple circles having a sublithographic diameter. The pattern of multiple circles is transferred into the first dielectric layer by a reactive ion etch, wherein the portion of the first dielectric layer above the fuselink has a honeycomb pattern comprising multiple circular cylindrical holes. A second dielectric layer is formed over the circular cylindrical holes by a non-conformal chemical vapor deposition and sublithographic cavities are formed on the fuselink. The sublithographic cavities provide enhanced thermal insulation relative to dielectric materials to the fuselink so that the electrical fuse may be programmed with less programming current. | 01-29-2009 |
20090029531 | HYBRID ORIENTATION SUBSTRATE AND METHOD FOR FABRICATION THEREOF - A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the exposed portion of the base semiconductor substrate. The resulting surface semiconductor layer and epitaxial surface semiconductor layer adjoin with an interface that is not perpendicular to the base semiconductor substrate. The method also includes implanting through the surface semiconductor layer and the epitaxial surface semiconductor layer a dielectric forming ion to provide a buried dielectric layer that separates the surface semiconductor layer and the epitaxial surface semiconductor layer from the base semiconductor substrate. | 01-29-2009 |
20090032886 | SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS - A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) first and second semiconductor body regions. The method further includes forming (i) a gate divider region and (ii) a gate electrode layer on top of the semiconductor substrate. The gate divider region is in direct physical contact with gate electrode layer. A top surface of the gate electrode layer and a top surface of the gate divider region are essentially coplanar. The method further includes patterning the gate electrode layer resulting in a first gate electrode region and a second gate electrode region. The gate divider region does not overlap the first and second gate electrode regions in the reference direction. | 02-05-2009 |
20090032959 | ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS - Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a first set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors. | 02-05-2009 |
20090039512 | ELECTROMIGRATION RESISTANT INTERCONNECT STRUCTURE - A line trench is formed in a dielectric layer that may contain an interlayer dielectric material. A metal liner is formed on the sidewalls and the bottom surface of the line trench. A conductive metal is deposited within a remaining portion of the line trench at least up to a top surface of the dielectric layer and planarized to form a metal line in the line trench. The metal line is recessed by a recess etch below the top surface of the dielectric layer. A dielectric line cap or a metallic line cap is formed by deposition of a dielectric cap layer or a metallic cap layer, followed by planarization of the dielectric or metallic cap layer. The dielectric line cap or the metallic line cap applies a highly compressive stress on the underlying metal line, which increases electromigration resistance of the metal line. | 02-12-2009 |
20090057818 | METHODS AND SYSTEMS INVOLVING ELECTRICALLY PROGRAMMABLE FUSES - An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse. | 03-05-2009 |
20090098689 | ELECTRICAL FUSE AND METHOD OF MAKING - A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing compressive stress liner material over the fuse material, and patterning the compressive stress liner material. | 04-16-2009 |
20090108351 | FINFET MEMORY DEVICE WITH DUAL SEPARATE GATES AND METHOD OF OPERATION - A FinFET device comprises a front gate (FG) and a separate back gate (BG) disposed on opposite sides of the fine. The fin structure may act as a floating body of a volatile memory cell. The front and back gates may be doped with the same or opposite polarity, and may be biased oppositely. A plurality of FinFETs may be connected in a memory array with single column erase, or double column erase capability. | 04-30-2009 |
20090108356 | INTEGRATION SCHEME FOR MULTIPLE METAL GATE WORK FUNCTION STRUCTURES - A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer. | 04-30-2009 |
20090108364 | DUAL WORKFUNCTION SILICIDE DIODE - A CMOS diode and method of making it are disclosed. In one embodiment, the diode comprises a silicon substrate having an N doped region and a P doped region. A first silicide region is formed on the N doped region of the silicon substrate, and a second silicide region formed on the P doped region of the silicon substrate. The first silicide region is comprised of a material having a bandgap value lower than the bandgap value of the material comprising the second silicide region. The result is a diode where the workfunction of each region of silicide more closely matches the workfunction of the doped silicon it contacts, resulting in reduced contact resistance. This provides for a diode with improved performance characteristics. | 04-30-2009 |
20090115020 | ELECTRICAL FUSE AND METHOD OF MAKING - A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing compressive stress liner material over the fuse material, and patterning the compressive stress liner material. | 05-07-2009 |
20090134470 | HIGH PERFORMANCE MOSFET COMPRISING A STRESSED GATE METAL SILICIDE LAYER AND METHOD OF FABRICATING THE SAME - The present invention relates to a semiconductor device that comprises at least one field effect transistor (FET) containing a source region, a drain region, a channel region, a gate dielectric layer, a gate electrode, and one or more gate sidewall spacers. The gate electrode of such an FET contains an intrinsically stressed gate metal silicide layer, which is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating stress in the channel region of the FET. Preferably, the semiconductor device comprises at least one p-channel FET, and more preferably, the p-channel FET has a gate electrode with an intrinsically stressed gate metal silicide layer that is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating compressive stress in the p-channel of the FET. | 05-28-2009 |
20090148677 | HIGH ASPECT RATIO ELECTROPLATED METAL FEATURE AND METHOD - Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up. | 06-11-2009 |
20090152638 | DUAL OXIDE STRESS LINER - A transistor structure includes a first type of transistor (e.g., P-type) positioned in a first area of the substrate, and a second type of transistor (e.g., N-type) positioned in a second area of the substrate. A first type of stressing layer (compressive conformal nitride) is positioned above the first type of transistor and a second type of stressing layer (compressive tensile nitride) is positioned above the second type of transistor. In addition, another first type of stressing layer (compressive oxide) is positioned above the first type of transistor. Further, another second type of stressing layer (compressive oxide) is positioned above the second type of transistor. | 06-18-2009 |
20090174010 | SRAM DEVICE STRUCTURE INCLUDING SAME BAND GAP TRANSISTORS HAVING GATE STACKS WITH HIGH-K DIELECTRICS AND SAME WORK FUNCTION - An SRAM semiconductor device includes: at least a first and a second field effect transistor formed on a same substrate, each of the transistors including a gate stack, each gate stack including a semiconductor layer disposed on a metal layer, the metal layer being disposed on a high-k dielectric layer located over a chemical region, wherein the metal layer of the first gate stack and the metal layer of the second gate stack have approximately a same work function, and wherein each channel region has approximately a same band gap. | 07-09-2009 |
20090201743 | MULTIWALLED CARBON NANOTUBE MEMORY DEVICE - A carbon nanotube based memory device comprises a set of three concentric carbon nanotubes having different diameters. The diameters of the three concentric carbon nanotubes are selected such that an inner carbon nanotube is semiconducting, and intershell electron transport occurs between adjacent carbon nanotubes. Source and drain contacts are made to the inner carbon nanotube, and a gate contact is made to the outer carbon nanotube. The carbon nanotube based memory device is programmed by storing electrons or holes in the middle carbon nanotube through intershell electron transport. Changes in conductance of the inner carbon nanotube due to the charge in the middle shell are detected to determine the charge state of the middle carbon nanotube. Thus, the carbon nanotube based memory device stores information in the middle carbon nanotube in the form of electrical charge. | 08-13-2009 |
20090206442 | METHOD AND STRUCTURE FOR RELIEVING TRANSISTOR PERFORMANCE DEGRADATION DUE TO SHALLOW TRENCH ISOLATION INDUCED STRESS - A method of forming shallow trench isolation (STI) regions for semiconductor devices, the method including defining STI trench openings within a semiconductor substrate; filling the STI trench openings with an initial trench fill material; defining a pattern of nano-scale openings over the substrate, at locations corresponding to the STI trench openings; transferring the pattern of nano-scale openings into the trench fill material so as to define a plurality of vertically oriented nano-scale openings in the trench fill material; and plugging upper portions of the nano-scale openings with additional trench fill material, thereby defining porous STI regions in the substrate. | 08-20-2009 |
20090206489 | DUAL DAMASCENE METAL INTERCONNECT STRUCTURE HAVING A SELF-ALIGNED VIA - A recessed region containing a line portion and a bulge portion is formed in a hard mask layer. Self-assembling block copolymers containing two or more different polymeric block components that are immiscible with one another are applied within the recessed region and annealed. A cylindrical polymeric block centered at the bulge portion is removed selective to a polymeric block matrix surrounding the cylindrical polymeric block. A via cavity is formed by transferring the cavity formed by removal of the cylindrical polymeric block into a dielectric layer. The pattern in the hard mask layer is subsequently transferred into the dielectric layer to form a line cavity. A metal via and a metal line are formed by deposition and planarization of metal. The metal via is self-aligned to the metal line. | 08-20-2009 |
20090218695 | LOW CONTACT RESISTANCE METAL CONTACT - A semiconductor structure and methods of making the same. The semiconductor structure includes a substrate having a silicide region disposed above a doped region, and a metal contact extending through the silicide region and being in direct contact with the doped region. | 09-03-2009 |
20090230427 | SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING - Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers. The structure further includes an epitaxially grown straining material directly on the polysilicon layer and between portions of the sidewalls. The epitaxially grown straining material, in a relaxed state, strains the polysilicon layer. | 09-17-2009 |
20090256173 | COMPLEMENTARY FIELD EFFECT TRANSISTORS HAVING EMBEDDED SILICON SOURCE AND DRAIN REGIONS - A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of a substrate. The first semiconductor region can be grown laterally adjacent to a second semiconductor region which has a lattice constant smaller than that of silicon. Layers consisting essentially of silicon can be grown epitaxially onto exposed major surfaces of the first and second semiconductor regions after which gates can be formed which overlie the epitaxially grown silicon layers. Portions of the first and second semiconductor regions adjacent to the gates can be removed to form recesses. Regions consisting essentially of silicon can be grown within the recesses to form embedded silicon regions. Source and drain regions then can be formed in the embedded silicon regions. The difference between the lattice constant of silicon and that of the underlying first and second regions results in tensile stressed silicon over the first semiconductor region and compressive stressed silicon over the second semiconductor region. | 10-15-2009 |
20090256211 | METAL GATE COMPATIBLE FLASH MEMORY GATE STACK - A first gate stack comprising two stacked gate electrodes in a first device region, a second gate stack comprising a metal gate electrode in a second device region, and a third gate stack comprising a semiconductor gate electrode in a third device region are formed by forming and removing portions of a silicon-oxide based gate dielectric layer, a first doped semiconductor layer, an interfacial dielectric layer, a high-k gate dielectric layer, a metal gate layer, and an optional semiconductor material layer in various device regions. The first gate stack may be employed to form a flash memory, and the second and third gate stacks may be employed to form a pair of p-type and n-type field effect transistors. | 10-15-2009 |
20090267196 | HIGH PERFORMANCE 3D FET STRUCTURES, AND METHODS FOR FORMING THE SAME USING PREFERENTIAL CRYSTALLOGRAPHIC ETCHING - The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes. | 10-29-2009 |
20090283829 | FINFET WITH A V-SHAPED CHANNEL - A fin-type field effect transistor (finFET) structure comprises a substrate having a planar upper surface, an elongated fin on the planar upper surface of the substrate (wherein the length and the height of the fin are greater that the width of the fin) and an elongated gate conductor on the planar upper surface of the substrate. The length and the height of the gate conductor are greater than the width of the gate conductor. The fin comprises a center section comprising a semiconducting channel region and end sections distal to the channel region. The end sections of the fin comprise conductive source and drain regions. The gate conductor covers the channel region of the fin. The sidewalls of the channel region comprise a different crystal orientation than the sidewalls of the source and drain regions. | 11-19-2009 |
20090302412 | CARRIER MOBILITY ENHANCED CHANNEL DEVICES AND METHOD OF MANUFACTURE - An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material. | 12-10-2009 |
20090302417 | STRUCTURE AND METHOD TO FORM DUAL SILICIDE E-FUSE - An e-fuse structure and method has anode, a fuse link, and a cathode. The first end of the fuse link is connected to the anode and the second end of the fuse link opposite the first end is connected to the cathode. This structure also includes a first silicide layer on the anode and the fuse link and a second silicide layer, different than the first silicide layer, on the cathode. The difference between the first silicide layer and the second silicide layer causes an enhanced flux divergence region at the second end of the fuse link. | 12-10-2009 |
20090309164 | STRUCTURE AND METHOD TO INTEGRATE DUAL SILICIDE WITH DUAL STRESS LINER TO IMPROVE CMOS PERFORMANCE - The present invention provides a semiconducting device including a substrate including a semiconducting surface having an n-type device in a first device region and a p-type device in a second device region, the n-type device including a first gate structure present overlying a portion of the semiconducting surface in the first device region including a first work function metal semiconductor alloy in the semiconducting surface adjacent to the portion of the semiconducting surface underlying the gate structure, and a first type strain inducing layer present overlying the first device region; and a p-type device including a second gate structure present overlying a portion of the semiconducting surface in the second device region including a second work function metal semiconductor alloy in the semiconducting surface adjacent to the portion of the semiconducting surface underlying the gate structure, and a second type strain inducing layer present overlying the second device region. | 12-17-2009 |
20090309184 | STRUCTURE AND METHOD TO FORM E-FUSE WITH ENHANCED CURRENT CROWDING - An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region. | 12-17-2009 |
20090315117 | CMOS DEVICES HAVING REDUCED THRESHOLD VOLTAGE VARIATIONS AND METHODS OF MANUFACTURE THEREOF - Stress enhanced transistor devices and methods of fabricating the same are provided. In one embodiment, a transistor device comprises: a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and epitaxial source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region. | 12-24-2009 |
20100005649 | ELECTRICAL FUSE HAVING SUBLITHOGRAPHIC CAVITIES THEREUPON - An electrical fuse and a first dielectric layer thereupon are formed on a semiconductor substrate. Self-assembling block copolymers containing two or more different polymeric block components are applied into a recessed region surrounded by a dielectric template layer. The self-assembling block copolymers are then annealed to form a pattern of multiple circles having a sublithographic diameter. The pattern of multiple circles is transferred into the first dielectric layer by a reactive ion etch, wherein the portion of the first dielectric layer above the fuselink has a honeycomb pattern comprising multiple circular cylindrical holes. A second dielectric layer is formed over the circular cylindrical holes by a non-conformal chemical vapor deposition and sublithographic cavities are formed on the fuselink. The sublithographic cavities provide enhanced thermal insulation relative to dielectric materials to the fuselink so that the electrical fuse may be programmed with less programming current. | 01-14-2010 |
20100019322 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A semiconductor device and method is provided that has a stress component for increased device performance. The method integrates a stress material into a trench used typically for an isolation structure. The method includes forming an isolation trench through a SOI layer and an underlying BOX layer. The method further includes filling the isolation trench with stress material having characteristics different than the BOX layer. | 01-28-2010 |
20100038705 | FIELD EFFECT DEVICE WITH GATE ELECTRODE EDGE ENHANCED GATE DIELECTRIC AND METHOD FOR FABRICATION - A semiconductor structure and a method for fabricating the semiconductor structure provide an undercut beneath a spacer that is adjacent a gate electrode within a field effect structure such as a field effect transistor structure. The undercut, which may completely or incompletely encompass the area interposed between the spacer and a semiconductor substrate is filled with a gate dielectric. The gate dielectric has a greater thickness interposed between the spacer and the semiconductor substrate than the gate and the semiconductor substrate. The semiconductor structure may be fabricated using a sequential replacement gate dielectric and gate electrode method. | 02-18-2010 |
20100096673 | SEMICONDUCTOR DEVICE STRUCTURE HAVING ENHANCED PERFORMANCE FET DEVICE - A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate: a first layer below and second layers on a gate with spacers, source and drain regions adjacent to the gate, silicides on the gate and source and drain regions; disposing a stress layer over the structure resulting from the forming step; disposing an insulating layer over the stress layer; removing portions of the insulating layer to expose a top surface of the stress layer; removing the top surface and other portions of the stress layer and portions of the spacers to form a trench, and then disposing a suitable stress material into the trench. | 04-22-2010 |
20100143649 | HIGH ASPECT RATIO ELECTROPLATED METAL FEATURE AND METHOD - Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up. | 06-10-2010 |
20100148259 | SOI SUBSTRATES AND SOI DEVICES, AND METHODS FOR FORMING THE SAME - An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate. | 06-17-2010 |
20100176450 | STRUCTURE AND METHOD OF FORMING A TRANSISTOR WITH ASYMMETRIC CHANNEL AND SOURCE/DRAIN REGIONS - A semiconductor structure is described. The structure includes a semiconductor substrate having a conductive gate abutting a gate insulator for controlling conduction of a channel region; and a source region and a drain region associated with the conductive gate, where the source region includes a first material and the drain region includes a second material, and where the conductive gate is self-aligned to the first material and the second material. In one embodiment, the first material includes Si and the second material includes SiGe. A method of forming a semiconductor structure is also described. The method includes forming a pad layer on a top surface of a SOI layer of a semiconductor substrate; patterning the pad layer and a portion of the SOI layer for forming a SiGe layer; epitaxially growing the SOI layer for forming a Si layer and a SiGe layer adjacent to a sidewall of the SOI layer; selectively pulling a portion of the pad layer; forming a gate dielectric of a portion of the SiGe layer and the SOI layer; forming a gate conductor over the gate dielectric; removing the remaining of the pad layer; forming a source region in at least one of the SOI layer and the SiGe layer; and forming a drain region in at least one of the SOI layer and the SiGe layer. | 07-15-2010 |
20100178615 | METHOD FOR REDUCING TIP-TO-TIP SPACING BETWEEN LINES - This invention provides a method for reducing tip-to-tip spacing between lines using a combination of photolithographic and copolymer self-assembling lithographic techniques. A mask layer is first formed over a substrate with a line structure. A trench opening of a width d is created in the mask layer. A layer of a self-assembling block copolymer is then applied over the mask layer. The block copolymer layer is annealed to form a single unit polymer block of a width or a diameter w which is smaller than d inside the trench opening. The single unit polymer block is selectively removed to form a single opening of a width or a diameter w inside the trench opening. An etch transfer process is performed using the single opening as a mask to form an opening in the line structure in the substrate. | 07-15-2010 |
20100187636 | METHOD TO INCREASE STRAIN ENHANCEMENT WITH SPACERLESS FET AND DUAL LINER PROCESS - A semiconductor structure and a method of fabricating the same in which strain enhancement is achieved for both nFET and pFET devices is provided. In particular, the present invention provides at least one spacerless FET for stronger strain enhancement and defect reduction. The at least one spacerless FET can be a pFET, an nFET, or a combination thereof, with spacerless pFETs being particularly preferred since pFETs are generally fabricated to have a greater width than nFETs. The at least one spacerless FET allows to provide a stress inducing liner in closer proximity to the device channel than prior art structures including FETs having spacers. The spacerless FET is achieved without negatively affecting the resistance of the corresponding silicided source/drain diffusion contacts, which do not encroach underneath the spacerless FET. | 07-29-2010 |
20100200934 | FIELD EFFECT DEVICE INCLUDNG RECESSED AND ALIGNED GERMANIUM CONTAINING CHANNEL - A field effect structure and a method for fabricating the field effect structure include a germanium containing channel interposed between a plurality of source and drain regions. The germanium containing channel is coplanar with the plurality of source and drain regions, and the germanium containing channel includes a germanium containing material having a germanium content greater than the germanium content of the plurality of source and drain regions. | 08-12-2010 |
20100237460 | METHODS AND SYSTEMS INVOLVING ELECTRICALLY PROGRAMMABLE FUSES - An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse. | 09-23-2010 |
20100252881 | CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME - The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor. | 10-07-2010 |
20100283121 | ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS - Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors. | 11-11-2010 |
20100295132 | PROGRAMMABLE PN ANTI-FUSE - Structure and method for providing a programmable anti-fuse in a FET structure. A method of forming the programmable anti-fuse includes: providing a p− substrate with an n+ gate stack; implanting an n+ source region and an n+ drain region in the p− substrate; forming a resist mask over the n+ drain region, while leaving the n+ source region exposed; etching the n+ source region to form a recess in the n+ source region; and growing a p+ epitaxial silicon germanium layer in the recess in the n+ source region to form a pn junction that acts as a programmable diode or anti-fuse. | 11-25-2010 |
20110070739 | DOUBLE PATTERNING PROCESS FOR INTEGRATED CIRCUIT DEVICE MANUFACTURING - A method of forming an integrated circuit (IC) device feature includes forming an initially substantially planar hardmask layer over a semiconductor device layer to be patterned; forming a first photoresist layer over the hardmask layer; patterning a first set of semiconductor device features in the first photoresist layer; registering the first set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the first photoresist layer; forming a second photoresist layer over the substantially planar hardmask layer; patterning a second set of semiconductor device features in the second photoresist layer; registering the second set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the second photoresist layer; and creating topography within the hardmask layer by removing portions thereof corresponding to both the first and second sets of semiconductor device features. | 03-24-2011 |
20110180853 | CARRIER MOBILITY ENHANCED CHANNEL DEVICES AND METHOD OF MANUFACTURE - An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material. | 07-28-2011 |
20110260323 | HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT - The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing. | 10-27-2011 |
20110280094 | Boost Cell Supply Write Assist - A method of increasing a drain to source voltage measured at an access pass-gate to a SRAM circuit in a SRAM memory array, including increasing a low voltage from a low voltage source powering said SRAM circuit, and increasing a high voltage from a high voltage source powering the SRAM circuit. | 11-17-2011 |
20120126339 | SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS - A semiconductor structure. The semiconductor structure includes: a semiconductor substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface and further includes a first semiconductor body region and a second semiconductor body region; a first gate dielectric region and a second gate dielectric region on top of the first and second semiconductor body regions, respectively; a first gate electrode region on top of the semiconductor substrate and the first gate dielectric region; a second gate electrode region on top of the semiconductor substrate and the second gate dielectric region; and a gate divider region in direct physical contact with the first and second gate electrode regions. The gate divider region does not overlap the first and second gate electrode regions in the reference direction. | 05-24-2012 |
20120135591 | SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING - Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. A method of forming a semiconductor structure includes forming sidewalls and spacers adjacent to a gate stack structure, and forming a recess in the gate stack structure. The method further includes epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure. The straining material is Si:C and the gate stack structure is a PFET gate stack structure. The straining material is grown above and covering a top surface of the sidewalls and the spacers. | 05-31-2012 |
20120175640 | SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING - Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers. The structure further includes an epitaxially grown straining material directly on the polysilicon layer and between portions of the sidewalls. The epitaxially grown straining material, in a relaxed state, strains the polysilicon layer. | 07-12-2012 |
20120178227 | REPLACEMENT GATE CMOS - A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate located over a second active region of a second polarity different than the first polarity. The first active region and the second active region are separated by an isolation region. The first gate and the second gate are co-linear, with facing endwalls that terminate over the isolation region. The facing endwalls do not have a spacer located or formed adjacent or adjoining thereto, although sidewalls of the first gate and the second gate do. The CMOS structure may be fabricated using a sequential replacement gate method. | 07-12-2012 |
20120193679 | HETEROJUNCTION TUNNELING FIELD EFFECT TRANSISTORS, AND METHODS FOR FABRICATING THE SAME - The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide. | 08-02-2012 |
20120214301 | STRUCTURE AND METHOD TO FORM E-FUSE WITH ENHANCED CURRENT CROWDING - An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region. | 08-23-2012 |
20120235236 | STRUCTURE AND METHOD OF FORMING A TRANSISTOR WITH ASYMMETRIC CHANNEL AND SOURCE/DRAIN REGIONS - A semiconductor structure includes a semiconductor substrate. A conductive gate abuts a gate insulator for controlling conduction of a channel region. The gate insulator abuts the channel region. A source region and a drain region are associated with the conductive gate. The source region includes a first material and the drain region includes a second material. The conductive gate is self-aligned to the first and the second material. | 09-20-2012 |
20130221529 | HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT - A hybrid interconnect structure (of the single or dual damascene type) is provided in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance. Moreover, the hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing. | 08-29-2013 |
20130228925 | HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT - A hybrid interconnect structure is provided that includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance. Moreover, the hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing. | 09-05-2013 |
20130230983 | HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT - A method of forming a hybrid interconnect structure including dielectric spacers is provided. The method includes forming at least one opening in a dielectric material utilizing a patterned hard mask located on a surface of the dielectric material as a mask, wherein an undercut is present beneath said patterned hard mask. Next, a dense dielectric spacer is formed in the at least one opening and at least partially on exposed sidewalls of the dielectric material. A diffusion barrier and a conductive material are then formed within the at least one opening. | 09-05-2013 |
20140151644 | HETEROJUNCTION TUNNELING FIELD EFFECT TRANSISTORS, AND METHODS FOR FABRICATING THE SAME - The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide. | 06-05-2014 |