Patent application number | Description | Published |
20120266914 | CLEANING FEATURE FOR ELECTRIC CHARGING CONNECTOR - A contamination cleaner for a socket of a charging connector used with a charging station for an electric vehicle wherein the charging connector mates to a charging coupler of the electric vehicle during charging includes a housing mechanically configured generally similarly to the charging coupler enabling the housing to mechanically mate to the charging connector; and a cleaning contact, coupled to the housing and complementary to the socket, for engaging the socket and removing surface contaminants from the socket whenever the housing mechanically mates to the charging connector. | 10-25-2012 |
20130057209 | Multiport Vehicle DC Charging System with Variable Power Distribution - A battery charging station is provided that includes a plurality of charge ports, a plurality of power stages where each power stage includes an AC to DC converter and where each power stage provides a portion of the charging station's maximum available charging power, a switching system that is used to couple the output of the power stages to the charging ports, a system monitor that determines current charging station and vehicle conditions, and a controller that controls operation of the switching system in accordance with a predefined set of power distribution rules and on the basis of the current charging station and vehicle conditions. Current charging station and vehicle conditions may include vehicle arrival time, usage fees, vehicle and/or customer priority information, battery pack SOC, and/or intended departure time. | 03-07-2013 |
20130057210 | Method of Operating a Multiport Vehicle Charging System - A method of distributing charging power among a plurality of charge ports of a battery charging station is provided, where the battery charging station includes a plurality of power stages where each power stage includes an AC to DC converter and provides a portion of the charging station's maximum available charging power, the method comprising the steps of (i) monitoring battery charging station conditions and operating conditions for each charging port; (ii) determining current battery charging station conditions, including current operating conditions for each charging port; (iii) determining power distribution for the battery charging station and the charging ports in response to the current battery charging conditions and in accordance with a predefined set of power distribution rules; and (iv) coupling the power stages to the charging ports in accordance with the power distribution. | 03-07-2013 |
20130078839 | Funnel Shaped Charge Inlet - A vehicle charge inlet integrated into a port assembly surface is provided. The charge inlet includes an inlet housing with a perimeter that is curvilinear, non-cylindrical and shaped so that only a single orientation of a complementary sized and shaped electrical connector may be inserted into the inlet. A plurality of electrical contacts, a latching mechanism and a divider are also integrated into the charge inlet housing, the divider extending from the bottom surface of the inlet housing and configured to fit within a complementary slot of the charge connector, the divider providing further electrical isolation between the electrical contacts. A funneling surface connects the open end of the inlet housing to the port assembly surface. | 03-28-2013 |
Patent application number | Description | Published |
20130042093 | CONTEXT STATE MANAGEMENT FOR PROCESSOR FEATURE SETS - Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction. | 02-14-2013 |
20130159726 | METHOD AND APPARATUS TO PROVIDE SECURE APPLICATION EXECUTION - A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed. | 06-20-2013 |
20130198853 | METHOD AND APPARATUS TO PROVIDE SECURE APPLICATION EXECUTION - A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed. | 08-01-2013 |
20130219154 | CONTEXT STATE MANAGEMENT FOR PROCESSOR FEATURE SETS - Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction. | 08-22-2013 |
Patent application number | Description | Published |
20100122262 | Method and Apparatus for Dynamic Allocation of Processing Resources - A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device. | 05-13-2010 |
20100208826 | VARIABLE-LENGTH CODE DECODER - A method that decodes serially received MPEG variable length codes by executing instructions in parallel. The method includes an execution unit, which includes multiple pipelined functional units. The functional units execute at least two of the instructions in parallel. The instructions utilize and share general purpose registers. The general purpose registers store information used by at least two of the instructions. | 08-19-2010 |
20100262746 | METHOD OF INTEGRATING A PERSONAL COMPUTING SYSTEM AND APPARATUS THEREOF - An integrated circuit also referred to as an integrated computing system has a single substrate that has either deposited thereon or etched thereon, a central processing unit, a north bridge, a south bridge, and a graphics controller. An internal bus is coupled between the north bridge and the central processing unit. The central processing unit and north bridge do not require interfaces to perform bus protocol conversions. | 10-14-2010 |
20110283293 | Method and Apparatus for Dynamic Allocation of Processing Resources - A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using available processing resources to produce resulting data, and the resulting data is passed to an input/output device. | 11-17-2011 |
20120070094 | VARIABLE-LENGTH CODE DECODER - An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers. | 03-22-2012 |
Patent application number | Description | Published |
20080216073 | Apparatus for executing programs for a first computer architechture on a computer of a second architechture - Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context. Without modifying a pre-existing operating system of the computer, an entry exception is establishing to be raised on each entry to the operating system at a specified entry point or on a specified condition. The entry exception has an associated entry handler programmed to save a context of an interrupted thread and modify the thread context before delivering the modified context to the operating system. A resumption exception is established to be raised on each resumption from the operating system complementary to one of the specified entries. The resumption exception has an associated exit handler programmed to restore the context saved by a corresponding execution of the entry handler. The entry exception, exit exception, entry handler, and exit handler are cooperatively designed to maintain an association between a one of the threads and an extended context of the thread through a context change induced by the operating system, the extended context including resources of the computer associated with the thread beyond those resources whose association with the thread is maintained by the operating system. | 09-04-2008 |
20090204785 | Computer with two execution modes - A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture. or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page. | 08-13-2009 |
20090300323 | Vector Processor System - A vector processing system provides high performance vector processing using a System-On-a-Chip (SOC) implementation technique. One or more scalar processors (or cores) operate in conjunction with a vector processor, and the processors collectively share access to a plurality of memory interfaces coupled to Dynamic Random Access read/write Memories (DRAMs). In typical embodiments the vector processor operates as a slave to the scalar processors, executing computationally intensive Single Instruction Multiple Data (SIMD) codes in response to commands received from the scalar processors. The vector processor implements a vector processing Instruction Set Architecture (ISA) including machine state, instruction set, exception model, and memory model. | 12-03-2009 |
20120144167 | APPARATUS FOR EXECUTING PROGRAMS FOR A FIRST COMPUTER ARCHITECTURE ON A COMPUTER OF A SECOND ARCHITECTURE - A multi-instruction set architecture (ISA) computer system includes a computer program, a first processor, a second processor, a profiler, and a translator. The computer program includes instructions of a first ISA, the first ISA having a first complexity. The first processor is configured to execute instructions of the first ISA. The second processor is configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity. The profiler is configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA. The translator is configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor. | 06-07-2012 |
20130185496 | Vector Processing System - A vector processing system provides high performance vector processing using a System-On-a-Chip (SOC) implementation technique. One or more scalar processors (or cores) operate in conjunction with a vector processor, and the processors collectively share access to a plurality of memory interfaces coupled to Dynamic Random Access read/write Memories (DRAMs). In typical embodiments the vector processor operates as a slave to the scalar processors, executing computationally intensive Single Instruction Multiple Data (SIMD) codes in response to commands received from the scalar processors. The vector processor implements a vector processing Instruction Set Architecture (ISA) including machine state, instruction set, exception model, and memory model. | 07-18-2013 |