Patent application number | Description | Published |
20080215929 | SWITCHING A DEFECTIVE SIGNAL LINE WITH A SPARE SIGNAL LINE WITHOUT SHUTTING DOWN THE COMPUTER SYSTEM - A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers. | 09-04-2008 |
20120256653 | PROGRAMMABLE LOGIC CIRCUIT USING THREE-DIMENSIONAL STACKING TECHNIQUES - A configurable die stack arrangement including a first configurable integrated circuit die located on a first substrate. The first configurable integrated circuit die includes a first array and a first configuration memory management circuit that includes an interface to the first array. The first array includes a first logic element and a first configuration memory. The configurable die stack arrangement also includes a second configurable integrated circuit die located on a second substrate that is different than the first substrate. The second configurable integrated circuit die includes a second array and a second configuration memory management circuit that includes an interface to the second array. The second array includes a second logic element and a second configuration memory. A signal is coupled to the first configuration management circuit and to the second configuration management circuit, and the first configuration memory management circuit includes circuitry to control the signal. | 10-11-2012 |
20130038380 | IIMPLEMENTING CHIP TO CHIP CALIBRATION WITHIN A TSV STACK - A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack. | 02-14-2013 |
20130138901 | IIMPLEMENTING MEMORY PERFORMANCE MANAGEMENT AND ENHANCED MEMORY RELIABILITY ACCOUNTING FOR THERMAL CONDITIONS - A method, system and computer program product implement memory performance management and enhanced memory reliability of a computer system accounting for system thermal conditions. When a primary memory temperature reaches an initial temperature threshold, reads are suspended to the primary memory and reads are provided to a mirrored memory in a mirrored memory pair, and writes are provided to both the primary memory and the mirrored memory. If the primary memory temperature reaches a second temperature threshold, write operations to the primary memory are also stopped and the primary memory is turned off with DRAM power saving modes such as self timed refresh (STR), and the reads and writes are limited to the mirrored memory in the mirrored memory pair. When the primary memory temperature decreases to below the initial temperature threshold, coherency is recovered by writing a coherent copy from the mirrored memory to the primary memory. | 05-30-2013 |
20130179724 | IIMPLEMENTING ENHANCED HARDWARE ASSISTED DRAM REPAIR - A method, system and computer program product are provided for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system that supports ECC. A data register providing DRAM repair is selectively provided in one of the Dynamic Random Access Memory (DRAM), a memory controller, or a memory buffer coupled between the DRAM and the memory controller. The data register is configured to map to any address. Responsive to the configured address being detected, the reads to or the writes from the configured address are routed to the data register. | 07-11-2013 |
20130275823 | PROGRAMMABLE LOGIC CIRCUIT USING THREE-DIMENSIONAL STACKING TECHNIQUES - A method of configuring a plurality of configurable integrated circuit dies including receiving a configuration data stream at a die stack. The configuration data stream includes configuration memory data for logic devices located on dies in the die stack. At least two of the dies are located on different substrates. The method also includes, performing for each of the dies in the die stack: receiving the configuration memory data for the die, storing the configuration memory data for the die in a configuration memory on the die, determining whether the configuration data stream includes configuration memory data for an additional die in the die stack, and transmitting the configuration data stream to the additional die in the die stack in response to the configuration data stream including configuration memory data for the additional die in the die stack. | 10-17-2013 |
20130339820 | THREE DIMENSIONAL (3D) MEMORY DEVICE SPARING - According to one embodiment of the present invention, a method for operating a three dimensional (“3D”) memory device includes detecting, by a memory controller, a first error on the 3D memory device and detecting, by the memory controller, a second error in a first chip in a first rank of the 3D memory device, wherein the first chip has an associated first chip select. The method also includes powering up a second chip in a second rank, sending a command from the memory controller to the 3D memory device to replace the first chip in the first chip select with the second chip and correcting the first error using an error control code. | 12-19-2013 |
20130339821 | THREE DIMENSIONAL(3D) MEMORY DEVICE SPARING - According to one embodiment of the present invention, a method for bank sparing in a 3D memory device that includes detecting, by a memory controller, a first error in the 3D memory device and detecting a second error in a first element in a first rank of the 3D memory device, wherein the first element in the first rank has an associated first chip select. The method also includes sending a command to the 3D memory device to set mode registers in a master logic portion of the 3D memory device that enable a second element to receive communications directed to the first element and wherein the second element is in a second rank of the 3D memory device, wherein the first element and second element are each either a bank or a bank group that comprise a plurality of chips. | 12-19-2013 |
20140040576 | REQUESTING A MEMORY SPACE BY A MEMORY CONTROLLER - Systems and methods are provided to process a request for a memory space from a memory controller. A particular method may include communicating, by a memory controller, a request for a memory space of a memory to a computer program. The memory controller is configured to initialize the memory, and the memory controller is configured to perform operations on the memory as instructed. The computer program is configured to make memory spaces of the memory available in response to requests for the memory spaces of the memory. The method may also include using, by the memory controller, the memory space in response to an indication from the computer program that the memory space is available. Also provided are systems and methods for copying a memory space by a memory controller to a memory space under exclusive control of the memory controller. | 02-06-2014 |
20140063987 | MEMORY OPERATION UPON FAILURE OF ONE OF TWO PAIRED MEMORY DEVICES - A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices. | 03-06-2014 |
20140068322 | IIMPLEMENTING DRAM COMMAND TIMING ADJUSTMENTS TO ALLEVIATE DRAM FAILURES - A method, system and computer program product are provided for implementing command timing adjustments to alleviate Dynamic Random Access Memory (DRAM) failures in a computer system. A predefined DRAM failure is detected. Responsive to the detected failure, a set of timers is adjusted for controlling predetermined timings used to access the DRAM. Responsive to the failure being resolved by the adjusted set of timers, checking for a predetermined level of performance is performed. | 03-06-2014 |
20140143510 | ACCESSING ADDITIONAL MEMORY SPACE WITH MULTIPLE PROCESSORS - An apparatus and method is provided for coupling additional memory to a plurality of processors. The method may include determining the memory requirements of the plurality of processors in a system, comparing the memory requirements of the plurality of processors to an available memory assigned to each of the plurality of processors, and selecting a processor from the plurality of processors that requires additional memory capacity. The apparatus may include a plurality of processors, where the plurality of processors is coupled to a logic element. In addition, the apparatus may include an additional memory coupled to the logic element, where the logic element is adapted to select a processor from the plurality of processors to couple with the additional memory. | 05-22-2014 |
20140164819 | MEMORY OPERATION OF PAIRED MEMORY DEVICES - A method and apparatus for operation of a memory module for storage of a data word is provided. The apparatus includes a memory module having a set of paired memory devices including a first memory device to store a first section of a data word and a second memory device to store a second section of the data word when used in failure free operation. The apparatus may further include a first logic module to perform a write operation by writing the first and second sections of the data word to both the first memory device and the second memory device upon the determination of certain types of failure. The determination may include that a failure exists in the word section storage of either the first or second memory devices but that no failures exist in equivalent locations of word section storage in the two memory devices. | 06-12-2014 |
20140164853 | MEMORY OPERATION OF PAIRED MEMORY DEVICES - A method and apparatus for operation of a memory module for storage of a data word is provided. The apparatus includes a memory module having a set of paired memory devices including a first memory device to store a first section of a data word and a second memory device to store a second section of the data word when used in failure free operation. The apparatus may further include a first logic module to perform a write operation by writing the first and second sections of the data word to both the first memory device and the second memory device upon the determination of certain types of failure. The determination may include that a failure exists in the word section storage of either the first or second memory devices but that no failures exist in equivalent locations of word section storage in the two memory devices. | 06-12-2014 |
20140188409 | DETECTING TSV DEFECTS IN 3D PACKAGING - A computer determines a threshold signal voltage of a semiconductor device. The computer determines a first expected signal propagation time for a signal travelling through a first test path of the semiconductor device. The computer transmits a first signal through the first test path. The computer measures a signal voltage and signal propagation time of the first signal. The computer determines that the signal voltage of the first signal does not reach or exceed the threshold signal voltage within the first expected signal propagation time. The computer determines that the first test path contains a defect. | 07-03-2014 |
20140250340 | SELF MONITORING AND SELF REPAIRING ECC - Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment detects that a specified number of correctable errors is exceeded. In another step, an exemplary embodiment detects the occurrence of an uncorrectable error. In another step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test. | 09-04-2014 |
20140281681 | ERROR CORRECTION FOR MEMORY SYSTEMS - According to one embodiment, a method for error correction in a memory module having ranks is provided where each rank has memory devices. The method includes determining a first mark condition for a first rank of the memory module, the first mark condition based on one or more uncorrectable error occurring in a first memory device in the first rank, placing a first mark in the first memory device, determining a second mark condition for the first rank, the second mark condition based on one or more uncorrectable error occurring in a second memory device in the first rank, placing a second mark in a third memory device in a second rank of the memory module and configuring the first memory device to respond to commands directed to the second rank, wherein configuring the first memory device is based on placing of the first mark and the second mark. | 09-18-2014 |
20140317473 | IMPLEMENTING ECC REDUNDANCY USING RECONFIGURABLE LOGIC BLOCKS - A method, system and computer program product are provided for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system. When a fail is detected when reading from memory, it is determined if the incorrect data is in the data or the ECC component of the data. When incorrect data is found in the ECC component of the data, and an actionable threshold is not reached, a predetermined Reliability, Availability, and Serviceability (RAS) action is taken. When the actionable threshold is reached with incorrect data identified in the ECC component of the data, an analysis process is performed to determine if the ECC logic is faulty. When a fail in the ECC logic is detected, the identified ECC failed logic is replaced with a spare block of logic. | 10-23-2014 |
20140328132 | MEMORY MARGIN MANAGEMENT - A method for testing and correcting a memory system is described. The method includes selecting a target memory unit of the memory system having a timing margin in response to a trigger to start a timing margin measurement. The stored data in the target memory unit is moved to a spare memory unit. The memory system performs reads and writes of user data from the spare memory unit while measuring the target memory unit. The timing margins of the target memory unit are measured. The reliability of the measured timing margins of the target memory unit based on a timing margin profile is determined. | 11-06-2014 |
20140334224 | REFERENCE VOLTAGE MODIFICATION IN A MEMORY DEVICE - A method and apparatus for modifying a reference voltage between refreshes in a memory device are disclosed. The memory array may include a plurality of memory cells. The memory device may also include a sense amplifier. The sense amplifier may be configured to read data from the plurality of memory cells using a reference voltage. The memory device may also include a sense amplifier reference voltage modification circuit. The sense amplifier reference voltage modification circuit may be configured to detect a triggering event and modify the reference voltage in response to detecting a triggering event. | 11-13-2014 |
20140334225 | PRIORITIZING REFRESHES IN A MEMORY DEVICE - A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event. | 11-13-2014 |
20140355369 | MEMORY OPERATION UPON FAILURE OF ONE OF TWO PAIRED MEMORY DEVICES - A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices. | 12-04-2014 |
20150033002 | REQUESTING MEMORY SPACES AND RESOURCES USING A MEMORY CONTROLLER - Methods of requesting memory spaces and resources using a memory controller are provided. A particular method may include communicating, by a memory controller, a request to a computer program for a resource, and using the resource in response to an indication from the computer program that the resource is available. Another particular method may include communicating a request to a memory controller for at least one of a memory space of a memory or a second resource. The memory controller may be configured to communicate the request from the first resource to a computer program. Another particular method may also include using, by the first resource, at least one of the memory space or the second resource in response to an indication that the memory space or the second resource is available. | 01-29-2015 |
20150106569 | CHIP STACK CACHE EXTENSION WITH COHERENCY - By arranging dies in a stack such that failed cores are aligned with adjacent good cores, fast connections between good cores and cache of failed cores can be implemented. Cache can be allocated according to a priority assigned to each good core, by latency between a requesting core and available cache, and/or by load on a core. | 04-16-2015 |
20150127898 | SYSTEM AND MEMORY CONTROLLER FOR INTERRUPTIBLE MEMORY REFRESH - A refresh command is communicated to a memory device to initiate an interruptible refresh which contains multiple segment refreshes separated by interrupt boundaries. A command is communicated to the memory device before execution of a segment refresh and the segment refresh is delayed at an interrupt boundary. Alternatively, a first number of commands in a queue is determined. A first number of segment refreshes to execute is determined based on the first number of commands. The first number of segment refreshes to execute is communicated to the memory device to cause execution of the first number of segment refreshes. A second number of commands in the queue is determined. A second number of segment refreshes to execute is determined based on the second number of commands. The second number of segment refreshes to execute is communicated to the memory device to cause execution of the second number of segment refreshes. | 05-07-2015 |
20150127899 | MEMORY DEVICE FOR INTERRUPTIBLE MEMORY REFRESH - A refresh command is received from a memory controller. An interruptible refresh containing multiple segment refreshes is initiated. The segment refreshes are separated by interrupt boundaries. A command is received before execution of a segment refresh. The first command is executed and execution of the first segment refresh is delayed at a first interrupt boundary. Alternatively, a first number of segment refreshes to execute is received from a memory controller. The received first number of segment refreshes is executed. A second number of segment refreshes to execute is received from a memory controller. The received second number of segment refreshes is executed. No segment refreshes are executed between the execution of the first number of segment refreshes and the execution of the second number of segment refreshes. | 05-07-2015 |
20150178147 | SELF MONITORING AND SELF REPAIRING ECC - Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test. | 06-25-2015 |
20150213853 | IMPLEMENTING SIMULTANEOUS READ AND WRITE OPERATIONS UTILIZING DUAL PORT DRAM - A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes. | 07-30-2015 |
20150213854 | IMPLEMENTING SIMULTANEOUS READ AND WRITE OPERATIONS UTILIZING DUAL PORT DRAM - A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes. | 07-30-2015 |
Patent application number | Description | Published |
20090303001 | SYSTEM FOR DETECTING AND COMMUNICATING WITH RFID MEMORY DEVICES - This invention relates to a system of communicating with a radio frequency identification (RFID) transponder microchip (IC) for the purpose of accessing pre-programmed data. Such system involves direct electrical contact between the system reading the data from the memory in the transponder IC and the IC itself via two mechanical contact points. This system provides an interface with a transponder IC in order to energize the IC. Once the presence of the transponder IC is detected, the host system can read or write to and process preprogrammed data stored in the IC. | 12-10-2009 |
20100022864 | SKIN PREPARATION DEVICE AND BIOPOTENTIAL SENSOR - The skin preparation device and sensor of the present invention include an array of rigid tines. The tines serve to “self-prepare” the skin at each electrode site. These tines, when pressed against the skin, penetrate the stratum corneum, thereby reducing skin impedance and improving signal quality. A self-prepping device of the present invention is an optimized array of short non-conductive rigid tines in which the individual tines are created in a geometry that allows for a sharp point at the tip when molding, machining or etching is used as a method of fabrication. This non-conductive array with rigid penetrating structures may, therefore, be used in combination with a conductive medium, preferably an ionic conductive gel. In penetrating the stratum corneum, micro-conduits are created in the layers of the skin enabling the conductive medium to reach the low impedance layers and to transmit bioelectrical signals from the skin to the electrode surface. Such a self-prepping device can be readily mass produced using molding methods or possibly other manufacturing methods, thereby providing for a low cost means of achieving improved performance of the biopotential sensor. Additionally this invention includes the integration of this self-prepping device into a biopotential sensor comprising an array of one or more electrodes. | 01-28-2010 |
20110273270 | PHYSIOLOGICAL SENSOR SYSTEM WITH AUTOMATIC AUTHENTICATION AND VALIDATION BY MEANS OF A RADIO FREQUENCY IDENTIFICATION PROTOCOL WITH AN INTEGRATED RFID INTERROGATOR SYSTEM - This invention relates to a physiological sensor which acquires pre-programmed data from an electrode or an electrode array using Radio Frequency Identification (RFID) technology. The source of the sensor may be authenticated by means of a wireless interface between an RFID transponder affixed to the electrode array, and an RFID interrogator embedded in the patient interface cable. The criteria for use are then verified to ensure that they are met by the electrode array before beginning signal acquisition. If the criteria are not met, a message is provided to the user via the monitor. | 11-10-2011 |
20120098646 | PHYSIOLOGICAL SENSOR SYSTEM WITH AUTOMATIC AUTHENTICATION AND VALIDATION BY MEANS OF A RADIO FREQUENCY IDENTIFICATION PROTOCOL WITH AN INTEGRATED RFID INTERROGATOR SYSTEM - This invention relates to a physiological sensor which acquires pre-programmed data from an electrode or an electrode array using Radio Frequency Identification (RFID) technology. The source of the sensor may be authenticated by means of a wireless interface between an RFID transponder affixed to the electrode array, and an RFID interrogator embedded in the patient interface cable. The criteria for use are then verified to ensure that they are met by the electrode array before beginning signal acquisition. If the criteria are not met, a message is provided to the user via the monitor. | 04-26-2012 |
20120251790 | SYSTEMS AND METHODS FOR CREATING SHARP FEATURES WITHIN A MOLD - The present disclosure describes systems and methods for creating sharp features within a mold. For example, three or more mold plates may be provided to create a single mold assembly. Each mold plate includes one or more mold cavities, each having one or more surfaces. The provided mold plates may be assembled to form the mold assembly having a combined mold cavity between adjacent mold cavities of the mold plates. Although none of the individual mold cavities of the mold plates include sharp features, when the mold assembly is assembled, a combined mold cavity will include sharp transitions (e.g., angles of less than 180 degrees, right angles, angles of less than 90 degrees, and so forth) between adjacent surfaces of the mold cavities. In certain embodiments, sets of mold plates may be re-aligned to create varying mold cavity geometries. In addition, in certain embodiments, a mold pin may be inserted into an inner volume of a mold plate to both create additional sharp transitions between adjacent surfaces. | 10-04-2012 |
20120253163 | METHOD AND SYSTEM FOR POSITIONING A SENSOR - Embodiments of the present disclosure relate to sensor designs or shapes configured to facilitate placement of sensor electrodes and, thus, proper positioning of the sensors on patients. According to certain embodiments, a sensor may include a substrate that includes multiple electrodes, where a first electrode is configured to be placed on a patient's temple and a second electrode is configured to be placed on a patient's forehead directly above a patient's eyebrow. The sensor may include a particular shape and a fixed distance between the first and second electrodes to facilitate proper angling and positioning of the first and second electrodes as well as the other electrodes (e.g., third and fourth electrodes). Other embodiments may include a method for positioning the sensor on the patient, including a monitor with help screens. | 10-04-2012 |
20130023748 | DEVICE WITH ENCAPSULATED GEL - Apparatus and techniques are provided for interfacing a device with a surface. The apparatus and techniques provide gel encapsulation and isolation mechanisms to extend the shelf-life of the preparation devices, allow for the use of more effective materials, and improve the quality of the contact between a device and an application surface. Particular embodiments of these apparatus and techniques suitable for use in medical contexts are also provided. | 01-24-2013 |
20130023749 | FORCE REGULATING DEVICE APPLICATORS - Disclosed herein are apparatus and techniques for applying a device to a subject. Such apparatus and techniques may provide feedback to an operator and/or regulate the force used to apply the device, yielding an improved result. Particularly useful embodiments include apparatus and techniques for applying a medical device, such as a skin surface electrode or microneedle array, to a patient's tissue. | 01-24-2013 |
20140159917 | PHYSIOLOGICAL SENSOR SYSTEM WITH AUTOMATIC AUTHENTICATION AND VALIDATION BY MEANS OF A RADIO FREQUENCY IDENTIFICATION PROTOCOL WITH AN INTEGRATED RFID INTERROGATOR SYSTEM - This invention relates to a physiological sensor which acquires pre-programmed data from an electrode or an electrode array using Radio Frequency Identification (RFID) technology. The source of the sensor may be authenticated by means of a wireless interface between an RFID transponder affixed to the electrode array, and an RFID interrogator embedded in the patient interface cable. The criteria for use are then verified to ensure that they are met by the electrode array before beginning signal acquisition. If the criteria are not met, a message is provided to the user via the monitor. | 06-12-2014 |
20140296683 | SKIN PREPARATION DEVICE AND BIOPOTENTIAL SENSOR - The skin preparation device and sensor of the present invention include an array of rigid tines. The tines serve to “self-prepare” the skin at each electrode site. These tines, when pressed against the skin, penetrate the stratum corneum, thereby reducing skin impedance and improving signal quality. A self-prepping device of the present invention is an optimized array of short non-conductive rigid tines in which the individual tines are created in a geometry that allows for a sharp point at the tip when molding, machining or etching is used as a method of fabrication. This non-conductive array with rigid penetrating structures may, therefore, be used in combination with a conductive medium, preferably an ionic conductive gel. In penetrating the stratum corneum, micro-conduits are created in the layers of the skin enabling the conductive medium to reach the low impedance layers and to transmit bioelectrical signals from the skin to the electrode surface. Such a self-prepping device can be readily mass produced using molding methods or possibly other manufacturing methods, thereby providing for a low cost means of achieving improved performance of the biopotential sensor. Additionally this invention includes the integration of this self-prepping device into a biopotential sensor comprising an array of one or more electrodes. | 10-02-2014 |