Patent application number | Description | Published |
20080215822 | PCI Express Enhancements and Extensions - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 09-04-2008 |
20100169523 | Scalable method and apparatus to configure a link - Disclosed herein are reconfigurable ports and methods for doing the same. | 07-01-2010 |
20110072164 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 03-24-2011 |
20110161703 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 06-30-2011 |
20110173367 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 07-14-2011 |
20110238882 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 09-29-2011 |
20120036293 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 02-09-2012 |
20120089750 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 04-12-2012 |
20130046908 | SCALABLE METHOD AND APPARATUS TO CONFIGURE A LINK - Disclosed herein axe reconfigurable ports and methods for doing the same. | 02-21-2013 |
Patent application number | Description | Published |
20090172185 | UNIFIED CONNECTOR ARCHITECTURE - A system, device, and method are disclosed. In one embodiment the system includes a first host controller that utilizes a first protocol. The system also includes a second host controller that utilizes a second protocol. The system also includes a unified connector port. Finally, the system includes a router that is coupled to the first host controller, the second host controller, and the unified connector port. The router is functionally capable of encapsulating a physical layer packet from the first host controller into a first unified connector protocol frame and then transmits the new first frame to the unified connector port. The router is also capable of encapsulating a physical layer packet that it receives from the second host controller into a second unified connector protocol frame and then transmits the second frame to the unified connector port. The first and second protocols are not the same protocol. | 07-02-2009 |
20100049885 | Unified multi-transport medium connector architecture - A device, method, and system are disclosed. In one embodiment the device includes a router to transmit data packets between multiple host controllers and one or more peripheral devices. The router can receive a data packet from a host controller and transmit the data packet to a peripheral device across a data transmission path. The peripheral device is coupled to the first data transmission path through a first universal multi-transport medium (UMTM) connector. The connector includes an optical coupling capable of transporting the first data packet within an optical signal and an electrical coupling capable of transporting the first data packet within an electrical signal. | 02-25-2010 |
20110072234 | Providing Hardware Support For Shared Virtual Memory Between Local And Remote Physical Memory - In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed. | 03-24-2011 |
20130091317 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 04-11-2013 |
20130097353 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 04-18-2013 |
20130111086 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS | 05-02-2013 |
20130132622 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-23-2013 |
20130132636 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-23-2013 |
20130132683 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-23-2013 |
20140073302 | Sensor and Context Based Adjustment of the Operation of a Network Controller - A method to adjust operation of a network controller of a device is disclosed. The method may include receiving contextual data from a sensor communicatively coupled to the device. The method may also include analyzing the contextual data to determine the context of the device. The method may also include modifying the network controller operation based on the analyzed contextual data. | 03-13-2014 |
20140208042 | PROVIDING HARDWARE SUPPORT FOR SHARED VIRTUAL MEMORY BETWEEN LOCAL AND REMOTE PHYSICAL MEMORY - In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed. | 07-24-2014 |
20140223042 | UNIFIED MULTI-TRANSPORT MEDIUM CONNECTOR ARCHITECTURE - A device, method, and system are disclosed. In one embodiment the device includes a router to transmit data packets between multiple host controllers and one or more peripheral devices. The router can receive a data packet from a host controller and transmit the data packet to a peripheral device across a data transmission path. The peripheral device is coupled to the first data transmission path through a first universal multi-transport medium (UMTM) connector. The connector includes an optical coupling capable of transporting the first data packet within an optical signal and an electrical coupling capable of transporting the first data packet within an electrical signal. | 08-07-2014 |
Patent application number | Description | Published |
20110067597 | MIXED PHTHALOCYANINE AND NAPHTHALOCYANINE DYES FOR NEAR-INFRARED APPLICATIONS - Mixed phthalocyanine and naphthalocyanine water-soluble dyes with near-infrared absorption comprise four isoindole units linked together in a large ring to form a phthalocyanine macrocycle. At least one benzene ring is linked to an isoindole unit and at least one naphthalene ring is linked to another isoindole unit. The remaining two isoindole units each have a benzene ring or a naphthalene ring linked thereto, in any combination. A metal atom is optionally complexed to the phthalocyanine macrocycle. | 03-24-2011 |
20110073005 | POLYPHENYLATED PHTHALOCYANINES WITH NEAR-INFRARED ABSORPTION - Polyphenylated phthalocyanine water-soluble dyes with near-infrared absorption comprise four isoindole units linked together in a large ring to form a phthalocyanine macrocycle, with either four anthracenyl groups or four naphthacenyl groups each linked to an isoindole, and a metal atom optionally complexed to the phthalocyanine macrocycle. | 03-31-2011 |
20120092428 | INK-JET INKS HAVING POLYMERS AND NEAR-INFRARED ABSORBING DYES - The present disclosure is drawn to methods and compositions directed at durable ink-jet inks. As such, an ink-jet ink can comprise a liquid vehicle, a colorant dispersed or dissolved in the liquid vehicle, a high T | 04-19-2012 |
20120137927 | PHTHALOCYANINES AND NAPHTHALOCYANINES WITH NEAR-IR ABSORPTIONS FOR INKJET INKS - A water-soluble phthalocyanine dye or naphthalocyanine dye with near-infrared absorption comprises at least one complexed unit. Each unit comprises a phthalocyanine or a naphthalocyanine moiety and, optionally, a metal atom complexed thereto and, if present, having a valency of from 1 to 5, with two valencies complexed to the phthalocynanine ring or the naphthalocyanine ring. Each unit has two linker moieties on opposite sides or adjacent sides of the unit, wherein water-soluble groups are present on at least one of the linkers, on the metal atom, and optionally on the phthalocyanine or naphthalocyanine moiety. | 06-07-2012 |
20120137928 | PHTHALOCYANINES AND NAPHTHALOCYANINES WITH NEAR-IR ABSORPTIONS FOR INKJET INKS - A water-soluble phthalocyanine dye or naphthalocyanine dye with near-infrared absorption comprises at least one complexed unit. Each unit comprises a phthalocyanine or a naphthalocyanine moiety and a metal atom complexed thereto and having a valency of at least three, with two valencies complexed to the phthalocynanine ring or the naphthalocyanine ring, each unit joined to another through a fused ring, at least one valency attached to water-soluble axial ligands. The dyes to may be employed in inkjet inks in conjunction with colorants. | 06-07-2012 |
20120174821 | DISPERSION OF NEAR INFRARED ABSORBING PIGMENTS AND METHOD OF MAKING THE SAME - A pigment dispersion containing milled particles of near infrared (NIR) absorbing pigment and an anionic surfactant of asymmetric structure as dispersant for the pigment, and a milling method for making the same are disclosed. | 07-12-2012 |
20130070015 | INK SET WITH NEAR INFRARED DETECTION CAPABILITY AND METHOD OF USING THE SAME - An ink set with near infrared detection capability is disclosed. The ink set includes a cyan ink including a cyan colorant, a magenta ink including a magenta colorant, and a yellow ink including a yellow colorant, each of the colorants having maximum light absorbance in the visible wavelength range of about 400 to 750 nm, wherein each of the cyan, magenta and yellow inks includes a near infrared (NIR) absorbing pigment, which is different in spectral absorption characteristic from the colorant and absorbs light in the wavelength range of about 750 to 1200 nm. | 03-21-2013 |
Patent application number | Description | Published |
20080258454 | Security printing and detecting systems and methods - A method of security printing can comprise the steps of printing a transparent ink onto a portion of a coated substrate resulting in printed region and an unprinted region, where the transparent ink is devoid of dyes, pigments, ceramics, metallics, and fluorescents; illuminating both the printed region and the unprinted region of the substrate, where the printed region scatters more light than the unprinted region creating a contrast; and detecting the contrast with a sensor that is sensitive to detecting light scattering differences between the printed region and the unprinted region. | 10-23-2008 |
20080266565 | Device and method for measuring ink levels in a container - An ink level sensing device and associated method. The ink level sensing device includes a near infrared illumination source that emits near infrared light, and a container configured to accommodate a supply of ink containing light absorption material. The device further includes a protruding chamber adjacent to the container. The protruding chamber is configured to accommodate a portion of the supply of ink accommodated by the container. The device also includes a sensor that is configured to receive a signal based on an amount of the light that passes through the protruding chamber. The method includes emitting a light from a near infrared illumination source and directing the light toward a protruding chamber of the ink supply. The method further includes sensing an amount of the light that passes through the protruding chamber in the ink supply. | 10-30-2008 |
20080269049 | Color forming compositions with a fluoran leuco dye having a latent developer - Compositions and systems for production of color images with a fluoran leuco dye having a latent developer are disclosed and described. A color forming composition or composite can include a polymer matrix, a thermally modifiable fluoran leuco dye having a latent developer attached thereto, and a radiation absorber. The thermally modifiable fluoran leuco dye can be developable upon the color forming composition being contacted with electromagnetic radiation which causes the radiation absorber to become energized, so that the energized radiation absorber causes the latent developer to undergo rearrangement to produce an intermediate dye form having a phenolic substituent. The intermediate dye can then undergo an acid catalyzed ring opening to produce a colored dye form. | 10-30-2008 |
20080317958 | Pigmented ink-jet ink with improved highlighter smear - Compositions, systems, and methods of printing an ink-jet image are provided. The composition can be an ink-jet ink, comprising a liquid vehicle, a pigmented colorant, and a wax emulsion. The wax emulsion can be present at from about 0.1 wt % to about 20 wt %, preferably 0.1 wt % to 10 wt %, and more preferably from 0.1 wt % to 5 wt % solid content of the ink-jet ink composition. Additionally, upon printing the ink-jet ink on a media substrate compared to printing a comparative ink-jet ink composition on a media substrate, the ink-jet ink composition exhibits improved alkaline highlighter smear fastness compared to the comparative ink-jet ink composition. | 12-25-2008 |
20110079716 | PHTHALOCYANINE, NAPHTHALOCYANINE, AND BRIDGED PHTHALOCYANINE/NAPHTHALOCYANINE DYES AND INKS CONTAINING THE SAME - Phthalocyanine dyes, naphthalocyanine dyes, and/or bridged phthalocyanine/naphthalocyanine dyes represented by one of the general structures I to XVII, inkjet ink formulation comprising said dyes, and detection systems using said dyes are disclosed and described. | 04-07-2011 |
20110094413 | PHTHALOCYANINE DYE AND INK CONTAINING THE SAME - Phthalocyanine dyes represented by the general structures (I) to (IV) and inkjet ink formulation including the phthalocyanine dyes. | 04-28-2011 |
20110135815 | INKS WITH WATER SOLUBLE NEAR IR DYES - The methods and compositions of the present invention provide an ink jet ink having a colorant, an aqueous vehicle, and water stable and water soluble phthalocyanine and/or naphthalocyanine dye chromophores. | 06-09-2011 |
20110204234 | PHTHALOCYANINE DYE WITH EXTENDED CONJUGATION, INK AND DETECTION SYSTEM USING SAME - A phthalocyanine dye with extended conjugation includes one or both of a phthalocyanine component and a naphthalocyanine component and at least one water soluble substituent on an aryl group of the phthalocyanine dye. The extended conjugation of the phthalocyanine dye includes at least one benzene moiety of the component being one of (a) joined to an aryl group either indirectly using an alkylene linkage or directly, (b) joined to a benzene moiety of another of the components to form an oligomer of the components, and (c) a combination of (a) and (b). The extended conjugation shifts absorption of the phthalocyanine dye to greater than 800 nm. | 08-25-2011 |
20120139994 | NAPHTHALOCYANINE DYE AND INK CONTAINING THE SAME - The present disclosure includes naphthalocyanine dyes or fused naphthalocyanine dyes represented by one of the general structures I to XV; inkjet ink formulations including the naphthalocyanine dyes; and a detection system ( | 06-07-2012 |
20130164500 | PRINTED ARTICLE - A printed article with metallic luster and gold-like appearance that encompasses a printable media on which a printed feature has been formed with an ink composition. The ink composition contains iron oxide pigment particles that have an average particle 5 size in the range of about 3 to about 300 nm and the printable media contains a bottom supporting substrate and ink-absorbing layer with pore diameters that are smaller than the average size of the iron oxide pigment particles. In such printed article, the ink composition forms onto the printable media a printed feature that has a thickness that is below about 300 nm. | 06-27-2013 |
20130183501 | PRINTING METHOD - A method for producing printed articles that encompasses providing a first ink composition that contains metal oxide particles with an average particle size in the range of about 3 to about 300 nm; providing a second ink composition that contains colored pigments dispersed in an ink vehicle; providing a printable media having a bottom supporting substrate and an ink-absorbing layer with pore diameters that are smaller than the size of the metal oxide pigment particles and colored pigments; and sequentially applying, on the same print area, the first and the second ink compositions onto said printable media. Also disclosed herein are the printed articles obtained according to the present method. | 07-18-2013 |
20140137766 | PERFLUOROPOLYETHERS AS INK ADDITIVES - An ink is disclosed. The ink composition includes an ink vehicle, a colorant, and a fluorosurfactant, wherein the fluorosurfactant is a polymer having the general formula: | 05-22-2014 |