Hsieh, Hsinchu City
An-Yu Hsieh, Hsinchu City TW
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20130258653 | LIGHT DEVICE AND ITS LIGHT EMITTING DIODE MODULE - A light device and its light emitting diode module are provided in the disclosure. The light emitting diode module includes a substrate, an arrayed light emitting group and a single sealant body. The arrayed light emitting group includes a plurality of light emitting strings connected between a positive pole and a negative pole in parallel. Each light emitting strings includes a plurality of blue light emitting diode chips and a red light emitting diode chips, which are both electrically connected on the substrate in series. The single sealant body completely covers all of the light emitting strings, and is contained with phosphors uniformly therein. | 10-03-2013 |
Betty Hsieh, Hsinchu City TW
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20110062526 | METAL GATE TRANSISTOR, INTEGRATED CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer. | 03-17-2011 |
Chang-Huain Hsieh, Hsinchu City TW
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20100177190 | MICROSCOPY SYSTEM WITH REVOLVABLE STAGE - A microscopy system includes an image focusing module, a stage for supporting a sample, image collection unit for collecting sliced images of the sample acquired by the image focusing module, and an image fusion unit for fusing sliced images of the sample acquired from different observation angles. The stage supports the sample and is configured to be revolvable around a rotational axis which is substantially perpendicular to an extending direction from the sample to the image focusing module so that enabling the image focusing module to acquire sliced images of the sample from different observation angles. The image fusion unit is used for remapping the sliced images acquired from different observation angles into a reference coordinate system, converting anisotropic voxels resolution of the sliced images to isotropic resolution, and fusing the sliced images into a final image. | 07-15-2010 |
Chao-Hsiang Hsieh, Hsinchu City TW
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20120060926 | POLYMERIZABLE FULLERENE DERIVATIVE AND THEIR USE IN ORGANIC PHOTOVOLTAIC CELLS - The present invention discloses an inverted organic photovoltaic cell comprising a polymerizable fullerene interlayer adapted to enhance the device performance and lifetime. The polymerizable fullerene derivative comprises a fullerene core, a bridging functional group and a polymerizable functional group. The fullerene core can be either C | 03-15-2012 |
Cheng-Chieh Hsieh, Hsinchu City TW
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20120145796 | DATA STORAGE DEVICE, STACKING METHOD THEREOF, AND DATA STORAGE DEVICE ASSEMBLY - A data storage device, a stacking method thereof, and a data storage device assembly are provided. The data storage device assembly includes a first data storage device and a second data storage device respectively having a body, a magnetic element, and a storage device. Each body has a first containing space and a second containing space. Each magnetic element is disposed in the corresponding first containing space. At least one of the magnetic elements of the first and the second data storage device is a magnet. Each storage device is disposed in the corresponding second containing space and includes an electrical connector terminal, a memory chip, and a memory controller with no crystal oscillator. The magnetic elements of the first and the second data storage device attract each other so that the body of the first data storage device is stacked on the body of the second data storage device. | 06-14-2012 |
Chia-Chi Hsieh, Hsinchu City TW
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20130087278 | METHOD FOR BONDING COMPONENTS BY UTILIZING JOULE HEATING TO CURE CARBON NANOTUBE-EPOXY RESIN COMPOSITE ADHESIVE - The using of carbon nanotubes to produce a thin film or buckypaper, hereafter referred to as carbon nanotube membrane, which is soaked with epoxy resin or a carbon nanotube-epoxy resin composite adhesive, and then placed between the joining edges of components, where after an electric current is passed through to heat up the carbon nanotube membrane. This leads to the curing temperature of the epoxy resin or carbon nanotube-epoxy resin composite adhesive, thereby hardening the epoxy resin or carbon nanotube-epoxy resin composite adhesive to achieve bonding. This invention utilizes simple equipment, and the method of an electric current passing through for heating, which can rapidly and uniformly heat the epoxy resin or carbon nanotube-epoxy resin composite adhesive, resulting in hardening and bonding. This method is not affected by the environment, and greatly reduces the time and resources required to harden the epoxy resin, and achieves a stronger effect additionally. | 04-11-2013 |
Chien-Chen Hsieh, Hsinchu City TW
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20140068924 | Method for Manufacturing Optoelectronic Module - A method for manufacturing an optoelectronic module is proposed. The method comprises the following steps: providing a top cover with a reflective surface. Then, a light-guiding structure is formed. A mounting device is provided. Next, an optoelectronic device is formed on the mounting device with a first precision. A control chip is formed on the mounting device with a second precision different from the first precision. The top cover combines with the mounting device, wherein the light-guiding structure is between the top cover and the mounting device, and the optoelectronic device faces the reflective surface. | 03-13-2014 |
Chien Te Hsieh, Hsinchu City TW
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20100267276 | Strap with transmission line functionality - A strap with transmission line functionality includes a strap body, a first connecting end and a second connecting end. The strap body has at least one signal line wrapped therein. The first connecting end is disposed at one end of the strap body and the second connecting end is disposed at an opposite end of the strap body so that signals can be transmitted between the first connecting end and the second connecting end via the signal line disposed in the strap body. The first connecting end is directly fixed to and electrically connected with an electronic product, and a signal connector is also disposed at the second connecting end to connect with an external device. The strap body is substantially looped into a circular form so as to be used as a wrist strap or a neck strap of the electronic product. | 10-21-2010 |
Chien-Yu Hsieh, Hsinchu City TW
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20130100731 | INDEPENDENTY-CONTROLLED-GATE SRAM - The present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-V | 04-25-2013 |
Chih-Chang Hsieh, Hsinchu City TW
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20140078804 | Mask Design With Optically Isolated Via and Proximity Correction Features - A lithography mask and method for manufacturing such mask that includes optically isolated via features and proximity correction features. The via patterns that include via features that define vias are positioned on the mask in rows and columns with a row and a column pitch between each row and column on the mask. The via patterns are positioned such that via features that are in adjacent columns are separated by at least one intervening row between them. The via patterns can also be positioned such that the via patterns that are in adjacent rows are separated by at least one intervening column between them. As a result, the via feature of each via pattern and the associated optical proximity correction features that are positioned around each via feature do not overlap with the optical proximity correction features and the via features of the surrounding via patterns. | 03-20-2014 |
20140273505 | SEMICONDUCTOR APPARATUS WITH TRANSPORTABLE EDGE RING FOR SUBSTRATE TRANSPORT - An apparatus and method for processing semiconductor substrates provides a substrate stage being a rotatable disc with a solid surface and a terraced edge with upper, intermediate and lower portions of increasing diameter. A hollow edge ring rests on the intermediate edge portion and a substrate disposed on the rotatable disc is lifted and transported by robot blades positioned beneath the edge ring and which lift the edge ring which holds the substrate around its edges. The rotatable disc and edge ring find application in MOCVD and other semiconductor manufacturing tools. | 09-18-2014 |
Chih-Cheng Hsieh, Hsinchu City TW
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20130335132 | CIRCUIT SHARING TIME DELAY INTEGRATOR - The present invention discloses a circuit sharing time delay integrator structure. The major composing elements of this circuit sharing time delay integrator structure are: a sharing circuit, a first control block, a plurality of second control blocks and a timing set generated by a timing generator circuit. The sharing circuit can be an OP-AMP, an active load, or any of a variety of combinations used in signal accumulation applications. With the implementation of the present invention to applications of signal accumulations, the necessity of an adder circuitry is eliminated, the overall circuitry and hence the total amount of transistors required when producing the integrated circuit is massively reduced, and thus a great cost reduction and better timing and power efficiency can all be thereof achieved. | 12-19-2013 |
20140084136 | OPTICAL RECOGNITION SYSTEM AND METHOD THEREOF - The present invention is related to an optical recognition system and a method thereof, and more particularly to an optical recognition system and a method that adopts a single-slope analog-to-digital converter to proceed a single-slope analog-to-digital conversion in order to have an image with a wide dynamic range. | 03-27-2014 |
Chih-Wel Hsieh, Hsinchu City TW
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20100285991 | COMBINATORY ANALYTICAL STRIP - A combinatory analytical strip including a substrate is disclosed. A first channel for a biochemical assay and a second channel for an immunological assay are provided concavely on an upper surface of the substrate. The results of both assays are detected by a sensor. Each channel includes a first area for receiving a fluid sample, a second area for delivering the fluid sample and a third area where the fluid sample reacts. These three areas are connected successively. A nitrocellulose layer having a hollow-matrix conformation is formed at a bottom of each of the second and third areas of both channels. Each of the nitrocellulose layers of the second areas comprises an average thickness that is not greater than that of each the nitrocellulose layers of the third areas. A reaction material is formed in the hollow-matrix conformation. The third areas of the first and second channels are both located on a line conforming a relative motion path of the sensor and the combinatory analytical strip. | 11-11-2010 |
Chin-I Hsieh, Hsinchu City TW
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20140084991 | TOUCH SENSOR CIRCUIT AND TOUCH DISPLAY DEVICE - A touch sensor circuit and a touch device are provided. The touch sensor circuit includes a charging capacitor, a first current supplying unit, a second current supplying unit, and a switch unit. Wherein, the charging capacitor is serially connected between a detecting terminal and a reference voltage. The first current supplying unit is coupled to the detecting terminal, and receives a first bias voltage signal, and generates a first charging current at the detecting terminal according to the first bias voltage signal. A second current supplying unit is coupled to the detecting terminal, and receives a second bias voltage signal, and generates a second charging current at the detecting terminal according to the second bias voltage signal. The second terminal and the third terminal of the switch respectively supply the first and the second bias voltage signal. | 03-27-2014 |
Chin-Kun Hsieh, Hsinchu City TW
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20110007521 | BACKLIGHT MODULE WITH A HEAT CONDUCTIVE BLOCK - A backlight module includes a bezel having at least one edge, a circuit board, one or more light emitting diodes connected to the circuit board for emitting light. Each light emitting diode has a light axis which is neither parallel nor vertical to the edge of the bezel. The backlight module utilizes a heat conductive block disposed between the bezel and the light emitting diode for transferring heat generated by the light emitting diode to the bezel. | 01-13-2011 |
20120113675 | LAMP DEVICE WITH COLOR-CHANGEABLE FILTER - A lamp device includes a supporting frame, a light emitting diode (LED) array source, a light filter, two end caps and two couples of electrodes. The LED array source is disposed on the supporting frame. The light filter is arc-shaped and combined with the supporting frame as a tubular structure, wherein the arc surface of the light filter is a light emitting surface of the LED array source. The light filter is used for absorbing a ray in a specific wavelength range of the emitting light of the LED array source. The two end caps are disposed at two ends of the tubular structure respectively. The two couples of electrodes are disposed at two ends of the tubular structure and mounted on the two end caps respectively for electrically connecting to the LED array source. | 05-10-2012 |
20120175655 | LIGHT EMITTING DIODE CUP LAMP - A light emitting diode (LED) cup lamp including a base, an LED light source and a light guiding device is disclosed. The LED light source is disposed on the base. The light guiding device is disposed above the LED light source. The light guiding device has a light guiding region facing the LED light source. After the light emitted from the LED light source is guided through the light guiding region, the light is further guided by other parts of the light guiding device so that the light is emitted towards the exterior of the LED cup lamp. | 07-12-2012 |
20120243216 | LAMP COVER AND LAMP STRUCTURE - A cover and a lamp structure. The cover whose curvature has a light incident surface and a light outgoing surface, and includes a plurality of 3D micro-structures disposed thereon and arranged in the form of an array. When a light is emitted into the light outgoing surface from the light incident surface, the light emitting angle of the light outgoing surface is increased through the refraction of the 3D micro-structures, so that the occurrence of mura or spots due to uneven distribution of the light is avoid. | 09-27-2012 |
Chi-Wen Hsieh, Hsinchu City TW
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20140065832 | ENHANCED FINFET PROCESS OVERLAY MARK - An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin. | 03-06-2014 |
20140367869 | Enhanced FinFET Process Overlay Mark - An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin. | 12-18-2014 |
Chris Hsieh, Hsinchu City TW
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20090294886 | METHOD OF MAKING WAFER STRUCTURE FOR BACKSIDE ILLUMINATED COLOR IMAGE SENSOR - An integrated circuit device is provided. The integrated circuit device can include a substrate; a first radiation-sensing element disposed over a first portion of the substrate; and a second radiation-sensing element disposed over a second portion of the substrate. The first portion comprises a first radiation absorption characteristic, and the second portion comprises a second radiation absorption characteristic different from the first radiation absorption characteristic. | 12-03-2009 |
Chung-An Hsieh, Hsinchu City TW
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20090278607 | Power Supply Device For Driving An Amplifier - A power supply device for driving first and second amplifiers includes a first power generator, a second power generator, a charge pump and a control unit. The first power generator provides a first voltage for first power reception ends of the first and second amplifiers. The second power generator provides a second voltage. The charge pump is coupled between the second power generator and a second power reception end of the first amplifier and between the second power generator and a second power reception end of the second amplifier, and is used for generating a third voltage for the first and second amplifiers according to the second voltage. The control unit is coupled to the second power generator and is used for controlling the second power generator, so as to adjust the second voltage to make the third voltage equal to a multiple of the first voltage. | 11-12-2009 |
20090278608 | Power Supply Device for Driving an Amplifier - A power supply device for driving an amplifier includes a power generator for providing a first voltage for a first power reception end of the amplifier, a power conversion unit coupled to the power generator, for converting the first voltage into a second voltage, a charge pump coupled between the power conversion unit and a second power reception end of the amplifier, for generating a third voltage for the amplifier according to the second voltage, and a control unit coupled to the power conversion unit, for controlling the power conversion unit, so as to adjust the second voltage to make the third voltage equal to a specific multiple of the first voltage. | 11-12-2009 |
20110304396 | POWER AMPLIFIER AND PROCESSING DEVICE UTILIZING THE SAME - A processing device including a control unit and a power amplifier is disclosed. The control unit generates a plurality of control signals according to an input signal. The power amplifier includes a plurality of switches. The control signals control the switches to turn on or off such that a short through current does not occur in the power amplifier. | 12-15-2011 |
Chung-Hsuan Hsieh, Hsinchu City TW
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20090302825 | CURRENT SOURCE - A current source includes a node, a biasing circuit, a loading circuit and a current mirror. The node has a specified voltage. The biasing circuit biases the specified voltage to be a first reference voltage. The loading circuit provides an equivalent resistor across the node and a second reference voltage to generate a reference current. The loading circuit includes a resistor and a metal oxide semiconductor field effect transistor (MOSFET). The resistor has a first temperature coefficient. The transistor operating in a linear region is controlled by a control voltage to turn on and to form a transistor resistor coupled with the resistor in series. The transistor resistor has a second temperature coefficient, wherein a temperature coefficient of the equivalent resistor is relevant to the first and second temperature coefficients. The current mirror receives the reference current and provides a mirrored current of the reference current as the output current. | 12-10-2009 |
Chun-Hsing Hsieh, Hsinchu City TW
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20080198267 | Interlaced image processing method and apparatus - In an interlaced image processing method for processing fields generated by interlacing and including a plurality of rows of scan signals, the method includes: performing horizontal line detection on a current field so as to determine which of the rows of the scan signals is a horizontal line; according to the horizontal line detection result of the current field and a horizontal line detection result of a previous field, adjusting position of the horizontal line in the current field so as to approach position of a corresponding horizontal line in the previous field; and according to the result of position adjustment, re-sampling the current field. An interlaced image processing apparatus for implementing the method is also disclosed. | 08-21-2008 |
20100085486 | IMAGE PROCESSING APPARATUS AND METHOD - An image processing apparatus includes a pixel difference calculator, a summing unit, a determining unit, and an output unit. The pixel difference calculator receives a present image having first pixels and a previous image having second pixels, calculates pixel differences between corresponding first and second pixels, and outputs positive and negative pixel difference values. The summing unit obtains a first output value by adding up those of the positive pixel difference values and a second output value by adding up those of the negative pixel difference values. The determining unit determines a noise level of the present image from the first and second output values, and outputs a blended value. The output unit adds together weights of pixels at the same positions of the present and previous images according to the blended value to generate an output image. An image processing method is also disclosed. | 04-08-2010 |
20100092044 | Image Processing Apparatus and Method - An image processing apparatus includes: a pixel difference calculator for calculating a difference value between each first pixel of a previous image and a second pixel of a present image and at a position corresponding to said each first pixel, and outputting a plurality of pixel differences; a counter counting a number of positive pixel differences and a number of negative pixel differences in the pixel differences of a sampling window; a motion level determining unit calculating a motion level of a pixel in the sampling window according to the numbers of the positive and negative pixel differences; a blending value determining unit determining a blending value according to the motion level; and an output unit adding together weights of the present and previous images according to the blending value to generate and output an output image. An image processing method is also disclosed. | 04-15-2010 |
20100104202 | IMAGE PROCESSING APPARATUS AND METHOD - An image processing apparatus for processing a previous image having first pixels and a present image having second pixels. The image processing apparatus includes: a pixel difference calculating unit which calculates pixel differences between corresponding pairs of the first and second pixels, and outputs pixel difference values; an edge processing unit which detects and compares edge types of the first and second pixels, sums a number of the edge types that are the same, and outputs a sum value; a noise level processing unit which calculates a noise level of the present image according to the sum value and the pixel differences; a blending value determining unit which determines a blending value according to the noise level; and an output unit which adds weights of the present and previous images according to the blending value and outputs an output image. An image processing method is also disclosed. | 04-29-2010 |
20120082379 | Image Adjustment Method and Device - An image adjustment method includes the steps of: a) configuring a weight-value generator to receive first image data and specified data and to generate an adaptive weight value according to the first image data and the specified data; and b) configuring an image blender to receive the first image data and second image data, and to generate adjusted image data by blending the first image data and the second image data with reference to the adaptive weight value. The adaptive weight value has a magnitude that corresponds to a difference between the first image data and the specified data. | 04-05-2012 |
20120263374 | DEVICE AND METHOD FOR TRANSFORMING 2D IMAGES INTO 3D IMAGES - A device for transforming 2D images into 3D images includes a position calculation unit and an image processing block. The position calculation unit generates multiple start points corresponding to multiple pixel lines of a panel according to a display type of the panel. The image processing block reshapes multiple input enable signals into multiple output enable signals according to the start points. The pixel lines of the panel displays the output data signal as multiple image signals respectively according to the output enable signals. The image signals include multiple left-eye image signals and multiple right-eye image signals. | 10-18-2012 |
20130028507 | 2D to 3D IMAGE CONVERSION APPARATUS AND METHOD THEREOF - A 2D to 3D image conversion apparatus includes a data queue, a conversion unit and an offset calculation unit. The data queue receives and temporarily stores an input data value corresponding to a current pixel. The conversion unit outputs a current offset table corresponding to a current depth parameter of the current pixel. The current offset table includes (m+1) reference offsets corresponding to the current pixel and neighboring m pixels. The offset calculation unit selects one of the reference offsets corresponding to the current pixel in the current offset table and multiple previous offset tables as a data offset corresponding to the current pixel. The data queue selects and outputs an output data value corresponding to the current pixel according to an integer part of the data offset and the input data value. | 01-31-2013 |
20130188027 | IMAGE DEPTH GENERATION DEVICE AND METHOD THEREOF - An image depth generation device and method thereof is disclosed in the present invention. The device includes at least a processing circuit and at least a calculator. The processing circuit receives an input image and determines a visual distance of a pixel Pi according to a color of the pixel in the input image and at least a reference value to generate a depth offset of each pixel. The calculator is coupled to the processing circuit and uses the depth offset of each pixel and a predetermined depth to generate an output depth value of each pixel in the input image. | 07-25-2013 |
Chun-I Hsieh, Hsinchu City TW
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20090283856 | METHOD FOR FABRICATING A SEMICONDUCTOR CAPACITPR DEVICE - A method for fabricating a semiconductor capacitor includes a substrate having thereon a carbon electrode. A transitional barrier layer is then deposited on the carbon electrode layer. Thereafter, a metal oxide layer is deposited on the transitional barrier layer, which reacts with the underlying transitional barrier layer to form a metal oxy-nitride layer acting as a capacitor dielectric layer of the capacitor device. A top electrode layer is then formed on the metal oxy-nitride layer. | 11-19-2009 |
20090311878 | METHOD FOR DEPOSITING A DIELECTRIC MATERIAL - A depositing method for a dielectric material is provided, where the dielectric material has the first and the second primary elements, and a single precursor includes the first and the second primary elements. The depositing method includes pulsing the single precursor, purging a redundant part of the single precursor, pulsing an oxidant for oxidizing the single precursor, and purging a redundant part of the oxidant. | 12-17-2009 |
20100021626 | METHOD OF FABRICATING RRAM - A method of fabricating a RRAM includes: forming a bottom electrode; forming a first metal layer, a first metal oxide layer, and a second metal layer on the bottom electrode in sequence; performing an RTO process followed by a top electrode formation; oxidizing the first metal layer to a second metal oxide layer comprising a second oxygen content; and oxidizing the second metal layer to a third metal oxide layer comprising a third oxygen content; wherein the first metal oxide layer has a first oxygen content after the RTO process is performed, the third oxygen content being higher than the first oxygen content and the first oxygen content being higher than the second oxygen content. | 01-28-2010 |
20100072449 | RRAM WITH IMPROVED RESISTANCE TRANSFORMATION CHARACTERISTIC AND METHOD OF MAKING THE SAME - A method for fabricating an RRAM is provided. First, a bottom electrode is formed. A resistive layer is formed on the bottom electrode. A top electrode is then formed on the resistive layer, wherein the top electrode is selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO). Finally, the top electrode is irradiated with UV light. | 03-25-2010 |
20100181545 | NON-VOLATILE MEMORY CELL AND FABRICATION METHOD THEREOF - A non-volatile memory cell and the fabrication method thereof are provided. The non-volatile memory cell comprises a top electrode, a bottom electrode and an oxide layer disposed between the top electrode and the bottom electrode. The oxide layer comprises a relatively low oxygen content layer adjacent to the bottom electrode, a relatively high oxygen content layer adjacent to the top electrode, and a transition layer disposed between the relatively high and the relatively low oxygen content layers. The transition layer has an oxygen concentration within a range between those of the relatively high and the relatively low oxygen content layers. | 07-22-2010 |
20100193762 | NON-VOLATILE MEMORY CELL AND FABRICATION METHOD THEREOF - A non-volatile memory cell and a fabrication method thereof are provided. The non-volatile memory cell includes an anode; a cathode having a surface facing the anode; a specific structure disposed on the surface; and an ion conductor disposed among the anode, the cathode and the specific structure, wherein the specific structure is one of a bulging area on the surface of the cathode and an insulating layer with an opening. | 08-05-2010 |
Dung-Yian Hsieh, Hsinchu City TW
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20120239178 | DEVICE PERFORMANCE PARMETER TUNING METHOD AND SYSTEM - A method comprises computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests. Each regression model outputs a wafer yield measure as a function of a plurality of device performance variables. For each failure bin, sensitivity of the wafer yield measure to each of the plurality of device performance variables is determined, and the device performance variables are ranked with respect to sensitivity of the wafer yield measure. A subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other are selected. The wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables are combined, to provide a combined wafer yield measure. At least one new process parameter value is selected to effect a change in the one device performance variable, based on the combined wafer yield measure. The at least one new process parameter value is to be used to process at least one additional wafer. | 09-20-2012 |
E. R. Hsieh, Hsinchu City TW
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20120126197 | Structure and process of basic complementary logic gate made by junctionless transistors - The present invention discloses a structure and process of basic complementary logic gate made by junctionless transistors. Junctionless N-channel transistor(s) and junctionless P-channel transistor(s) are formed on a semiconductor wafer, a conducting contact structure is used to connect the transistors to form a basic complementary logic gate(s) such as inverter, NAND, NOR, etc. | 05-24-2012 |
Ho-Ting Hsieh, Hsinchu City TW
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20130047173 | OPTICAL DISK DRIVE - An optical disk drive including a housing, a top cover, a spindle motor and a supporting element is provided. The housing has an accommodating space. The top cover covers the accommodating space. The spindle motor is disposed within the accommodating space and has a shaft. The supporting element is disposed between an end of the shaft and the top cover. When the top cover is deformed, the shaft props up the top cover through the supporting element. | 02-21-2013 |
20130125148 | OPTICAL DISC DRIVE - An optical disc drive including a case, a tray, a traverse, a plurality of washers, a plurality of fastening elements and a plurality of adjustment elements is provided. The tray is suitable for carrying an optical disc and includes a plurality of hollow alignment pillars. The traverse is disposed on the tray and includes a plurality of alignment holes for containing the corresponding hollow alignment pillars. Each washer is disposed in each of the alignment holes and leans between each of the alignment holes and each of the hollow alignment pillars. The fastening elements lock the traverse onto the tray. Each adjustment element leans between each of the washers and the tray, and bears an engagement pressure. | 05-16-2013 |
Hsiao Hui Hsieh, Hsinchu City TW
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20100231254 | METHOD FOR CONFIGURING COMBINATIONAL SWITCHING MATRIX AND TESTING SYSTEM FOR SEMICONDUCTOR DEVICES USING THE SAME - A method for configuring a combinational switching matrix comprises the steps of setting a first switching module and a second switching module, coupling at least one of the output ports of the first switching module with at least one of the input ports of the second switching module to form the combinational switching matrix, building a connection mapping table based on the coupling relationship between the output port of the first switching module and the input port of the second switching module, and displaying a channel switching interface showing the input terminals, the output terminals, and the on/off states of the virtual switching devices of the combinational switching matrix. | 09-16-2010 |
Hsieh-Shen Hsieh, Hsinchu City TW
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20130139593 | INERTIAL SENSOR WITH STRESS ISOLATION STRUCTURE - An inertial sensor with stress isolation structure includes a substrate, a suspension bridge, a guard ring and an electromechanical conversion mechanism. The substrate has a housing trough and an annular wall surrounding the housing trough. The suspension bridge is located in the housing trough and connected to the annular wall. The guard ring is connected to the suspension bridge and suspended in the housing trough. The suspension bridge is located between the substrate and guard ring. The electromechanical conversion mechanism is connected to and surrounded by the guard ring. Through the guard ring, interferences of applied forces to the electromechanical conversion mechanism can be reduced, precision of the inertial sensor can be improved, and performance impact caused by succeeding element package process can also be reduced. Thus package, test and calibration processes can be simplified to lower production cost. | 06-06-2013 |
Hsien-Cheng Hsieh, Hsinchu City TW
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20100097042 | LOW DROPOUT REGULATOR HAVING A CURRENT-LIMITING MECHANISM - A low dropout regulator having a current-limiting mechanism is disclosed. The regulator includes a sensing resistor, an error amplifier, and first through fourth transistors. The first transistor generates an output voltage according to an input voltage and a current control signal. The sensing resistor is employed to generate a sense voltage based on the current flowing through the fourth transistor so as to control the second transistor for generating an internal voltage. The third transistor controls the current control signal based on a voltage divided from the internal voltage. The channel width/length ratio of the first transistor is greater than that of the fourth transistor. When the third transistor is turned off, the error amplifier adjusts the voltage of the current control signal according to a voltage divided from the output voltage; when the third transistor is turned on, the voltage of the current control signal is not adjusted. | 04-22-2010 |
Hsin-Ju Hsieh, Hsinchu City TW
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20100330631 | Cis-aconitate Decarboxylase Mutants Having Improved Enzymatic Activity - Cis-aconitate decarboxylase mutants having one or more mutations in a C-terminal region as compared with a wild-type cis-aconitate decarboxylase of | 12-30-2010 |
20100330632 | Cis-aconitate Decarboxylase Mutants Having Improved Enzymatic Activity - Cis-aconitate decarboxylase mutants having one or more mutations in a C-terminal region as compared with a wild-type cis-aconitate decarboxylase of | 12-30-2010 |
Hsin-Ta Hsieh, Hsinchu City TW
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20130144425 | FIVE-AXIS FLANK MILLING SYSTEM FOR MACHINING CURVED SURFACE AND A TOOLPATH PLANNING METHOD THEREOF - The present invention discloses a five-axis flank milling system for machining a curved surface and a tool-path planning method. The method generates a tool path comprising a series of cutter locations by optimization with minimizing machining errors. The tool path planning method includes a reciprocating tool path planning method and a multi-pass tool path planning method. The reciprocating tool path planning method eliminates the “forward only” limitation. The tool is allowed to move backward in certain regions, producing smaller machining errors compared with forward only cutter movement. Furthermore, the multi-pass tool path planning method computes various tool paths applied to finish milling multiple times. Each path can be chosen to be generated by minimizing undercut error, overcut error, or the total machining error. The machining errors are reduced in a progressive manner, resulting in better machining quality than single pass tool path. | 06-06-2013 |
Hsiu-Chun Hsieh, Hsinchu City TW
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20120305910 | HYBRID THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF AND DISPLAY PANEL HAVING THE SAME - A hybrid thin film transistor includes a first thin film transistor and a second thin film transistor. The first thin film transistor includes a first gate, a first source, a first drain and a first semiconductor layer disposed between the first gate, the first source and the first drain, and the first semiconductor layer includes a crystallized silicon layer. The second thin film transistor includes a second gate, a second source, a second drain and a second semiconductor layer disposed between the second gate, the second source and the second drain, and the second semiconductor layer includes a metal oxide semiconductor layer. | 12-06-2012 |
Hui-Yen Hsieh, Hsinchu City TW
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20090195207 | Servo Control Circuit - The present invention discloses a servo control circuit comprising: a first node for receiving a control voltage; a second node for receiving a feedback voltage; an operational amplifier controlling a current on a path according to the voltages at the first and second nodes, the path including an internal voltage node thereon; an analog to digital converter (ADC) for converting the voltage at the internal voltage node to a digital signal; and a control logic circuit for generating a servo control signal according to the digital signal. | 08-06-2009 |
20110199029 | Bi-Direction Driver IC and Method for Bi-Directionally Driving an Object - The present invention discloses a bi-direction driver IC and a method for bi-directionally driving an object. The method comprises: providing a first and a second integrated circuit (IC) chips, coupled with an object to be driven, wherein each of the first and second IC chips is capable of single-directionally driving the object; providing a reverse current path in each of the first and second IC chips; driving the object in a first direction by the first IC chip, wherein current flows through the reverse current path in the second IC chip; and driving the object in a second direction by the second IC chip, wherein current flows through the reverse current path in the first IC chip. | 08-18-2011 |
Hung Chang Hsieh, Hsinchu City TW
Patent application number | Description | Published |
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20100279234 | DOUBLE PATTERNING METHOD USING METALLIC COMPOUND MASK LAYER - A hard mask layer and a developable bottom anti-reflective coating (dBARC) layer are formed over a dielectric layer of a substrate. A first photosensitive layer is formed above the dBARC layer, exposed, and developed to form a first pattern. The dBARC layer is developed. The first pattern is etched into the hard mask layer to form a first pattern of openings in the hard mask layer. Following removal of the first photosensitive layer, a second photosensitive layer is formed within the first pattern of openings. The second photosensitive layer is exposed and developed to form a second pattern. The dBARC layer is developed. The second pattern is etched into the hard mask layer to form a second pattern of openings in the hard mask layer. Following the removal of the second photosensitive layer and the dBARC layer, the first and the second patterns are etched into the dielectric layer. | 11-04-2010 |
20120266810 | PLANARIZATION SYSTEM FOR HIGH WAFER TOPOGRAPHY - A system for planarizing a semiconductor device includes a holder component for holding the substrate. The substrate has at least one opening therein, and each opening defines a lower portion and an upper portion. A resist applicator applies a layer of resist over the substrate, such that the resist layer covers the lower and upper portions. An etching component etches back the resist layer to expose the upper portion of the at least one opening. The resist applicator and the etching component repeat the steps of applying and etching, respectively, to remove a predetermined amount below the upper portion. A deposition component deposits an insulating layer over the substrate. A planarizing component planarizes the insulating layer until the upper portion of the at least one opening is exposed. | 10-25-2012 |
20120270398 | PLANARIZATION METHOD FOR HIGH WAFER TOPOGRAPHY - A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed. | 10-25-2012 |
20120309197 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES - A method of forming a semiconductor structure includes forming an opening in a substrate. A dielectric layer is formed and substantially conformal to the opening. A sacrificial structure is formed within the opening, covering a portion of the dielectric layer. A portion of the dielectric layer is removed by using the sacrificial structure as an etch mask layer. The sacrificial structure is removed. | 12-06-2012 |
20130154100 | METHOD OF PATTERNING A SEMICONDUCTOR DEVICE HAVING IMPROVED SPACING AND SHAPE CONTROL AND A SEMICONDUCTOR DEVICE - A pattern on a semiconductor substrate is formed using two separate etching processes. The first etching process removes a portion of an intermediate layer above an active region of the substrate. The second etching process exposes a portion of the active region of the substrate. A semiconductor device formed using the patterning method has a decreased mask error enhancement factor and increased critical dimension uniformity than the prior art. | 06-20-2013 |
20130273740 | FILM PORTION AT WAFER EDGE - A film layer on a substrate of the wafer is patterned to form a first plurality of areas of the film layer and a second plurality of areas of the film layer. The first plurality of areas of the film layer is removed. The second plurality of areas of the film layer is kept on the substrate. A first portion of the film layer is kept on the substrate. A first edge of the first portion of the film layer is substantially near an edge of the wafer. The first portion of the film layer defines a boundary for the wafer. | 10-17-2013 |
20140035149 | METHOD OF PATTERNING A SEMICONDUCTOR DEVICE HAVING IMPROVED SPACING AND SHAPE CONTROL AND A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a first active region in the semiconductor substrate, and a second active region in the semiconductor substrate. The semiconductor device further includes a first conductive line over the semiconductor substrate electrically connected to the first active region and having a first end face adjacent to the second active region, and the first end face having an image log slope of greater than 15 μm | 02-06-2014 |
20140272704 | THICKENING PHASE FOR SPIN COATING PROCESS - Among other things, one or more techniques and systems for performing a spin coating process associated with a wafer and for controlling thickness of a photoresist during the spin coating process are provided. In particular, a thickening phase is performed during the spin coating process in order to increase a thickness of the photoresist. For example, air temperature of down flow air, flow speed of the down flow air, and heat temperature of heat supplied towards the wafer are increased during the thickening phase. The increase in down flow air and heat increase a vaporization factor of the photoresist, which results in an increase in viscosity and thickness of the photoresist. In this way, the wafer can be rotated at relatively lower speeds, while still attaining a desired thickness. Lowering rotational speed of wafers allows for relatively larger wafers to be stably rotated. | 09-18-2014 |
20140272715 | Lithography Process on High Topology Features - A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist. | 09-18-2014 |
Hung-Wen Hsieh, Hsinchu City TW
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20130151752 | BIT-LEVEL MEMORY CONTROLLER AND A METHOD THEREOF - The present invention is directed to a bit-level memory controller and method adaptable to managing defect bits of a non-volatile memory. A bad column management (BCM) unit retrieves a bit-level mapping table, in which defect bits are respectively marked, based on which the BCM unit constructs a bit-level script (BLS) that contains a plurality of entries denoting defect-bit groups respectively. An internal buffer is configured to store data managed by the BCM unit according to the BLS. | 06-13-2013 |
I-Lin Hsieh, Hsinchu City TW
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20110009060 | Systems and Methods for Reducing Interference Between a Plurality of Wireless Communications Modules - A wireless communications system is provided with a first wireless communications and a second wireless communications. The first wireless communications module transmits or receives a first wireless signal in a first frequency band selected from a first frequency range. The second wireless communications module transmits or receives a second wireless signal in a second frequency band selected from a second frequency range, and adjusts a transmission power of the second wireless signal in response to that a frequency offset between the first frequency band and the second frequency band falls within a predetermined range. | 01-13-2011 |
20110009074 | SYSTEMS AND METHODS FOR COEXISTENCE BETWEEN PLURALITY OF WIRELESS COMMUNICATIONS MODULES SHARING SINGLE ANTENNA - A system for the coexistence between a plurality of wireless communications modules sharing single antenna is provided. A wireless communications chipset includes a first wireless communications module configured to transmit or receive first wireless communications signals, and a second wireless communications module configured to transmit or receive second wireless communications signals. A path selection circuit is configured to connect the first wireless communications module to the antenna via a first transceiving path or a second transceiving path for transmitting and receiving the first wireless signals according to transceiving statuses of the first wireless signals and the second wireless signals. | 01-13-2011 |
20110310741 | APPARATUSES AND METHODS FOR COORDINATION BETWEEN PLURALITY OF CO-LOCATED WIRELESS COMMUNICATION MODULES VIA ONE WIRE - The invention provides a mobile communication device having a Packet Traffic Arbitrator (PTA) module and a first wireless communication module, coupled to the PTA module via only one wire and configured to perform a first wireless transceiving. The first wireless communication module sends a first request indicating a remaining period of time for a second wireless communication module to use to the PTA module via the wire, and receives, via the wire, a first response indicating whether the first request has been accepted. | 12-22-2011 |
20140241406 | WIRELESS COMMUNICATIONS SYSTEM PERFORMING TRANSMISSION AND RECEPTION ACCORDING TO OPERATIONAL STATES OF CO-LOCATED INTERFACE APPARATUS AND RELATED WIRELESS COMMUNICATIONS METHOD THERE OF - A wireless communications system co-located with an interface apparatus includes a radio subsystem. The radio subsystem includes a transmission circuit arranged for performing a radio transmission, and a reception circuit arranged for performing a radio reception when the interface apparatus operates in a first operational state. The interface apparatus operates in one of a plurality of operational states including the first operational state and a second operational state, and a power consumption of the interface apparatus in the first operational state is lower than a power consumption of the interface apparatus in the second operational state. | 08-28-2014 |
20140254634 | SYSTEMS AND METHODS FOR REDUCING INTERFERENCE BETWEEN A PLURALITY OF WIRELESS COMMUNICATIONS MODULES - A wireless communications includes a first wireless communications and a second wireless communications. The first wireless communications module transmits or receives a first wireless signal in a first frequency band selected from a first frequency range. The second wireless communications module transmits or receives a second wireless signal in a second frequency band selected from a second frequency range, and adjusts a transmission power of the second wireless signal in response to that a frequency offset between the first frequency band and the second frequency band falls within a predetermined range. The first wireless communications module is further configured to determine an in-band range in the overlapping part of the first and second frequency ranges, and a transmission power of the second wireless signal is adjusted in response to a frequency offset between the first frequency band and the second frequency band. | 09-11-2014 |
20140357288 | APPARATUSES AND METHODS FOR COORDINATION BETWEEN PLURALITY OF CO-LOCATED WIRELESS COMMUNICATION MODULES VIA ONE WIRE - A wireless communication device has a first wireless communication module coupled to a second wireless communication module via only one wire. The first wireless communication module is configured to performing a first wireless transceiving and to send a first request to the second wireless communication module indicating a remaining period of time to perform a second wireless transceiving, during which the first wireless communication module is not required to perform wireless transceiving. The second wireless communication module is configured to perform a second wireless transceiving, the second wireless communication module further configured to send a first response to the first request by indicating acceptance of the request if a status of the second wireless communication module is in an active mode, else by indicating that the first request is not accepted if the status of the second wireless communication module is in a sleep mode. | 12-04-2014 |
Jerwei Hsieh, Hsinchu City TW
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20130205899 | Combo Transducer and Combo Transducer Package - A combo transducer includes a base, a proof mass, a membrane unit and a plurality of transducing components. The base is formed with an aperture. The proof mass is disposed in the aperture and has a surface that is formed with a cavity. The membrane unit includes a supporting part connected to the base, a covering part disposed to cover the surface of the proof mass, and a resilient linking part interconnecting the supporting part and the covering part such that the proof mass is movable relative to the base. The transducing components are disposed at the membrane unit. At least one of the transducing components is disposed at the covering part and is registered with the cavity. | 08-15-2013 |
20130285248 | Package Structure and Substrate Bonding Method - A substrate bonding method comprises the following steps. Firstly, a first substrate and a second substrate are provided, wherein a surface of the first substrate is covered by a first Ag layer and a surface of the second substrate is covered by a second Ag layer and a metallic layer from bottom to top, wherein the metallic layer comprises a first Sn layer. Secondly, a bonding process is performed by aligning the first and second substrates followed by bringing the metallic layer into contact with the first Ag layer followed by applying a load while heating to a predetermined temperature in order to form Ag | 10-31-2013 |
Jui Hai Hsieh, Hsinchu City TW
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20100122657 | Electrode, Chemical Vapor Deposition Apparatus Including the Electrode and Method of Making - The present disclosure is directed to a chemical vapor deposition apparatus. The apparatus comprises a chamber having a gas inlet and a gas outlet. A first electrode is at least partially positioned in the chamber. The first electrode comprises an electrically conductive first portion and an electrically conductive second portion, the first portion being attached to the second portion by a first TIG weld bead. A second electrode is at least partially positioned in the chamber. The second electrode comprises an electrically conductive third portion and an electrically conductive fourth portion, the third portion being attached to the fourth portion by a second TIG weld bead. An electrode and a method of making the electrode are also disclosed. | 05-20-2010 |
20100147219 | HIGH TEMPERATURE AND HIGH VOLTAGE ELECTRODE ASSEMBLY DESIGN - A chemical vapor deposition apparatus is disclosed. The chemical vapor deposition apparatus comprises a chamber having a base plate, a chamber wall, a gas inlet and a gas outlet. The base plate has holes therethrough. A plurality of electrodes extend through the holes of the base plate. The plurality of electrodes are capable of being attached to a power source. At least two of the plurality of electrodes are capable of being electrically coupled to a silicon rod positioned in the chamber. An electrical isolation bushing can be positioned between each of the plurality of electrodes and the base plate. The electrical isolation bushing comprises a sleeve portion surrounding a portion of the electrodes that extends through the base plate and a collar portion surrounding the holes at a surface of the base plate. In some instances, the collar portion can comprise a different material than the sleeve portion. In some instances, an isolation layer can be employed in addition to the isolation bushing, the isolation layer surrounding the holes at the surface of the base plate. In some instances, the collar portion and the sleeve portion are both ceramic. | 06-17-2010 |
Jui Hai (harry) Hsieh, Hsinchu City TW
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20100101494 | ELECTRODE AND CHEMICAL VAPOR DEPOSITION APPARATUS EMPLOYING THE ELECTRODE - A chemical vapor deposition apparatus is disclosed. The chemical vapor deposition apparatus comprises a chamber having a base plate, a chamber wall, a gas inlet, a gas outlet and a plurality of electrodes each comprising an electrode body and an electrode cap removably attached to the electrode body. The electrode body can be positioned through the base plate. The cap can be positioned inside the chamber. An electrical isolation layer is positioned between the electrode and the base plate. The plurality of electrodes are capable of being attached to a power source. At least two of the plurality of electrodes are capable of being electrically coupled to a silicon rod positioned in the chamber. | 04-29-2010 |
Jung-Yu Hsieh, Hsinchu City TW
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20110073937 | Method for Fabricating a Charge Trapping Memory Device - A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer. | 03-31-2011 |
20130001667 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MAKING THE SAME - A method for making a nonvolatile memory device includes the following steps. A conductive structure is formed, wherein the conductive structure has a first top portion. The first top portion is converted into a second top portion having a domed surface. | 01-03-2013 |
Jung-Yuan Hsieh, Hsinchu City TW
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20100081273 | METHOD FOR FABRICATING CONDUCTIVE PATTERN - A method for fabricating a conductive pattern including following steps is provided. A first conductive layer is formed on a substrate. A patterned hard mask layer is formed on the first conductive layer. A portion of the first conductive layer is removed to expose a portion of the substrate by using the patterned hard mask layer as a mask. A dielectric layer covering the patterned hard mask layer is formed on the substrate. A portion of the dielectric layer is removed to expose the patterned hard mask layer. The patterned hard mask layer is removed to form an opening in the dielectric layer. A second conductive layer is formed in the opening. | 04-01-2010 |
Junwei Hsieh, Hsinchu City TW
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20100278391 | Apparatus for behavior analysis and method thereof - In the present invention, an apparatus for behavior analysis and method thereof is provided. In this apparatus, each behavior is analyzed and has its corresponding posture sequence through a triangulation-based method of triangulating the different triangle meshes. The two important posture features, the skeleton feature and the centroid context, are extracted and complementary to each other. The outstanding ability of posture classification can generate a set of key postures for coding a behavior sequence to a set of symbols. Then, based on the string representation, a novel string matching scheme is proposed to analyze different human behaviors even though they have different scaling changes. The proposed method of the present invention has been proved robust, accurate, and powerful especially in human behavior analysis. | 11-04-2010 |
Jun-Wei Hsieh, Hsinchu City TW
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20120106802 | VEHICLE LICENSE PLATE RECOGNITION METHOD AND SYSTEM THEREOF - A vehicle license plate recognition method and a system thereof are disclosed. A region where a vehicle license plate image exists is detected according to the edge densities of an input image and a vehicle license plate specification. A text area of the vehicle license plate image is divided into a plurality of character images. The character images are binarized to obtain a plurality of binarized character images. A plurality of characters is recognized from the binarized character images. The characters are recombined to form a character string. The abovementioned steps are repeated to obtain a new character string from another image of the same vehicle, which is captured at a next time point. The character string is compared with the new character string character by character to obtain a comparison result for verifying reliability of recognition through a voting technique. | 05-03-2012 |
Kun-Hung Hsieh, Hsinchu City TW
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20080247284 | RECORDING APPARATUS FOR OPTICAL DISK DRIVE - A recording method for an optical disk drive is implemented as follows. First, at least one of the level of the focusing error signal, the level of the tracking error signal, a wobble synchronization pattern loss, the error rate of demodulating a wobble signal, the frequency of buffer under-run occurrence, the temperature of the drive, the wobble jitter and the level of write power is detected. If at least one detected value exceeds the preset value, the recording will be ceased. Then, the rotation speed of the optical disk drive is decreased, and the recording is resumed with the decreased rotation speed. If at least one of the temperature of the drive, the wobble jitter and the estimated write power exceeds the reset value before recording starts, the rotation speed of the optical disk drive is decreased before recording. | 10-09-2008 |
20090080322 | RECORDING METHOD AND APPARATUS FOR OPTICAL DISK DRIVE - A recording method for an optical disk drive is implemented as follows. First, at least one of the level of the focusing error signal, the level of the tracking error signal, a wobble synchronization pattern loss, the error rate of demodulating a wobble signal and the frequency of buffer under-run occurrence is detected. If at least one detected value exceeds the preset value, the recording will be ceased. Then, the rotation speed of the optical disk drive is decreased, and the recording is resumed with the decreased rotation speed. | 03-26-2009 |
Meng-Han Hsieh, Hsinchu City TW
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20090050904 | LIGHT EMITTING DIODE CIRCUIT - A light emitting diode circuit includes a chip and a light emitting diode. The chip includes a current control unit that is used for controlling a driving current flowing through a path. The light emitting diode is positioned outside of the chip and is coupled to the path. The light emitting diode generates a light source according to the driving current. The light emitting diode circuit can directly control the current value of a driving current flowing through the light emitting diode. In this way, the circuit design is simplified and the production cost of the electronic product is reduced. | 02-26-2009 |
20090190631 | METHOD FOR GENERATING A SPREAD SPECTRUM CLOCK AND APPARATUS THEREOF - A method for generating a spread spectrum clock includes the steps of providing a reference clock having a reference period; generating a plurality of output clocks respectively having different phases according to the reference clock; generating a first/second control signal according to the reference clock and a spread spectrum clock and starting a first/second duration accordingly; during the first/second duration, outputting a first/second selecting signal representing a first/second predetermined sequence according to the first/second control signal, wherein the second predetermined sequence is a substantial reversed sequence of the first predetermined sequence; and during the first/second duration, sequentially outputting some or all of the output clocks as the spread spectrum clock according to the first/second predetermined sequence. | 07-30-2009 |
20090198754 | Order adaptive finite impulse response filter and operating method thereof - A device for allocating a number of taps of a designated finite impulse response filter is disclosed. The device comprises a plurality of designated finite impulse response filters having fixed number of taps, a plurality of allocation finite impulse response filters having fixed number of taps, a control unit and an estimate unit. Depending on intensities of responses to interferences, at least one of the allocation FIR filters may be coupled in series to any one of the designated finite impulse response filters, thereby to provide a signal having excellent quality. | 08-06-2009 |
Meng-Wei Hsieh, Hsinchu City TW
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20130161739 | DUMMY GATE FOR A HIGH VOLTAGE TRANSISTOR DEVICE - A semiconductor device and methods for forming the same are provided. The semiconductor device includes a first doped region and a second, oppositely doped, region both formed in a substrate, a first gate formed overlying a portion of the first doped region and a portion of the second doped region, two or more second gates formed over the substrate overlying a different portion of the second doped region, one or more third doped regions in the second doped region disposed only between the two or more second gates such that the third doped region and the second doped region having opposite conductivity types, a source region in the first doped region, and a drain region in the second doped region disposed across the second gates from the first gate. | 06-27-2013 |
20140264618 | ISOLATION STRUCTURE - A structure comprises a p-type substrate, a deep n-type well and a deep p-type well. The deep n-type well is adjacent to the p-type substrate and has a first conductive path to a first terminal. The deep p-type well is in the deep n-type well, is separated from the p-type substrate by the deep n-type well, and has a second conductive path to a second terminal. A first n-type well is over the deep p-type well. A first p-type well is over the deep p-type well. | 09-18-2014 |
Min-Hsun Hsieh, Hsinchu City TW
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20090146049 | OPTOELECTRONIC DEVICE ASSEMBLY - An embodiment of present invention discloses an optoelectronic device package including a first auxiliary energy receiver having a first energy inlet and a side wall for substantially directing energy far away from the first energy inlet; an optical element optically coupled to the first auxiliary energy receiver and having a recess facing the first energy inlet; and an optoelectronic device optically coupled to the optical element and receiving the energy from the first energy inlet. | 06-11-2009 |
20090302334 | Light-emitting element array - A light-emitting element array includes a conductive substrate; an adhesive layer disposed on the conductive substrate; a first epitaxial light-emitting stack layers disposed on the adhesive layer, the first epitaxial light-emitting stack layers including a first p-contact and an first n-contact, wherein the first p-contact and the first n-contact are disposed on the same side of the first epitaxial light-emitting stack layer; and a second epitaxial light-emitting stack layers disposed on the adhesive layer including a second p-contact and an second n-contact, wherein the second p-contact and the second n-contact are disposed on the opposite side of the epitaxial light-emitting stack layer; wherein the first epitaxial light-emitting stack layers and the second epitaxial light-emitting stack layers are electrically connected in anti-parallel. | 12-10-2009 |
20100213493 | LIGHT-EMITTING DEVICE - A light-emitting device including: a light-emitting stacked layer having first conductivity type semiconductor layer, a light-emitting layer formed on the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer formed on the light-emitting layer, wherein the upper surface of the second conductivity type semiconductor layer is a textured surface; a first planarization layer formed on a first partial of the upper surface of the second conductivity type semiconductor layer; a first transparent conductive oxide layer formed on the first planarization layer and a second partial of the second conductivity type semiconductor layer, including a first portion in contact with the first planarization layer and a second portion having a first plurality of cavities in contact with the second conductivity type semiconductor layer; and a first electrode formed on the first portion of the first transparent conductive oxide layer. | 08-26-2010 |
20100308355 | LIGHT-EMITTING DEVICE HAVING A THINNED STRUCTURE AND THE MANUFACTURING METHOD THEREOF - A semiconductor light-emitting device having a thinned structure comprises a thinned structure formed between a semiconductor light-emitting structure and a carrier. The manufacturing method comprises the steps of forming a semiconductor light-emitting structure above a substrate; attaching the semiconductor light-emitting structure to a support; thinning the substrate to form a thinned structure; forming or attaching a carrier to the thinned substrate; and removing the support. | 12-09-2010 |
20100314657 | OPTOELECTRONIC DEVICE - A optoelectronic device comprises a semiconductor stack layer; a first transparent conductive oxide (abbreviate as “TCO” hereinafter) layer located on the semiconductor stack layer, wherein the first TCO layer has at least one opening; and a second TCO layer covering the first TCO layer, wherein the second TCO layer is filled into the opening of the first TCO layer and contacted with the semiconductor stack layer, and one of the first TCO layer and the second TCO layer forms an ohmic contact with the semiconductor stack layer. | 12-16-2010 |
20110089444 | LIGHT-EMITTING ELEMENT - A light emitting element includes a carrier, a conductive connecting structure disposed on the carrier, an epitaxial stack structure including at least a first lighting stack and a second lighting stack disposed on the conductive connecting structure, an insulation section disposed between the epitaxial stack structure and the conductive connecting structure, and at least a metal line laid on the surface of the light emitting element, wherein the first light emitting stack further includes two electrodes having different polarity formed thereon; the second lighting stack is electrically connected to the conductive connecting structure at the bottom thereof and includes an electrode formed thereon. The insulation section is disposed below the first lighting stack to make the first lighting stack be insulated from the conductive connecting structure. The metal lines and the conductive connecting structure are electrically connected to each of the lighting stacks in parallel connection or series connection. | 04-21-2011 |
20110108879 | LIGHT-EMITTING DEVICE - A light-emitting device comprising a semiconductor light-emitting stack, comprising a light emitting area; an electrode formed on the semiconductor light-emitting stack, wherein the electrode comprises a current injected portion and an extension portion; a current blocking structure formed between the current injected portion and the semiconductor light-emitting stack, and formed between a first part of the extension portion and the semiconductor light-emitting stack; and an electrical contact structure formed between a second part of the extension portion and the semiconductor light-emitting stack. | 05-12-2011 |
20120012867 | MULTI-DIMENSIONAL LIGHT-EMITTING DEVICE - The present application provides a multi-dimensional light-emitting device electrically connected to a power supply system. The multi-dimensional light-emitting device comprises a substrate, a blue light-emitting diode array and one or more phosphor layers. The blue light-emitting diode array, disposed on the substrate, comprises a plurality of blue light-emitting diode chips which are electrically connected. The multi-dimensional light-emitting device comprises a central area and a plurality of peripheral areas, which are arranged around the central area. The phosphor layer covers the central area. When the power supply system provides a high voltage, the central area and the peripheral areas of the multi-dimensional light-emitting device provide a first light and a plurality of second lights, respectively. The first light and the second lights are blended into a mixed light. | 01-19-2012 |
20120104455 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optoelectronic device includes a substrate and a first transition stack formed on the substrate including at least a first transition layer formed on the substrate and having at least one hollow component formed inside the first transition layer, and a second transition layer wherein the second transition layer is an unintentional doped layer or an undoped layer formed on the first transition layer. | 05-03-2012 |
20120231560 | LIGHT-EMITTING DEVICE HAVING A THINNED STRUCTURE AND THE MANUFACTURING METHOD THEREOF - A semiconductor light-emitting device having a thinned structure comprises a thinned structure formed between a semiconductor light-emitting structure and a carrier. The manufacturing method comprises the steps of forming a semiconductor light-emitting structure above a substrate; attaching the semiconductor light-emitting structure to a support; thinning the substrate to form a thinned structure; forming or attaching a carrier to the thinned substrate; and removing the support. | 09-13-2012 |
20120326185 | LIGHT EMITTING DEVICE - A light emitting device including a carrying element having two electric conductors connectable to a power source, a light emitting element disposed on the carrying element and electrically connected to the two electric conductors, and at least one correction element electrically connected to the light emitting element, wherein the light emitting element is adapted to provide a light source upon connection of the two electric conductors with the power source, and the at least one correction element allows the light emitting element to have functions of temperature compensation, voltage correction, or surge absorption. | 12-27-2012 |
20130001624 | LIGHT-EMITTING DEVICE - A light-emitting device includes a semiconductor light-emitting stack; a current injected portion formed on the semiconductor light-emitting stack; an extension portion having a first branch radiating from the current injected portion and having a first width, and a first length greater than the first width, and a second branch extending from the first branch and having a second width larger than the first width, and a second length greater than the second width; and an electrical contact structure between the second branch and the semiconductor light-emitting stack. | 01-03-2013 |
20130029440 | METHOD FOR FABRICATING SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device is disclosed. The semiconductor light-emitting device comprises a multilayer epitaxial structure disposed on a substrate. The substrate has a predetermined lattice direction perpendicular to an upper surface thereof, wherein the predetermined lattice direction is angled toward [0 | 01-31-2013 |
20130033168 | WAVELENGTH CONVERSION STRUCTURE, MANUFACTURING METHODS THEREOF, AND LIGHTING EMITTING DEVICE INCLUDING THE WAVELENGTH CONVERSION STRUCTURE - A wavelength conversion structure comprises a phosphor layer comprising a first part and a second part formed on the first part, wherein the first part and the second part have a plurality of pores, a first material layer formed in the plurality of pores of the first part, a second material layer formed in the plurality of pores of the second part and a plurality of phosphor particles, wherein the plurality of phosphor particles is distributed in the first material layer and the second material layer. | 02-07-2013 |
20130181245 | LIGHT-EMITTING DEVICE - A light-emitting device including: a light-emitting stacked layer having first conductivity type semiconductor layer, a light-emitting layer formed on the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer formed on the light-emitting layer, wherein the upper surface of the second conductivity type semiconductor layer is a textured surface; a first planarization layer formed on a first part of the upper surface of the second conductivity type semiconductor layer; a first transparent conductive oxide layer formed on the first planarization layer and a second part of the second conductivity type semiconductor layer, including a first portion in contact with the first planarization layer and a second portion having a first plurality of cavities in contact with the second conductivity type semiconductor layer;; and a first electrode formed on the first portion of the first transparent conductive oxide layer. | 07-18-2013 |
20130207135 | LIGHT EMITTING ELEMENT - A light emitting element is provided in this application, including a carrier; a conductive connecting structure disposed on the carrier and including a transparent conductive connecting layer; and an epitaxial stack structure disposed on the conductive connecting structure and including a plurality of electrically connected epitaxial light-emitting stacks, which substantially have the same width. | 08-15-2013 |
20130292643 | LIGHT-EMITTING DEVICE - A light-emitting device comprising: a light-emitting stacked layer having a first conductivity type semiconductor layer; a light-emitting layer formed on the first conductivity type semiconductor layer; and a second conductivity type semiconductor layer formed on the light-emitting layer; a transparent conductive oxide layer formed on the second conductivity type semiconductor layer wherein the transparent conductive oxide layer having a first portion and a second portion and the upper surface of the transparent conductive oxide layer is a textured surface; a first electrode formed on the second portion of the transparent conductive oxide layer, and a second electrode formed on the first conductivity type semiconductor layer; a planarization layer formed on the first portion of the transparent conductive oxide layer, and the second electrode; and a reflective layer formed on the planarization layer that is devoid of the first electrode and the second electrode. | 11-07-2013 |
20130292731 | LIGHT-EMITTING DEVICE - A light-emitting device wherein the light-emitting device having a corner, comprising: a light-emitting stacked layer having a first conductivity type semiconductor layer; a light-emitting layer formed on the first conductivity type semiconductor layer; and a second conductivity type semiconductor layer formed on the light-emitting layer; a transparent conductive oxide layer formed on the second conductivity type semiconductor layer wherein the upper surface of the transparent conductive oxide layer is a textured surface; a first electrode formed on the upper surface of the transparent conductive oxide layer; a second electrode formed on the first conductivity type semiconductor layer; a planarization layer formed on partial of the transparent conductive oxide layer and the second electrode; and a reflective layer formed on the upper surface of the planarization layer wherein the projection of the edge of the reflective layer is not overlapped with the edge of the first electrode or the second electrode. | 11-07-2013 |
20130314001 | Light-Emitting Device with Temperature Compensation - The present application provides a light-emitting device comprising a first light-emitting diode group; a second light-emitting diode group electrically connected to the first light-emitting diode group in parallel; and a temperature compensation. element electrically connected to the second light-emitting diode group in series; and a first switch device connected between the second light-emitting diode group and the temperature compensation element. | 11-28-2013 |
20130341667 | LIGHT-EMITTING DEVICE - A light-emitting device includes a semiconductor light-emitting stack; a current injected portion formed on the semiconductor light-emitting stack; an extension portion having a first branch radiating from the current injected portion and a second branch extending from the first branch; an electrical contact structure between the second branch and the semiconductor light-emitting stack and having a first width; and a current blocking structure located right beneath the electrical contact structure and having a second width larger than the first width. | 12-26-2013 |
20140061708 | LIGHT-EMITTING DEVICE - A light-emitting device includes a first electrode; a light-emitting stacked layer on the first electrode; a first contact layer on the light-emitting stacked layer, wherein the first contact layer includes a first contact link and a plurality of first contact lines connected to the first contact link; a first conductive post in the light-emitting stacked layer and electrically connecting the first electrode and the first contact layer; and a passivation layer between the first conductive post and the light-emitting stacked layer. | 03-06-2014 |
20140093991 | METHOD FOR MANUFACTURING HIGH EFFICIENCY LIGHT-EMITTING DIODES - A method of manufacturing a light-emitting device comprising the steps of cutting a substrate by a laser beam to form a cavity in the substrate and generate a by-product directly on the substrate by the cutting, and removing the by-product by a chemical solution containing an acid under a predetermined cleaning temperature. | 04-03-2014 |
20140186979 | LIGHT EMITTING DEVICE AND MANUFACTURE METHOD THEREOF - The present disclosure provides a method for forming a light-emitting apparatus, comprising providing a first board having a plurality of first metal contacts, providing a substrate, forming a plurality of light-emitting stacks and trenches on the substrate, wherein the light-emitting stacks are apart from each other by the plurality of the trenches, bonding the light-emitting stacks to the first board, forming an encapsulating material commonly on the plurality of the light-emitting stacks, and cutting the first board and the encapsulating material to form a plurality of chip-scale LED units. | 07-03-2014 |
Pai-Chu Hsieh, Hsinchu City TW
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20120062753 | IMAGE ENCODING INTEGRATED CIRCUIT AND ENCODED IMAGE DATA TRANSMISSION METHOD THEREOF - An image encoding integrated circuit and an encoded image data transmission method thereof are provided. The image encoding integrated circuit is utilized in a webcam and includes a central processing unit, an image sensing control unit, an image encoder unit, a bit rate monitoring unit, a transmission unit, and a bit rate control unit. The central processing unit, the image sensing control unit, the bit rate monitoring unit, and the transmission unit respectively produce a demand adjustment signal, a sensing status signal, a bit rate signal, and a transmission status signal. The bit rate control unit utilizes at least one of the signals to produce a quantization parameter signal. The image encoding unit transmits encoded image data in a specific bit rate, wherein the bit rate is adjusted according to the quantization parameter signal. The output bit rate of the image encoding unit is adjusted in consideration of even more system parameters, so as to improve the efficiency of the bit rate control. | 03-15-2012 |
20120294542 | PIXEL DATA COMPRESSION AND DECOMPRESSION METHOD - A pixel data decompression method for decompressing a frame is provided. The method includes: loading memory storage addresses corresponding to to-be-decompressed blocks; reading and decompressing a pixel line of a current block according to a memory storage address of the current block; updating the memory storage address of the current block according to a decompression result; reading a memory storage address of a next block if decompression of a pixel line of the frame is not completed; and repeating the above steps until decompression of the frame is completed. | 11-22-2012 |
20120294544 | IMAGE COMPRESSION METHOD - An image compression method is provided. Residuals of a lot of pixel data are calculated. Respective compression costs of the residuals of the pixel data are estimated according to a lot of category residual relationships. The compression costs are compared and one of the category residual relationships is selected. The residuals of the pixel data are compressed according to the selected category residual relationship. | 11-22-2012 |
Pao-Ju Hsieh, Hsinchu City TW
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20100110336 | OPTICAL ELEMENTS, BACKLIGHT MODULES, AND LIQUID CRYSTAL DISPLAY EMPLOYING THE SAME - Optical elements and backlight modules employing the same are provided. The optical element can be a brightness enhancement diffusion complex film, comprising a cholesteric liquid crystal film and a transparent optical film directly disposed on the cholesteric liquid crystal film. Particularly, the whole transparent optical film directly contacts to the cholesteric liquid crystal film, in the absence of an intermediate located between the transparent optical film and the cholesteric liquid crystal film. | 05-06-2010 |
20100321626 | BISTABLE DISPLAY MATERIALS AND METHODS AND DEVICES THEREOF - A display material and method and device thereof are provided. The display material is first formed by evenly mixing appropriate weight ratios of DFLCs, incurable nanoparticles, curable nanoparticles, and a photoinitiator. Next, the evenly mixed mixture is disposed between two parallel conducting transparent substrates, wherein an electrical field is conducted thereto and the DFLCs therein aligned to the direction of the applied electrical field. Concurrently, under the applied electrical field, some curable nanoparticles within the evenly mixed mixture, form short nano chains, initiating the photo initiator. The frame structure of short nano chains stabilize both the clear and scattering states, thereby the bistable characteristic was improved and the contrast ratio was enhanced as applied to bistable displays. | 12-23-2010 |
20130341566 | POLYMER-STABILIZED OPTICAL ISOTROPIC LIQUID CRYSTAL FORMULATION AND OPTICAL ISOTROPIC LIQUID CRYSTAL DEVICE - An embodiment provides a polymer-stabilized optical isotropic liquid crystal formulation, including 50 to 99.5 parts by weight of an optical isotropic liquid crystal material; and 0.5 to 50 parts by weight of polymer, wherein the polymer is polymerized by an acrylic monomer containing fluorine groups and an acrylic monomer with a liquid crystal phase and/or an acrylic monomer without a liquid crystal phase. | 12-26-2013 |
Tsung-Eong Hsieh, Hsinchu City TW
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20110079754 | Fabricating method of nano-powder and application thereof - A fabricating method of nano-powder is provided. First, a mixture having at least a first material and a second material is provided. Then, the mixture is sintered to obtain a single phase alloy body. After that, the single phase alloy body is pre-crumbled to obtain a powder to be ground. Then, a chemical dispersant is added into the powder to further be ground, so as to obtain the nano-powder. | 04-07-2011 |
Tsung-Fu Hsieh, Hsinchu City TW
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20100279436 | Inspection Method For Integrated Circuit Manufacturing Processes - The present disclosure provides a method for manufacturing integrated circuit devices including an electron beam inspection. The method includes forming a silicide region on a substrate. In an embodiment, the silicide region is formed to provide contact to a device feature such as a source or drain region. An electron beam scan is then performed on the substrate. The electron beam scan includes a first scan and a second scan. The first scan includes a lower landing energy than the second scan. In an embodiment, the first scan provides a dark silicide image analysis and a bright image analysis. In an embodiment, the second scan provides a dark silicide image analysis. The method continues to form a conductive plug after performing the electron beam scan. | 11-04-2010 |
Tsung-Jung Hsieh, Hsinchu City TW
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20120179638 | RELATIVE VARIABLE SELECTION SYSTEM AND SELECTION METHOD THEREOF - The present invention discloses a relative variable selection system and a selection method thereof. In the present invention, the receiving module receives a plurality of variables. Based on a correlation coefficient of variables, a first selection module sequentially selects variables with a correlation coefficient greater than a first threshold value. Based on the variables selected by the first selection module, a first calculating module selects a regression value and a weighted value corresponding to the foregoing variables. Based on the weighted values, a second selection module sequentially selects variables with a weighted value smaller than a second threshold value. Based on the variables selected by the second selection module, a second calculating module calculates analyzed values of the foregoing variables. Based on the analyzed values of the variables, a third selection module selects analyzed values which are greater than the target value. | 07-12-2012 |
Tsung-Ying Hsieh, Hsinchu City TW
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20100207638 | Testing System and Testing Method - The invention discloses a testing system and a testing method. The testing system includes a testing platform and a fetching device. The testing platform includes a metal base plate, a DUT board, a testing stand and a metal wall. The DUT board is disposed on the metal base plate. The testing stand is disposed on the DUT board. The metal wall is disposed on the metal base plate and surrounds the testing stand. The fetching device is movably disposed above the testing platform and used for placing a DUT on the testing stand. A metal covering plate of the fetching device corresponds to the metal wall of the testing platform. When the fetching device places the DUT on the testing stand, the metal covering plate cooperates with the metal wall and the metal base plate of the testing platform to form an isolated space, so as to isolate the DUT. | 08-19-2010 |
20100289706 | WIRELESS COMMUNICATING DEVICE AND PORTABLE ELECTRONIC APPARATUS USING THE SAME - A portable electronic apparatus is provided which includes a first housing, a second housing, a control unit, a display unit, and a wireless communication device. The two housings are rotatably coupled to each other. The control unit is accommodated in the first housing. The display unit is accommodated in the second housing and is connected to the control unit. The wireless communication device is accommodated in the second housing and has a wireless communication module and an antenna. The wireless communication module is connected to the control unit and the antenna, and is configured to perform wireless communication through the antenna under control of the control unit. | 11-18-2010 |
20130201650 | MOLDED RADIO-FREQUENCY STRUCTURE WITH SELECTIVE ELECTROMAGNETIC SHIELDING AND FORMING METHOD THEREOF - A molded radio-frequency (RF) structure with electromagnetic shielding includes a substrate layer, an RF layer, a molded layer and a metal layer. The RF element is disposed on the substrate layer. The molded layer is located on the substrate layer and overlays the RF element. The metal layer is coated on the molded layer, and has an opening located above the RF element. | 08-08-2013 |
Wei-Chih Hsieh, Hsinchu City TW
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20110221512 | Charge Pump - A charge pump is disclosed for amplifying an input voltage received at an input end and outputting the amplified voltage at an output end as an output voltage. The charge pump includes a plurality of source/drain coupling transistors for serving as charging capacitors, and a plurality of cascode-connected transistors being symmetrically connected to between the input end and the output end. The charge pump further includes a plurality of diode-connected transistors to protect the source/drain coupling transistors against breakdown during the course of charge transfer and to speed up the charge transfer. | 09-15-2011 |
Wei-Jer Hsieh, Hsinchu City TW
Wei-Pin Hsieh, Hsinchu City TW
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20100240120 | ANALYTICAL STRIP AND THE MANUFACTURING METHOD THEREOF - An analytical strip including a substrate and a channel structure is disclosed. A substrate has a flat surface and the channel is formed on the flat surface according to a predetermined pattern. The surface of channel structure is not lower than the surface of the substrate. The channel has a hollow-matrix conformation and the channel is more hydrophilic than the flat surface of the substrate is. The strip also contains a reaction material formed in the hollow-matrix. | 09-23-2010 |
Wen-Chin Hsieh, Hsinchu City TW
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20090261914 | CRYSTAL OSCILLATOR CIRCUITS - An oscillator circuit. A gain stage element is coupled between both terminals of the crystal. The gain stage element provides a transconductance for oscillation according to a current provided by a current source, and outputs a periodic signal through an output terminal. A bias element is coupled between an input terminal and the output terminal of the gain stage element to bias the gain stage element. A first capacitor is coupled to the input terminal of the gain stage element. A second capacitor is coupled to the output terminal of the gain stage element. A controller detects the periodic signal, and adjusts the current when the periodic signal is obtained. | 10-22-2009 |
20100128177 | SIGNAL PROCESSING UNITS CAPABLE OF PROVIDING PLUG-IN DETECTION - Signal processing units capable of providing plug-in detection without an external circuit occupying GPIO resource are provided, in which a switching element is coupled to a television signal output pad, a terminal resistor is coupled between the switching element and a ground voltage, and an interrupt signal generator generates an interrupt signal when a receiving port of a television signal receiver is coupled to the television signal pad. A control unit turns on the switching element to connect the terminal resistor to the television signal output pad when receiving the interrupt signal, wherein the switching element, the terminal resistor, the interrupt signal generator and the control unit are integrated in a chip. | 05-27-2010 |
Wen-Hsing Hsieh, Hsinchu City TW
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20140103438 | MULTI-GATE SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin. | 04-17-2014 |
20140138763 | Semiconductor Integrated Device with Channel Region - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device precursor. The semiconductor device precursor includes a substrate, source/drain regions on the substrate, dummy gate stacks separating the source/drain regions on the substrate and a doped region under the dummy gate stacks. The dummy gate stack is removed to form a gate trench. The doped region in the gate trench is recessed to form a channel trench. A channel layer is deposited in the channel trench to form a channel region and then a high-k (HK) dielectric layer and a metal gate (MG) are deposited on the channel region. | 05-22-2014 |
20140151761 | Fin-Like Field Effect Transistor (FinFET) Channel Profile Engineering Method And Associated Device - A FinFET device and method for fabricating a FinFET device are disclosed. An exemplary method includes providing a substrate; forming a fin over the substrate; forming an isolation feature over substrate; forming a gate structure including a dummy gate over a portion of the fin, the gate structure traversing the fin, wherein the gate structure separates a source region and a drain region of the fin, a channel being defined in the portion of the fin between the source region and the drain region; and replacing the dummy gate of the gate structure with a metal gate, wherein during the replacing the dummy gate, a profile of the portion of the fin is modified. In an example, modifying the profile of the portion of the fin includes increasing a height of the portion of the fin and/or decreasing a width of the portion of the fin. | 06-05-2014 |
20140183641 | HIGH EFFICIENCY FINFET DIODE - Disclosed are a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped. | 07-03-2014 |
20140217479 | FINFET WITH DUAL WORKFUNCTION GATE STRUCTURE - Disclosed are a method to fabricate a semiconductor device having a two-layered gate structure, and so fabricated a semiconductor. The gate threshold voltage can be tuned by using two metal layers with different workfunctions, disposed over a fin structure on a substrate and extending in parallel to the current flow direction in the fin structure, and by varying individual thicknesses of the layer so as to change the relative coverage of the fin structure by the layers. The method may comprise providing a substrate having a fin structure, depositing first and second gate metals, and forming a gate dielectric layer. The method may further comprise determining the workfunctions of the first and second gate metals and their thicknesses to achieve a desired gate threshold voltage. Forming the first and second gate metal layers and the dielectric layer may use processes such as deposition, epitaxial growth, CMP, or selective etching. | 08-07-2014 |
20140264493 | Semiconductor Device and Fabricating the Same - A semiconductor device includes a substrate, a gate stack having at least one gate vertex directed to an area in the substrate below the gate stack. The semiconductor device also includes a source structure having at least one vertex directed toward the area in the substrate and a drain structure having at least one vertex directed toward the area in the substrate. | 09-18-2014 |
Wen-I Hsieh, Hsinchu City TW
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20140069802 | APPARATUS AND METHODS FOR PHYSICAL VAPOR DEPOSITION - This disclosure provides systems, methods, and apparatus related to physical vapor deposition. In one aspect, an apparatus includes a magnet assembly including a magnet element, a substrate holder configured to hold a substrate, a target holder configured to hold a target positioned between the magnet assembly and the substrate, a motor configured to move the magnet assembly across a face of the substrate, and a controller. The controller includes program instructions for conducting a process including moving the magnet assembly across the face of the substrate using the motor to sputter material from the target onto the substrate. The material sputtered onto the substrate may have a substantially uniform thickness. | 03-13-2014 |
Wen-Yi Hsieh, Hsinchu City TW
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20080311713 | MOBILITY ENHANCEMENT BY STRAINED CHANNEL CMOSFET WITH SINGLE WORKFUNCTION METAL-GATE AND FABRICATION METHOD THEREOF - The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively. As such, the threshold voltages of the two types of transistors can be obtained in oppositely symmetric by single metal gate. | 12-18-2008 |
Yen-Chang Hsieh, Hsinchu City TW
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20130175553 | LIGHT-EMITTING DIODE DEVICE - The present invention is directed to a light-emitting diode (LED) device, which includes at least one LED unit. Each LED unit includes at least one LED, which includes a first doped layer, a second doped layer and a conductive defect layer. The conductive defect layer is formed on the first or second doped layer. The conductive defect layer may be deposited between two LEDs, or between the first/second doped layer and an electrode. | 07-11-2013 |
20130175674 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a p-type doped layer, an n-type doped layer, and an internal electrical connection layer that is deposited and electrically coupled between the p-type doped layer and the n-type doped layer. In one embodiment, the internal electrical connection layer includes a group IV element and a nitrogen element, and the number of atoms of the group IV element and the nitrogen element is greater than 50% of the total number of atoms in the internal electrical connection layer. In another embodiment, the internal electrical connection layer includes carbon element with a concentration greater than 10 | 07-11-2013 |
20130178046 | METHOD OF MANUFACTURING A SEMICONDUCTOR APPARATUS - A method of manufacturing a semiconductor apparatus is disclosed. A first-type doped layer, a second-type doped layer, and an internal electrical connection layer are formed. The internal electrical connection layer is deposited and electrically coupled between the first-type doped layer and the second-type doped layer. In one embodiment, the internal electrical connection layer is formed by using a group IV based precursor and nitrogen based precursor. In another embodiment, the internal electrical connection layer is formed by a mixture comprising a carbon-contained doping source, and the internal electrical connection layer has a carbon concentration greater than 10 | 07-11-2013 |
20130228740 | LIGHT-EMITTING DIODE DEVICE - A light-emitting diode (LED) device includes at least one LED unit. Each LED unit includes at least one LED. Each LED includes an n-side nitride semiconductor layer, a p-side nitride semiconductor layer, and an active layer that is located between the n-side nitride semiconductor layer and the p-side nitride semiconductor layer. The active layer is includes one or more well layers. At least one of the well layers has a multilayered structure. | 09-05-2013 |
Yi-Chang Hsieh, Hsinchu City TW
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20120315953 | ENCLOSURE FOR IMAGE CAPTURE SYSTEMS WITH FOCUSING CAPABILITIES - Embodiments of the invention describe an enclosure for an image capture system that includes an image capture unit and a solid state die to provide focusing capabilities for a lens unit of the image capture unit. The enclosure may electrically couple the solid state die to the image capture unit and/or other system circuitry. The enclosure may further serve as EMI shielding for the image capture system. | 12-13-2012 |
Ying Hao Hsieh, Hsinchu City TW
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20110049567 | BOTTLE-NECK RECESS IN A SEMICONDUCTOR DEVICE - The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess. | 03-03-2011 |
Yong-Fen Hsieh, Hsinchu City TW
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20140007709 | SPECIMEN PREPARATION FOR TEM - A specimen kit having a tiny chamber is disclosed for a specimen preparation for TEM. The space height of the chamber is far smaller than dimensions of blood cells and therefore is adapted to sort nanoparticles from the blood cells. The specimen prepared under this invention is suitable for TEM observation over a true distribution status of nanoparticles in blood. The extremely tiny space height in Z direction eliminates the possibility of aggregation of the nanoparticles and/or agglomeration in Z direction during drying; therefore, a specimen prepared under this invention is suitable for TEM observation over the dispersion and/or agglomeration of nanoparticles in a blood. | 01-09-2014 |
Yuan-Chih Hsieh, Hsinchu City TW
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20080246152 | SEMICONDUCTOR DEVICE WITH BONDING PAD - A semiconductor device with a bonding pad is provided. The semiconductor device includes a first substrate having a device area and a bonding area, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are disposed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is disposed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is disposed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad, and the first substrate is exposed through an opening in the lowermost metal pattern. | 10-09-2008 |
20090039452 | EMBEDDED BONDING PAD FOR IMAGE SENSORS - A semiconductor device includes a semiconductor substrate having a front surface and a back surface, elements formed on the substrate, interconnect metal layers formed over the front surface of the substrate, including a topmost interconnect metal layer, an inter-metal dielectric for insulating each of the plurality of interconnect metal layers, and a bonding pad disposed within the inter-metal dielectric, the bonding pad in contact with one of the interconnect metal layers other than the topmost interconnect metal layer. | 02-12-2009 |
20090124073 | SEMICONDUCTOR DEVICE WITH BONDING PAD - A method for forming a semiconductor device with a bonding pad is disclosed. A first substrate having a device area and a bonding area is provided, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are formed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is formed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is formed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad. An opening through the first substrate is formed to expose the lowermost metal pattern. | 05-14-2009 |
20100087029 | METHOD OF FABRICATING BACKSIDE ILLUMINATED IMAGE SENSOR - A method for fabricating a backside illuminated image sensor is provided. An exemplary method can include providing a substrate with a front surface and a back surface; forming a first alignment mark for global alignment on the front surface of the substrate; forming a second alignment mark for fine alignment in a clear-out region on the front surface of the substrate; aligning the substrate from the back surface using the first alignment mark; and removing a portion of the back surface of the substrate at the clear-out region for locating the second alignment mark. | 04-08-2010 |
20100151615 | METHODS FOR FABRICATING IMAGE SENSOR DEVICES - Image sensor devices and methods for fabricating the same are provided. An exemplary embodiment of an image sensor device comprises a support substrate. A passivation structure is formed over the support substrate. An interconnect structure is formed over the passivation structure. A first semiconductor layer is formed over the interconnect structure, having a first and second surfaces, wherein the first and second surfaces are opposing surfaces. At least one light-sensing device is formed over/in the first semiconductor layer from a first surface thereof. A color filter layer is formed over the first semiconductor layer from a second surface thereof. At least one micro lens is formed over the color filter layer. | 06-17-2010 |
20110156217 | POWER DEVICES HAVING REDUCED ON-RESISTANCE AND METHODS OF THEIR MANUFACTURE - A method for forming a support structure for supporting and handling a semiconductor wafer containing vertical FETs formed at the front surface thereof is provided. In one embodiment, a semiconductor wafer is provided having a front surface and a rear surface, wherein the front surface comprises one or more dies separated by dicing lines. The wafer is thinned to a predetermined thickness. A plurality of patterned metal features are formed on a thinned rear surface to provide support for the wafer, wherein each of the plurality of patterned metal features covers substantially one die, leaving the dicing lines substantially uncovered. The wafer is thereafter diced along the dicing lines to separate the one or more dies for later chip packaging. | 06-30-2011 |
20110159631 | METHOD OF FABRICATING BACKSIDE ILLUMINATED IMAGE SENSOR - A method for fabricating a backside illuminated image sensor is provided. An exemplary method can include providing a substrate having a front surface and a back surface; forming an alignment mark at the front surface of the substrate, wherein the alignment mark is detectable for alignment from the back surface; and processing the substrate from the back surface by performing registration from the back surface and using the alignment mark as a reference. | 06-30-2011 |
20110233621 | Wafer Level Packaging Bond - The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum. | 09-29-2011 |
20120025389 | Hermetic Wafer Level Packaging - Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers. | 02-02-2012 |
20120074590 | MULTIPLE BONDING IN WAFER LEVEL PACKAGING - The present disclosure provides a method for fabricating a MEMS device including multiple bonding of substrates. In an embodiment, a method includes providing a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, providing a semiconductor substrate including a second bonding layer, and providing a cap including a third bonding layer. The method further includes bonding the MEMS substrate to the semiconductor substrate at the first and second bonding layers, and bonding the cap to the semiconductor substrate at the second and third bonding layers to hermetically seal the MEMS substrate between the cap and the semiconductor substrate. A MEMS device fabricated by the above method is also provided. | 03-29-2012 |
20120080761 | SEMICONDUCTOR HAVING A HIGH ASPECT RATIO VIA - A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer. | 04-05-2012 |
20120091598 | HANDLING LAYER FOR TRANSPARENT SUBSTRATE - A device is provided which includes a transparent substrate. An opaque layer is disposed on the transparent substrate. A conductive layer disposed on the opaque layer. The opaque layer and the conductive layer form a handling layer, which may be used to detect and/or align the transparent wafer during fabrication processes. In an embodiment, the conductive layer includes a highly-doped silicon layer. In an embodiment, the opaque layer includes a metal. In embodiment, the device may include a MEMs device. | 04-19-2012 |
20120148870 | SELF-REMOVAL ANTI-STICTION COATING FOR BONDING PROCESS - A bond free of an anti-stiction layer and bonding method is disclosed. An exemplary method includes forming a first bonding layer; forming an interlayer over the first bonding layer; forming an anti-stiction layer over the interlayer; and forming a liquid from the first bonding layer and interlayer, such that the anti-stiction layer floats over the first bonding layer. A second bonding layer can be bonded to the first bonding layer while the anti-stiction layer floats over the first bonding layer, such that a bond between the first and second bonding layers is free of the anti-stiction layer. | 06-14-2012 |
20120149152 | METHOD TO PREVENT METAL PAD DAMAGE IN WAFER LEVEL PACKAGE - The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a bonding pad on a first substrate; forming wiring pads on the first substrate; forming a protection material layer on the first substrate, on sidewalls and top surfaces of the wiring pads, and on sidewalls of the bonding pad, such that a top surface of the bonding pad is at least partially exposed; bonding the first substrate to a second substrate through the bonding pad; opening the second substrate to expose the wiring pads; and removing the protection material layer. | 06-14-2012 |
20120235300 | SEMICONDUCTOR HAVING A HIGH ASPECT RATIO VIA - The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer. | 09-20-2012 |
20120238091 | SEMICONDUCTOR HAVING A HIGH ASPECT RATIO VIA - The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed over the dielectric layer and the portion of the via sidewalls. In an example, the dielectric layer is an oxide layer. | 09-20-2012 |
20130037891 | MEMS DEVICE AND METHOD OF FORMATION THEREOF - The present disclosure provides a method including providing a first substrate; and forming a microelectromechanical system (MEMS) device on a first surface of the first substrate. A bond pad is formed on at least one bonding site on the first surface of the first substrate. The bonding site is recessed from the first surface. Thus, a top surface of the bond pad may lie below the plane of the top surface of the substrate. A device with recessed connective element(s) (e.g., bond pad) is also described. In further embodiments, a protective layer is formed on the recessed connective element during dicing of a substrate. | 02-14-2013 |
20130208371 | BIOLOGICAL SENSING STRUCTURES AND METHODS OF FORMING THE SAME - A method of forming of biological sensing structures including a portion of a substrate is recessed to form a plurality of mesas in the substrate. Each of the plurality of mesas has a top surface and a sidewall surface. A first light reflecting layer is deposited over the top surface and the sidewall surface of each mesa. A filling material is formed over a first portion of the first light reflecting layer. A stop layer is deposited over the filling material and a second portion of the first light reflecting layer. A sacrificial layer is formed over the stop layer and is planarized exposing the stop layer. A first opening is formed in the stop layer and the first light reflecting layer. A second light reflecting layer is deposited over the first opening. A second opening is formed in the second light reflecting layer. | 08-15-2013 |
20130285170 | MULTIPLE BONDING IN WAFER LEVEL PACKAGING - A MEMS device is described. The device includes a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, a semiconductor substrate including a second bonding layer, and a cap including a third bonding layer, the cap coupled to the semiconductor substrate by bonding the second bonding layer to the third bonding layer. The first bonding layer includes silicon, the semiconductor substrate is electrically coupled to the MEMS substrate by bonding the first bonding layer to the second bonding layer, and the MEMS substrate is hermetically sealed between the cap and the semiconductor substrate. | 10-31-2013 |
20130344640 | Method of Making Wafer Structure for Backside Illuminated Color Image Sensor - An integrated circuit device is provided. The integrated circuit device can include a substrate; a first radiation-sensing element disposed over a first portion of the substrate; and a second radiation-sensing element disposed over a second portion of the substrate. The first portion comprises a first radiation absorption characteristic, and the second portion comprises a second radiation absorption characteristic different from the first radiation absorption characteristic. | 12-26-2013 |
20140051336 | GRINDING WHEEL FOR WAFER EDGE TRIMMING - A grinding wheel for wafer edge trimming includes a head having an open side and an abrasive end bonded around an edge of the open side of the head. The abrasive end is arranged to have multiple simultaneous contacts around a wafer edge during the wafer edge trimming. | 02-20-2014 |
20140054779 | Semiconductor Having a High Aspect Ratio Via - The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer. | 02-27-2014 |
20140103462 | MEMS Devices and Methods for Forming the Same - A method includes forming a Micro-Electro-Mechanical System (MEMS) device on a front surface of a substrate. After the step of forming the MEMS device, a through-opening is formed in the substrate, wherein the through-opening is formed from a backside of the substrate. The through-opening is filled with a dielectric material, which insulates a first portion of the substrate from a second portion of the substrate. An electrical connection is formed on the backside of the substrate. The electrical connection is electrically coupled to the MEMS device through the first portion of the substrate. | 04-17-2014 |
20140154841 | Hermetic Wafer Level Packaging - Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers. | 06-05-2014 |
20140248730 | MEMS Device and Method of Formation Thereof - The present disclosure provides a method including providing a first substrate; and forming a microelectromechanical system (MEMS) device on a first surface of the first substrate. A bond pad is formed on at least one bonding site on the first surface of the first substrate. The bonding site is recessed from the first surface. Thus, a top surface of the bond pad may lie below the plane of the top surface of the substrate. A device with recessed connective element(s) (e.g., bond pad) is also described. In further embodiments, a protective layer is formed on the recessed connective element during dicing of a substrate. | 09-04-2014 |
20150021666 | TRANSISTOR HAVING PARTIALLY OR WHOLLY REPLACED SUBSTRATE AND METHOD OF MAKING THE SAME - A transistor includes a substrate, a channel layer over the substrate, an active structure over the channel layer, a gate electrode over the channel layer, and a drain electrode over the channel layer. The active structure is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active structure. The gate electrode and the drain electrode define a first space therebetween. The substrate has a first portion directly under the first space defined between the gate electrode and the drain electrode, and the first portion has a first electrical conductivity value less than that of intrinsic silicon and a thermal conductivity value greater than that of intrinsic silicon. | 01-22-2015 |
20150044008 | Robot Blade Design - The present disclosure relates to a wafer transfer robot having a robot blade that can be used to handle substrates that are patterned on both sides without causing warpage of the substrates. In some embodiments, the wafer transfer robot has a robot blade coupled to a transfer arm that varies a position of the robot blade. The robot blade has a wafer reception area that receives a substrate. Two or more spatially distinct contact points are located at positions along a perimeter of the wafer reception area that provide support to opposing edges of the substrate. The two or more contact points are separated by a cavity in the robot blade. The cavity mitigates contact between a backside of the substrate and the robot blade, while providing support to opposing sides of the substrate to prevent warpage of the substrate. | 02-12-2015 |
20150044759 | BIOLOGICAL SENSING STRUCTURES - A biological sensing structure includes a mesa integrally connected a portion of a substrate, wherein the mesa has a top surface and a sidewall surface adjacent to the top surface. The biological sensing structure includes a first light reflecting layer over the top surface and the sidewall surface of the mesa. The biological sensing structure includes a filling material surrounding the mesa, wherein the mesa protrudes from the filling material. The biological sensing structure includes a stop layer over the filling material and a portion of the first light reflecting layer. The biological sensing structure includes a second light reflecting layer over a portion of the stop layer and a portion of the top surface of the mesa. The biological sensing structure includes an opening in the second light reflecting layer to partially expose the top surface of the mesa. | 02-12-2015 |
20150069539 | Cup-Like Getter Scheme - The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by increasing an area in which a getter layer is deposited, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having one or more residual gases. A cavity is formed within a top surface of the substrate. The cavity has a bottom surface and sidewalls extending from the bottom surface to the top surface. A getter layer, which absorbs the one or more residual gases, is deposited over the substrate at a position extending from the bottom surface of the cavity to a location on the sidewalls. By depositing the getter layer to extend to a location on the sidewalls of the cavity, the area of the substrate that is able to absorb the one or more residual gases is increased. | 03-12-2015 |
20150069581 | NOBLE GAS BOMBARDMENT TO REDUCE SCALLOPS IN BOSCH ETCHING - A method of etching a trench in a substrate is provided. The method repeatedly alternates between using a fluorine-based plasma to etch a trench, which has trench sidewalls, into a selected region of the substrate; and using a fluorocarbon plasma to deposit a liner on the trench sidewalls. The liner, when formed and subsequently etched, has an exposed sidewall surface that includes scalloped recesses. The trench, which includes the scalloped recesses, is then bombarded with a molecular beam where the molecules are directed on an axis parallel to the trench sidewalls to reduce the scalloped recesses. | 03-12-2015 |
Yu-Cheng Hsieh, Hsinchu City TW
Patent application number | Description | Published |
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20090240357 | METHOD FOR FINDING OUT THE FRAME OF A MULTIMEDIA SEQUENCE - An electronic device is provided comprising a multimedia play unit and a processor. The processor receives a multimedia sequence, acquires a first bitrate of a first frame header from the received multimedia sequence, predicts a first length of a first frame comprising the first frame header by a formula employing at least parameters comprising the first bitrate and a proportion of a second length to a second bitrate of a second frame header prior to the first frame header, and directs the multimedia play unit to play frame data of the first frame according to the predicted first length of the first frame. | 09-24-2009 |
Yung-Wei Hsieh, Hsinchu City TW
Patent application number | Description | Published |
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20130183823 | BUMPING PROCESS - A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots corresponded to the first areas of the titanium-containing metal layer, forming a plurality of copper bumps at the opening slots, proceeding a heat procedure, forming a plurality of bump isolation layers on the copper bumps, forming a plurality of connective layers on the bump isolation layers, removing the photoresist layer, removing the second areas and enabling each the first areas to form an under bump metallurgy layer. | 07-18-2013 |
20130187265 | PACKAGE STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF - A semiconductor structure comprises a carrier, a plurality of under bump metallurgy layers, a plurality of copper containing bumps and an organic barrier layer, wherein the carrier comprises a protective layer and a plurality of conductive pads, mentioned protective layer comprises a plurality of openings, the conductive pads exposed by the openings, mentioned under bump metallurgy layers being formed on the conductive pads, mentioned copper containing bumps being formed on the under bump metallurgy layers, each of the copper containing bumps comprises a top surface and a ring surface in connection with the top surface, mentioned organic barrier layer having a first coverage portion, and mentioned first coverage portion covers the top surface and the ring surface of each of the copper containing bumps. | 07-25-2013 |
20130214407 | SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF - A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dissociation substances. | 08-22-2013 |
20130214419 | SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF - A semiconductor packaging method includes providing a substrate having a plurality of connection pads; mounting a chip on the substrate, wherein the chip comprises a plurality of copper-containing bumps directly coupled to the connection pads, and each of the copper-containing bumps comprises a ring surface; forming an anti-dissociation gel between the substrate and the chip, wherein the anti-dissociation gel comprises a plurality of anti-dissociation substances, and the ring surfaces of the copper-containing bumps are covered by the anti-dissociation substances. | 08-22-2013 |
20130249081 | METHOD FOR MANUFACTURING FINE-PITCH BUMPS AND STRUCTURE THEREOF - A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer. | 09-26-2013 |
20130249089 | METHOD FOR MANUFACTURING FINE-PITCH BUMPS AND STRUCTURE THEREOF - A method for manufacturing fine-pitch bumps comprises the steps of providing a silicon substrate; forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first zones and a plurality of second zones; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer to form a plurality of opening slots; forming a plurality of copper bumps at the opening slots, wherein each of the copper bumps comprises a first top surface and a ring surface; heating the photoresist layer to form a plurality of body portions and a plurality of removable portions; etching the photoresist layer; and removing the second zones to enable each of the first zones to form an under bump metallurgy layer having a bearing portion and an extending portion. | 09-26-2013 |
20130252374 | SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF - A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dissociation substances. | 09-26-2013 |
20130256882 | METHOD FOR MANUFACTURING FINE-PITCH BUMPS AND STRUCTURE THEREOF - A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer. | 10-03-2013 |
20140159234 | SEMICONDUCTOR MANUFACTURING PROCESS AND STRUCTURE THEREOF - A semiconductor manufacturing process includes the following steps of providing a silicon substrate having at least one connection pad and a protection layer, forming a first seed layer having at least one first section and at least one second section, forming a first photoresist layer, forming a first buffer layer having a coupling portion and a cladding portion, removing the first photoresist layer, removing the second section of the first seed layer to form a first under bump metallurgy layer, forming a support layer on the protection layer and the first buffer layer, the first under bump metallurgy layer has a first ring wall, the first buffer layer has a second ring wall, wherein the first ring wall, the second ring wall and the cladding portion are cladded by the support layer, and forming a connection portion and covering the coupling portion with the connection portion. | 06-12-2014 |
20140367856 | SEMICONDUCTOR MANUFACTURING PROCESS AND STRUCTURE THEREOF - A semiconductor manufacturing process includes the following steps of providing a silicon substrate having at least one connection pad and a protection layer, forming a first seed layer having at least one first section and at least one second section, forming a first photoresist layer, forming a first buffer layer having a coupling portion and a cladding portion, removing the first photoresist layer, removing the second section of the first seed layer to form a first under bump metallurgy layer, forming a support layer on the protection layer and the first buffer layer, the first under bump metallurgy layer has a first ring wall, the first buffer layer has a second ring wall, wherein the first ring wall, the second ring wall and the cladding portion are cladded by the support layer, and forming a connection portion and covering the coupling portion with the connection portion. | 12-18-2014 |