Jouppi
Norm Jouppi, Palo Alto, CA US
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20090103855 | Three-dimensional die stacks with inter-device and intra-device optical interconnect - Examples of a computer system packaged in a three-dimensional stack of dies are described. The package includes an electrical die and an optical die coupled to and stacked with the electrical die. The electrical die includes circuitry to process and communicate electrical signals, and the optical die includes structures to transport optical signals. The electrical die has a smaller area than the optical die so that the optical die includes an exposed mezzanine which is configured with optical input/output ports. Additionally, the packaging can be configured to provide structural support against insertion forces for external optical connections. | 04-23-2009 |
20090103929 | Synchronous optical bus providing communication between computer system components - A synchronous optical bus system for communication between computer system components is described. In one example, the optical bus system is used for communication between a memory controller and memory devices optically coupled to an optical interconnect. Optical bus interface units couple the components to the optical interconnect and are arranged on the optical interconnect in order that a sum of an optical path length from a controller component to each computer system component and from each computer system component to the controller component is the same for all the coupled computer system components. A synchronous protocol is used for communication between the components. | 04-23-2009 |
Normal Paul Jouppi, Palo Alto, CA US
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20100200733 | Systems and methods for tuning optical ring resonators - Various embodiments of the present invention relate to systems and methods for monitoring and tuning detector and modulator resonators during operation. Aspects of the present invention use DC balanced coding of data in optical signals tune and monitor the performance of a resonator. Whether the resonator is being used as a modulator or a detector, the intensity of the light coupled into the resonator is DC balanced and varies as a function of the data being transmitted. Average intensity variations of the light scattered from the resonator are converted into an electronic feedback signal, which is used to determine appropriate levels of thermal and electronic tuning applied to the resonator. | 08-12-2010 |
Norman P. Jouppi, Palo Alto, CA US
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20110052204 | Intentionally Skewed Optical Clock Signal Distribution - Embodiments of the present invention relate to systems and methods for distributing an intentionally skewed optical-clock signal to nodes of a source synchronous computer system. In one system embodiment, a source synchronous system comprises a waveguide, an optical-system clock optically coupled to the waveguide, and a number of nodes optically coupled to the waveguide. The optical-system clock generates and injects a master optical-clock signal into the waveguide. The master optical-clock signal acquiring a skew as it passes between nodes. Each node extracts a portion of the master optical-clock signal and processes optical signals using the portion of the master optical-clock signal having a different skew for the respective extracting node. | 03-03-2011 |
20110069963 | Optoelectronic Switches Using On-chip Optical Waveguides - Embodiments of the present invention are directed to optoelectronic network switches. In one embodiment, an optoelectronic switch includes a set of roughly parallel input waveguides and a set of roughly parallel output waveguides positioned roughly perpendicular to the input waveguides. Each of the output waveguides crosses the set of input waveguides. The optoelectronic switch includes at least one switch element configured to switch one or more optical signals transmitted on one or more input waveguides onto one or more crossing output waveguides. | 03-24-2011 |
20110145493 | Independently Controlled Virtual Memory Devices In Memory Modules - Various embodiments of the present invention are directed a multi-core memory modules. In one embodiment, a memory module ( | 06-16-2011 |
20110145504 | Independently Controllable And Reconfigurable Virtual Memory Devices In Memory Modules That Are Pin-compatible With Standard Memory Modules - Various embodiments of the present invention are directed multi-core memory modules. In one embodiment, a memory module ( | 06-16-2011 |
20140173170 | MULTIPLE SUBARRAY MEMORY ACCESS - A multiple subarray-access memory system is disclosed. The system includes a plurality of memory chips, each including a plurality of subarrays and a memory controller in communication. with the memory chips, the memory controller to receive a memory fetch width (“MFW”) instruction during an operating system start-up and responsive to the MFW instruction to fix a quantity of the subarrays that will be activated in response to memory access requests. | 06-19-2014 |
Paul Norman Jouppi, Palo Alto, CA US
Patent application number | Description | Published |
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20120151159 | INTERFACE METHODS AND APPARATUS FOR MEMORY DEVICES - A disclosed example apparatus includes an interface ( | 06-14-2012 |