Patent application number | Description | Published |
20090065867 | ORIENTATION-OPTIMIZED PFETS IN CMOS DEVICES EMPLOYING DUAL STRESS LINERS - A PFET is provided on a silicon layer having a (110) surface orientation and located in a substrate. A compressive stress liner disposed on the gate and source/drain regions of the PFET generates a primary longitudinal compressive strain along the direction of the PFET channel. A tensile stress liner disposed on at least one NFET located transversely adjacent to the PFET generates a primary longitudinal tensile strain along the direction of the NFET channel. A secondary stress field from the at least one NFET tensile liner generates a beneficial transverse tensile stress in the PFET channel. The net benefits of the primary compressive longitudinal strain and the secondary tensile transverse stress are maximized when the azimuthal angle between the direction of the PFET channel and an in-plane [1 | 03-12-2009 |
20090242942 | ASYMMETRIC SOURCE AND DRAIN FIELD EFFECT STRUCTURE AND METHOD - A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor structure using a semiconductor substrate that includes a horizontal plateau region contiguous with and adjoining a sloped incline region. Within the context of a CMOS semiconductor structure, such a semiconductor substrate allows for fabrication of a pFET and an nFET upon different crystallographic orientation semiconductor regions, while one of the pFET and the nFET (i.e., typically the pFET) has asymmetric source and drain regions. | 10-01-2009 |
20120181549 | STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS - A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers. | 07-19-2012 |
20130140636 | STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS - A stressed channel field effect transistor (FET) includes a substrate; a gate stack located on the substrate; a channel region located in the substrate under the gate stack; source/drain stressor material located in cavities in the substrate on either side of the channel region; and vertical source/drain buffers located in the cavities in the substrate between the source/drain stressor material and the substrate, wherein the source/drain stressor material abuts the channel region above the source/drain buffers. | 06-06-2013 |
Patent application number | Description | Published |
20090103604 | Method and Apparatus for On-Chip Voltage Controlled Oscillator Function - This invention uses a flying adder frequency synthesis circuit to provide the required frequency adjustments to accommodate the varying encoding density of a MPEG2 video data stream. This invention adjusts the local clock based on the information extracted from the program clock reference signal in the incoming data. This invention replaces an external or internal voltage-controlled crystal oscillator using a phase locked loop circuit on the video processing integrated circuit. | 04-23-2009 |
20090160493 | System and Method for Generating a Spread-Spectrum Clock Signal - A circuit for, and method of, generating a spread-spectrum clock signal. In one embodiment, the circuit includes: (a) a modulator configured to generate a modulated control value, and (b) a frequency synthesizer coupled to the modulator and configured to generate a spread-spectrum clock signal based on a variation of the modulated control value, the frequency synthesizer having a directly-derivable frequency response output. | 06-25-2009 |
20090161809 | Method and Apparatus for Variable Frame Rate - A method and apparatus for adjusting to a frame rate. The method displays the video frames with varying rates. The method comprising the steps of detecting a change in the frame rate, calculating the FREQ of the frame, adjusting the phase-locked loop utilizing the calculated FREQ, and utilizing the adjusted phase-locked loop output as the pixel clock to display the frame. | 06-25-2009 |
20110131439 | Jitter Precorrection Filter in Time-Average-Frequency Clocked Systems - Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals. Time-average frequency synthesis circuitry generates internal clock signals of a desired frequency, for example as based on a recovered clock signal from an input data stream, in a manner in which not all periods of the clock signal are of uniform duration. A jitter precorrection filter is inserted into the data path to apply a variable delay to pre-correct for distortion caused by jitter in the clock cycle. In embodiments of the invention using a flying-adder architecture to generate the clock signal, coefficients of the digital filer realizing the jitter precorrection filter are calculated according to the currently-selected oscillator phase and according to a fractional portion of a digital frequency control word. | 06-02-2011 |
20110238721 | ADDER CIRCUIT AND XIU-ACCUMULATOR CIRCUIT USING THE SAME - A Xiu-accumulator circuit including N cascaded adders is provided. Each adder includes two registers, wherein one register stores an addition result information and the other register stores a carry-in information. Respective addition result information from respective adder is further fed back to itself for accumulation. The carry-in information outputted from a previous stage adder is fed to a next stage adder at a next clock cycle. After N clock cycles, the carry-in information outputted from the first stage adder is fed to the last stage adder. | 09-29-2011 |
20110254601 | LOCK DETECTOR, METHOD APPLICABLE THERETO, AND PHASE LOCK LOOP APPLYING THE SAME - A lock detector for a phase lock loop (PLL) includes: first and second pulse width extenders, performing pulse width extension on first and second pulses for generating third and fourth pulses, respectively; first and second delay circuits, delaying the third and the fourth pulses into first and second sampling clocks, respectively; and a cross-sampling circuit, sampling the third pulse based on the second sampling clock and sampling the fourth pulse based on the first sampling clock to indicate whether the PLL is locked. | 10-20-2011 |
20110285439 | Digital to Frequency Synthesis Using Flying-Adder with Dithered Command Input - To make Flying-Adder architecture even more powerful, a new concept, time-average-frequency, is incorporated into the clock generation circuitry. This is a fundamental breakthrough since it attacks the clock generation problem from its root: how is the clock signal used in real systems? By investigating from this direction, a much more powerful architecture, fixed-VCO-Flying-Adder architecture, is created. Furthermore, based on fixed-VCO-Flying-Adder frequency synthesizer and time-average-frequency, a new type of component called Digital-to-Frequency Converter (DFC) is born. | 11-24-2011 |
20120229171 | FREQUENCY SYNTHESIZER AND FREQUENCY SYNTHESIZING METHOD FOR CONVERTING FREQUENCY'S SPURIOUS TONES INTO NOISE - One of the advantages of direct frequency synthesis technique (e.g., flying-adder architecture) is its capability of generating arbitrary frequency by utilizing the time-average-frequency concept. In the clock output of the direct frequency synthesizer, instead of one type of cycle, there are two types of cycles. Unlike the conventional one-type-cycle clock wherein clock energy is concentrated at its designed frequency, Time-Average-Frequency based clock spreads some of its energy into spurious tones, which could be harmful to certain applications. The spurious tones are caused by the periodic carry sequence generated from a fractional part accumulator inside the frequency synthesizer. The invention suggests a method and an apparatus to break this periodicity and convert the spurious tones into broadband noise. | 09-13-2012 |
20140093015 | Circuits and Methods for Time-Average Frequency Based Clock Data Recovery - A clock data recovery circuit includes a binary phase detector configured to receive an incoming data signal and a recovered clock, and output a phase offset signal and recovered data; a digital loop control circuit configured to receive the phase offset signal and output a control signal; and a digital frequency generator configured to receive the control signal and output the recovered clock. A method of clock recovery includes generating a digital phase offset signal from incoming data and feedback clock signals; generating a clock frequency control signal from the phase offset signal; generating a recovered clock in response to the control signal; slowing down the recovered clock when the digital phase offset signal has a first binary state; speeding up the recovered clock when the digital phase offset signal has a second binary state; and holding the recovered clock when the digital phase offset signal has a third binary state. | 04-03-2014 |
20140118173 | METHOD OF REDUCING WATER-WAVE NOISE AND SYSTEM THEREOF - A method of reducing a water-wave noise for an analog to digital conversion includes performing sampling on an analog input signal; determining whether the analog input signal is interfered with by a periodic noise such that a water wave is generated; and executing one or both of the following steps when the analog input signal is interfered with by the periodic noise: adjusting a sampling frequency of the ADC, and adjusting a noise frequency of the periodic noise. | 05-01-2014 |
20140197867 | Circuits and Methods for Using a Flying-Adder Synthesizer as a Fractional Frequency Divider - An open loop clock divider circuit includes (a) a first divider configured to receive an incoming clock signal and output a first divided clock signal, (b) a flying-adder synthesizer configured to fractionally divide the first divided clock signal and output a fractionally divided clock signal, and (c) a second divider configured to receive the fractionally divided clock signal and output a second divided clock signal. The open loop clock divider circuit advantageously provides a fractional divider in which there is no feedback loop between the source frequency (f | 07-17-2014 |
Patent application number | Description | Published |
20100053836 | TWO STAGE SURGE PROTECTION FOR SINGLE WIRE MULTI SWITCH TRANSCEIVER - An architecture for protecting circuitry used for signal communications between a frequency translation module ( | 03-04-2010 |
20100071009 | SIX PORT LINEAR NETWORK SINGLE WIRE MULTI SWITCH TRANSCEIVER - A fluid sensor comprises a sensor housing ( | 03-18-2010 |
20100103580 | FREQUENCY TRANSLATION MODULE PROTECTION CIRCUIT - An architecture for protecting circuitry used for signal communications between a frequency translation module and a decoder from transient voltage surges. According to an exemplary embodiment, the apparatus comprises a first signal path between a transmission line and a first reference potential for conducting negative voltage surges between said transmission line and said first reference potential, comprising a first diode and a first clamping diode, wherein a second reference potential is coupled to a junction of the first diode and the first clamping diode, and a second signal path between the transmission line and the first reference potential, comprising a second diode and a second clamping diode for conducting positive voltage surges between said transmission line and said first reference potential, wherein a second reference potential is coupled to a junction of the second diode and the second clamping diode. | 04-29-2010 |
20100105318 | FREQUENCY TRANSLATION MODULE INTERFACE - An architecture and protocol enables signal communications between either a frequency translation module and a decoder within a dwelling, or between an antenna and a decoder within a dwelling. According to an exemplary embodiment, the decoder comprises a switch | 04-29-2010 |
20140078316 | TEST TECHNIQUE FOR SET-TOP BOXES - A test system ( | 03-20-2014 |
20150082358 | METHOD AND APPARATUS FOR TRACKING TRANSMISSION LEVEL OF A HOME NETWORK SIGNAL IN A BROADCAST SIGNAL RECEIVING DEVICE - A method and apparatus for tracking the transmission power level of a home network transmission signal based on the signal level of a received broadcast signal is described. The method includes transmitting a signal at a first transmitted level used for communicating in a home network, detecting a signal level for the transmitted signal in a circuit used for receiving a broadcast signal, determining if a gain setting value for the signal level changes, and adjusting the transmitted signal level for the transmitted signal based on the determination. The apparatus includes a network circuit that transmits a signal at a first transmitted signal level, a detector that detects the transmitted signal in a circuit for receiving a broadcast signal, and a controller that determines if a signal level setting value for the signal level changes and adjusts the transmitted signal level based on the determination. | 03-19-2015 |
20150303889 | APPARATUS AND METHOD FOR FILTERING SINGALS IN A RECEIVER - An apparatus and method for filtering a signal is described. The apparatus includes a first singly terminated filter that filters a signal in a first frequency range, and a second singly terminated filter that filters the signal in a second frequency range, the inputs of the filters being connected together, wherein an element of the first filter is coupled to an additional element to form a frequency response transmission zero in a stopband frequency range of the first filter. The method includes receiving a signal, the signal containing content from a first source in a first frequency range and content from a second source in a second frequency range different than the first range, applying filtering, and applying filtering to generate a second output signal, using filters that include a singly terminated filter section with additional circuit elements to form a transmission frequency zero in the stopband frequency range. | 10-22-2015 |
Patent application number | Description | Published |
20140050264 | Slice base skip mode signaling for multiple layer video coding - Methods and apparatus may be used to signal slice skip mode of a multiple layer scalable coding system. A correlation between the corresponding regions of video signals in multiple layers and inter-layer processing techniques may make it possible to infer a slice or picture in the enhancement layer from the corresponding region in a base layer picture. Accordingly, a video stream may be encoded to indicate that an enhancement layer slice or picture may be skipped. | 02-20-2014 |
20140064374 | METHOD AND APPARATUS OF MOTION VECTOR PREDICTION FOR SCALABLE VIDEO CODING - Inter-layer motion mapping information may be used to enable temporal motion vector prediction (TMVP) of an enhancement layer of a bitstream. For example, a reference picture and a motion vector (MV) of an inter-layer video block may be determined. The reference picture may be determined based on a collocated base layer video block. For example, the reference picture may be a collocated inter-layer reference picture of the reference picture of the collocated base layer video block. The MV may be determined based on a MV of the collocated base layer video block. For example, the MV may be determined by determining the MV of the collocated base layer video block and scaling the MV of the collocated base layer video block according to a spatial ratio between the base layer and the enhancement layer. TMVP may be performed on the enhancement layer picture using the MV of the inter-layer video block. | 03-06-2014 |
20140072031 | Reference Picture Lists Modification - Systems, methods, and instrumentalities are disclosed relating to modifications to reference picture lists used for multiple layer video coding. A bitstream that may include a reference picture list of a slice may be received. An indication to reposition a reference picture within the reference picture list from a first position to a second position may be received. An indication to insert a reference picture within the reference picture list at a position may be received. The reference picture may be repositioned and/or inserted in the reference picture list in response to receiving the indication. A reference picture previously associated with the position may be shifted in the reference picture list according to the indication to reposition and/or insert the reference picture, although an indication to reposition the reference picture previously associated with the position may not be received. The slice may be decoded using the reference picture list. | 03-13-2014 |
20150103886 | HIGH LEVEL SYNTAX FOR HEVC EXTENSIONS - A video coding device may identify a network abstraction layer (NAL) unit. The video coding device may determine whether the NAL unit includes an active parameter set for a current layer. When the NAL unit includes the active parameter set for the current layer, the video coding device may set an NAL unit header layer identifier associated with the NAL unit to at least one of: zero, a value indicative of the current layer, or a value indicative of a reference layer of the current layer. The NAL unit may be a picture parameter set (PPS) NAL unit. The NAL unit may be a sequence parameter set (SPS) NAL unit. | 04-16-2015 |
20150186100 | TWO-DIMENSIONAL PALETTE CODING FOR SCREEN CONTENT CODING - Video data, e.g., screen content video data may be palette coded. A palette table including one or more color indices may be produced. A color index may correspond to one color. A palette index map may be created that maps one or more pixels of the video data to a color index in the palette table, or a color that may be explicitly coded. A palette index map prediction data may be generated that includes data that indicates values in the palette index map associated with at least some portions of the video data that are generated in a traverse scan order in which a scan line is scanned in an opposite direction of a preceding parallel scan line. | 07-02-2015 |
20150264365 | PALETTE CODING FOR SCREEN CONTENT CODING - Video data may be palette decoded. Data defining a palette table may be received. The palette table may comprise index values corresponding to respective colors. Palette index prediction data may be received and may comprise data indicating index values for at least a portion of a palette index map mapping pixels of the video data to color indices in the palette table. The palette index prediction data may comprise run value data associating run values with index values for at least a portion of a palette index map. A run value may be associated with an escape color index. The palette index map may be generated from the palette index prediction data at least in part by determining whether to adjust an index value of the palette index prediction data based on a last index value. The video data may be reconstructed in accordance with the palette index map. | 09-17-2015 |
20150264374 | SYSTEMS AND METHODS FOR RGB VIDEO CODING ENHANCEMENT - Systems, methods, and devices are disclosed for performing adaptive residue color space conversion. A video bitstream may be received and a first flag may be determined based on the video bitstream. A residual may also be generated based on the video bitstream. The residual may be converted from a first color space to a second color space in response to the first flag. | 09-17-2015 |
20150358635 | MOTION INFORMATION SIGNALING FOR SCALABLE VIDEO CODING - Systems, methods and instrumentalities are provided to implement motion information signaling for scalable video coding. A video coding device may generate a video bitstream comprising a plurality of base layer pictures and a plurality of corresponding enhancement layer pictures. The video coding device may identify a prediction unit (PU) of one of the enhancement layer pictures. The video coding device may determine whether the PU uses an inter-layer reference picture of the enhancement layer picture as a reference picture. The video coding device may set motion vector information associated with the inter-layer reference picture of enhancement layer to a value indicative of zero motion, e.g., if the PU uses the inter-layer reference layer picture as the reference picture. | 12-10-2015 |
20150365666 | ENHANCED DEBLOCKING FILTERS FOR VIDEO CODING - Deblocking filters used in video coding systems (e.g., single layer video coding systems or multi-layer video coding systems) may be enhanced. Inter layer prediction for scalable video coding (SVC) may be implemented using enhanced deblocking filters. Enhanced deblocking filters may be configured to be adapted, for example by adjusting a deblocking filter boundary strength calculation process. A deblocking filter boundary strength parameter may be assigned in accordance with, for example, a video block partition size of an input video block or a neighboring video block, whether an input video block or a neighboring video block was predicted using an inter layer reference, and/or whether at least one of an input video block or a neighboring video block have one or more corresponding base layer blocks that were coded using intra mode. | 12-17-2015 |
20150373359 | METHODS AND SYSTEMS FOR INTRA BLOCK COPY SEARCH ENHANCEMENT - In an intra-block copy video encoding method, an encoder performs a hash-based search to identify a selected set of candidate blocks for prediction of an input video block. For each of the candidate blocks in the selected set, the encoder determines a correlation between, on the one hand, luma and chroma components of the input video block and, on the other hand, luma and chroma components of the respective candidate blocks. A predictor block is selected based on the correlation and is used to encode the input video block. In different embodiments, the correlation may be the negative of the sum of absolute differences of the components, may include a Jaccard similarity measure between respective pixels, or may be based on a Hamming distance between two high precision hash values of the input video block and the candidate block. | 12-24-2015 |
20150373366 | METHODS AND SYSTEMS FOR INTRA BLOCK COPY CODING WITH BLOCK VECTOR DERIVATION - Systems and methods are described for encoding and decoding video using derived block vectors as predictors in intra block copy mode. In an exemplary encoding method, an encoder identifies at least a first candidate block vector for the prediction of an input video block, where the first candidate block vector points to a first candidate block. The encoder then identifies a first predictive vector (e.g. a block vector or a motion vector) that was used to encode the first candidate block. From the first candidate block vector and the first predictive vector, the encoder generates a derived predictive vector from the first candidate block vector and the first predictive vector. The encoder then encodes the video block in the bit stream using the derived predictive vector for the prediction of the input video block. | 12-24-2015 |
Patent application number | Description | Published |
20140175634 | METHODS OF PROMOTING ADHESION BETWEEN UNDERFILL AND CONDUCTIVE BUMPS AND STRUCTURES FORMED THEREBY - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein. | 06-26-2014 |
20140177149 | REDUCTION OF UNDERFILL FILLER SETTLING IN INTEGRATED CIRCUIT PACKAGES - Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed. | 06-26-2014 |
20140332966 | EPOXY-AMINE UNDERFILL MATERIALS FOR SEMICONDUCTOR PACKAGES - Epoxy-amine underfill materials for semiconductor packages and semiconductor packages having an epoxy-amine underfill material are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon. A semiconductor package substrate has a surface with a plurality of contact pads thereon. A plurality of conductive contacts couples the surface of the semiconductor die to the surface of the semiconductor package substrate. An epoxy-amine underfill material is disposed between the surface of the semiconductor die and the surface of the semiconductor package substrate and surrounds the plurality of conductive contacts. The epoxy-amine underfill has high adhesion and is based on a low volatility multi-functional amine species. | 11-13-2014 |
20140377916 | METHODS TO PREVENT FILLER ENTRAPMENT IN MICROELECTRONIC DEVICE TO MICROELECTRONIC SUBSTRATE INTERCONNECTION STRUCTURES - Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particles within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures. | 12-25-2014 |
20150179478 | NARROW-GAP FLIP CHIP UNDERFILL COMPOSITION - An underfill composition comprises a curable resin, a plurality of filler particles loaded within the resin, the filler particles comprising at least 50 weight % of the underfill composition. The filler particles comprise first filler particles having a particle size of from 0.1 micrometers to 15 micrometers and second filler particles having a particle size of less than 100 nanometers. A viscosity of the underfill composition is less than a viscosity of a corresponding composition not including the second filler particles. | 06-25-2015 |
20150179479 | METHODS TO PREVENT FILLER ENTRAPMENT IN MICROELECTRONIC DEVICE TO MICROELECTRONIC SUBSTRATE INTERCONNECTION STRUCTURES - Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particless within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures. | 06-25-2015 |