Patent application number | Description | Published |
20100277665 | Display Device with Multiple Display Modules - A display device including a first prism sheet, a second prism sheet disposed side by side with the first prism sheet, a first display module, and a second display module is provided. The first display module is disposed beneath the first prism and has a first display surface. At least a portion of the first display surface close to the second prism sheet is inclined toward the second prism sheet and forms a first angle with respect to the first prism sheet. The second display module is disposed beneath the second prism sheet and has a second display surface. At least a portion of the second display surface closed to the first prism sheet is inclined toward the first prism sheet and forms a first angle with respect to the second prism sheet. | 11-04-2010 |
20130010411 | Display Module and Manufacturing Method Thereof - A display module includes a first housing, a second housing, a display panel, and a glue. The first housing is disposed on the second housing and has a metal sidewall. A first gap exists between the metal sidewall and a sidewall of the first housing. The display panel is disposed on the first housing and has a side surface facing the sidewall, wherein a second gap exists between the side surface and the inner surface. The glue fills the second gap. A manufacturing method of the display module includes disposing the second housing on the first housing and forming the first gap; providing the glue on the inner face of the sidewall and above the first gap; making the display panel push and graze the glue; disposing the display panel on the first housing and forming the second gap, wherein the glue fills the second gap. | 01-10-2013 |
20130263488 | DISPLAY DEVICE AND ASSEMBLY METHOD THEREOF - A display device includes a frame, an adhesive tape, a curing adhesive and a display panel. The frame has a top surface, an inner surface and an outer surface. The top surface is connected between the inner surface and the outer surface. The top surface has a first adhesive region and a second adhesive region which are adjacent to each other. The first adhesive region is located between the inner surface and the second adhesive region. The adhesive tape is adhered to the first adhesive region. The display panel is adhered to the top surface of the frame by the adhesive tape. The curing adhesive is adhered to at least one side surface of the display panel, the second adhesive region and the adhesive tape. A display device assembly method is also provided. | 10-10-2013 |
20130265739 | Display Device with Narrowed Frame Border and Manufacturing Method Thereof - A display device with narrowed frame border and a manufacturing method thereof are provided. The display device includes a backlight module, an optical film, and a display panel. The backlight module includes an outer frame and a light source module. The outer frame has a bottom plate and a sidewall connected to the bottom plate, and the light source module is disposed in the outer frame near the sidewall. The optical film is disposed on the backlight module and covers the light source module. One side of the optical film protrudes outside from the sidewall and is bent to attach a portion of the sidewall. The display panel is disposed on the optical film opposite to the backlight module. | 10-10-2013 |
20140111975 | Light Guide Plate and Backlight Module and Display Module Using the Same - A light guide plate includes a plate body and a supporting unit. The plate body has a light-exiting face and a lateral side, wherein the supporting unit is disposed along the lateral side. The supporting unit has a top surface and an outer lateral surface, the top surface is above the light-exiting face, the lateral surface protrudes from an end surface of the lateral side of the plate body, wherein a portion of the end surface away from the light-exiting face is exposed to form a recess. A backlight module includes the light guide plate mentioned above and a back plate, wherein the light guide plate is disposed on the back plate. A periphery of the back plate has a side wall formed thereon and extending into the recess. A display device includes the light guide plate mentioned above and a display panel, wherein the display panel is disposed on the light guide plate and is supported by the top surface. | 04-24-2014 |
20150055372 | Thin Type Display Module - A display module including a backlight module and a display panel is provided. The backlight module includes a light guide plate and a light source module. The light guide plate has a light incident surface, a light-exiting surface, a light-guiding inclined surface, a bottom surface, and a lateral surface, wherein the light-guiding inclined surface is connected to the light incident surface and the light-exiting surface; the light incident surface, the light-guiding inclined surface, and a portion of the bottom surface constitute a wedge portion while the light-exiting surface, the lateral surface, and other portions of the bottom surface constitute a plate portion. The light source module is disposed at the light incident surface and emits light into the wedge portion. The display panel is disposed on the light guide plate and has a side. The side of the display panel has a projection disposed in the light-guiding inclined surface or the plate portion. | 02-26-2015 |
Patent application number | Description | Published |
20090243500 | LCD and Backlight Module Thereof - A backlight module includes fluorescent lamps, an inverter for supplying power for the lamps, dimming circuits each connecting the lamp in series, a signal processor for converting a video signal into a dimming signal, and a control unit. The lamps are disposed as an array having more than two columns and two rows on a substrate. The control unit electrically connects the signal processor and the dimming circuit and changes the luminance of the lamps by adjusting the dimming circuit according to the dimming signal. | 10-01-2009 |
20100062651 | Multi-Slot Connector and Manufacture Method Thereof - A multi-slot connector and a manufacture method thereof are provided. The multi-slot connector includes a housing and a conducting structure. The conducting structure has a body and a terminal portion extending from the body. After extending out from the body, the terminal portion bends to form a first ridge. After bending the first ridge, the terminal portion turns to form a winding portion which winds back toward the body and bends to form a second ridge, wherein the first and second ridges protrude toward different directions. The housing has a first slot and a second slot. When the conducting structure is disposed in the housing, the first ridge and the second ridge are respectively corresponding to the first slot and the second slot. | 03-11-2010 |
20100097539 | Flat Panel Display and Method for Fabricating the Same - In the specification and drawing a flat panel display with a front cover, a rear cover, a printed circuit board and a display module is disclosed. The rear cover is fixed on the front cover, wherein the rear cover has a printed circuit board region and a panel region. The printed circuit board is locked on the rear cover and corresponding to the printed circuit board region. The display module is fixed on the front cover and corresponding to the panel region, wherein the display module comprise an liquid crystal panel facing the front cover and a back plate facing the rear cover. Moreover, a method for fabricating the flat panel display is also disclosed in the specification and drawing. | 04-22-2010 |
20100141567 | Display Device and Manufacture Method Thereof - The present invention discloses a flat display device and a manufacture method thereof. The flat display device includes a flat display module, a front cover, an auxiliary support, a back cover set, and a circuit board. The back cover set includes a sub-cover and a main back cover, wherein the circuit board is disposed on the inner surface of the sub-cover. The front cover has a display opening for an active area of the flat display module to be exposed outside the display opening and present images through the display opening. The main back cover includes a opening for part of the sub-cover to pass through and be exposed outside the opening. | 06-10-2010 |
20120015562 | Multi-Slot Connector and Manufacture Method Thereof - A multi-slot connector and a manufacture method thereof are provided. The multi-slot connector includes a housing and a conducting structure. The conducting structure has a body and a terminal portion extending from the body. After extending out from the body, the terminal portion bends to form a first ridge. After bending the first ridge, the terminal portion turns to form a winding portion which winds back toward the body and bends to form a second ridge, wherein the first and second ridges protrude toward different directions. The housing has a first slot and a second slot. When the conducting structure is disposed in the housing, the first ridge and the second ridge are respectively corresponding to the first slot and the second slot. | 01-19-2012 |
Patent application number | Description | Published |
20090109440 | Optical Sensor and Operating Method Thereof - The present invention discloses an optical sensor. The optical sensor comprises a sensor for sensing a reflected light, an image capture device coupling with the sensor for reading the reflected light and calculating an average light intensity of the reflected light, a controller coupling with the image capture device for outputting a control signal based on the average light intensity, a driver coupling with the controller for receiving the control signal to output a drive current based on the control signal, and a light source coupling with the driver for receiving the drive current to generate a light. | 04-30-2009 |
20130009913 | HYRBID HUMAN-INTERFACE DEVICE - The present invention discloses a hybrid human-interface device including an optical navigation module and a pointing module. The optical navigation module is configured to replace the conventional buttons of a convention pointing device, such as an optical mouse or a trackball mouse or TV controller. The optical navigation module is configured to sense gestures of at least one object operated by a user to activate commands associated with particular programs running on the host. Since the optical navigation module is only configured to sense gestures of the object but not the movement of the hybrid human-interface device relative to a surface, the resolution thereof is aimed to be sufficiently high enough for sensing gestures and no need to be relatively high. | 01-10-2013 |
20130051439 | FREQUENCY CALIBRATION DEVICE AND METHOD FOR PROGRAMMABLE OSCILLATOR - A frequency calibration method for a programmable oscillator includes the steps of: counting an oversampling number of an oversampling signal and estimating an accumulated bit number of a USB data stream according to the oversampling signal; calculating a difference between the oversampling number and M times of the accumulated bit number when the accumulated bit number is larger than a predetermined value; and determining a frequency calibration step of the oversampling signal according to the difference. The present invention further provides a frequency calibration device for a programmable oscillator. | 02-28-2013 |
20130057473 | MOUSE DEVICE - There is provided a mouse device including a control chip and at least one control component. The control chip includes a voltage detection circuit coupled to the at least one control component through at least one multiplexing pin and detects at least one voltage value on the at least one multiplexing pin using the voltage detection circuit thereby identifying an operating state of the at least one control component. | 03-07-2013 |
20130243242 | User identification system and method for identifying user - The present invention discloses an identification system which includes an image sensor, a storage unit and a comparing unit. The image sensor captures a plurality of images of the motion trajectory generated by a user at different timings. The storage unit has stored motion vector information of a group of users including or not including the user generating the motion trajectory. The comparing unit compares the plurality of images with the motion vector information to identify the user. The present invention also provides an identification method. | 09-19-2013 |
20130285907 | HYBRID HUMAN-INTERFACE DEVICE - The present invention discloses a hybrid human-interface device including an optical navigation module and a pointing module. The optical navigation module is configured to replace the conventional buttons of a convention pointing device, such as an optical mouse or a trackball mouse or TV controller. The optical navigation module is configured to sense gestures of at least one object operated by a user to activate commands associated with particular programs running on the host. Since the optical navigation module is only configured to sense gestures of the object but not the movement of the hybrid human-interface device relative to a surface, the resolution thereof is aimed to be sufficiently high enough for sensing gestures and no need to be relatively high. | 10-31-2013 |
Patent application number | Description | Published |
20110147765 | DUMMY STRUCTURE FOR ISOLATING DEVICES IN INTEGRATED CIRCUITS - The present disclosure provides an integrated circuit. The integrated circuit includes a first operational device having a first transistor of a first composition; a second operational device having a second transistor of the first composition; and an isolation transistor disposed between the first and second transistors, the isolation transistor having a second composition different from the first composition. | 06-23-2011 |
20140176112 | LOW VOLTAGE BANDGAP REFERENCE CIRCUIT - A low voltage bandgap reference circuit includes a positive temperature coefficient circuit unit, a negative temperature coefficient circuit unit and a load unit, wherein the positive temperature coefficient circuit unit comprises a first differential operational amplifier, a first, second and third transistor, a first resistor, a first and second diode, and the negative temperature coefficient circuit unit includes a second differential operational amplifier, a fourth, fifth and sixth transistor, a second resistor and a third diode. The low voltage bandgap reference circuit provides a current having a positive temperature coefficient characteristics and a current having a negative temperature coefficient characteristics to flow through the load unit, whereby generate a stable reference voltage thereon, which the stable reference voltage is less affected by the temperature. Therefore, it avoids the problems of the low voltage bandgap reference circuit can not be activated at low voltage. | 06-26-2014 |
20140337547 | HIGH SPEED DATA TRANSMISSION STRUCTURE - A high-speed data transmission structure includes first and second electronic units and an input/output bus. The input/output bus is electrically connected to the first and second electronic units, and includes a clock signal line and N data lines, where N is an even integer. The data lines are divided into first and second data signal line groups, each provided with the same number of data lines. In a transmit mode, the first electronic unit generates and transmits a clock signal to the clock data line, and generates output signals at each clock period of the clock signal. The output signals consist of N/2 data signals lasting for two clock periods of the clock signal, and the first and second data signal line groups alternatively receive the output signals. The second electronic unit simultaneously performs a receive mode to fetch and latch the data signals according to the clock signal. | 11-13-2014 |
Patent application number | Description | Published |
20110286077 | DISPLAY DEVICE - A display device includes a display panel, a barrier layer, and a sealant. The display panel includes a backplane and a frontplane disposed on the backplane, wherein the frontplane includes a plurality of frontplane sidewalls. The frontplane sidewalls at least include a first frontplane sidewall and a second frontplane sidewall, forming a frontplane concavity. The barrier layer includes a first barrier layer sidewall and a second barrier layer sidewall, wherein the first barrier layer sidewall and the second barrier layer sidewall form a barrier layer concavity. The barrier layer concavity corresponds to the frontplane concavity, and at least one of the barrier layer concavity and the frontplane concavity does not include a right angle. The sealant is disposed in a sealant accommodating space defined by the frontplane sidewalls of the frontplane, an inner surface of the backplane and an inner surface of the barrier layer. | 11-24-2011 |
20110299151 | E-INK DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - An E-ink display device includes an active element array substrate, an E-ink layer, a protective layer and a sealant. The active element array substrate has a surface, and the surface includes a contacting region and a sealing region. The E-ink layer is disposed on the contacting region and has a first side wall, and a first included angle defined between the first side wall and the surface being smaller than 90 degrees or larger than 90 degrees. The protective layer is disposed on the E-ink layer and has a second side wall, and a second included angle defined between the second side wall and the surface is smaller than 90 degrees or larger than 90 degrees. The sealant is disposed on the sealing region and surrounds the E-ink layer and the protective layer. A method for manufacturing the E-ink display device is also provided. | 12-08-2011 |
20120120364 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A display device includes a substrate, a backplane, a display medium layer, a protective layer, a driving component, a flexible printed circuit (FPC) and a sealant. The backplane and the display medium layer are disposed on the lower side and the upper side of the substrate, respectively. The protective layer covers the display medium layer and prevents moisture and oxygen from permeating into the display medium layer to deteriorate its performance. The sealant surrounds the first side surface of the substrate and the second side surface of the display medium layer, and wraps at least a portion of the driving component and a portion of the FPC. Additionally, a manufacturing method of a display device is also provided. | 05-17-2012 |
Patent application number | Description | Published |
20110228187 | LIQUID CRYSTAL DISPLAY PANEL AND RELATED DEVICE - A liquid crystal display panel includes a first substrate, a second substrate, a first electrode, a second electrode, a third electrode, an isolating layer, and a conductor. The first electrode is disposed between the first substrate and the isolating layer, on which the conductor is disposed. Each of the second and third electrodes is disposed on the second substrate and includes a contact surface. The second and third electrodes are not in contact with each other and are separated by a gap. The conductor is disposed in accordance with the location of the gap. | 09-22-2011 |
20110228205 | LIQUID CRYSTAL DISPLAY PANEL AND RELATED DEVICE - A liquid crystal display panel includes a first substrate, a second substrate, a first electrode, a second electrode, a third electrode, an isolating layer, and a conductor. The first electrode is disposed between the first substrate and the isolating layer, on which the conductor is disposed. Each of the second and third electrodes is disposed on the second substrate and includes a contact surface. The second and third electrodes are not in contact with each other and are separated by a gap. The conductor is disposed in accordance with the location of the gap. | 09-22-2011 |
20130057513 | LIQUID CRYSTAL DISPLAY PANEL AND RELATED DEVICE - A liquid crystal display panel includes a first substrate, a second substrate, a first electrode, a second electrode, a third electrode, an isolating layer, and a conductor. The first electrode is disposed between the first substrate and the isolating layer, on which the conductor is disposed. Each of the second and third electrodes is disposed on the second substrate and includes a contact surface. The second and third electrodes are not in contact with each other and are separated by a gap. The conductor is disposed in accordance with the location of the gap. | 03-07-2013 |
Patent application number | Description | Published |
20080212353 | SRAM design with separated VSS - An array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns includes a plurality of VSS lines connected to VSS nodes of the SRAM cells, with each VSS line connected to the SRAM cells in a same column. The plurality of VSS lines includes a first VSS line connected to a first column of the SRAM cells; and a second VSS line connected to a second column of the SRAM cells, wherein the first and the second VSS lines are disconnected from each other. | 09-04-2008 |
20100165707 | Read/Write Margin Improvement in SRAM Design Using Dual-Gate Transistors - An integrated circuit structure includes a static random access memory (SRAM) cell. The SRAM cell includes a pull-up transistor and a pull-down transistor forming an inverter with the pull-up transistor. The pull-down transistor includes a front gate connected to a gate of the pull-up transistor, and a back-gate decoupled from the front gate. | 07-01-2010 |
20100165749 | Sense Amplifier Used in the Write Operations of SRAM - A static random access memory (SRAM) circuit includes a pair of complementary global bit-lines, and a pair of complementary local bit-lines. A global read/write circuit is coupled to, and configured to write a small-swing signal to, the pair of global bit-lines in a write operation. The SRAM circuit further includes a first multiplexer and a second multiplexer, each having a first input and a second input. The first input of the first multiplexer and the first input of the second multiplexer are coupled to different one of the pair of global bit-lines. A sense amplifier includes a first input coupled to an output of the first multiplexer, and a second input coupled to an output of the second multiplexer. The sense amplifier is configured to amplify the small-swing signal to a full-swing signal, and outputs the full-swing signal to the pair of local bit-lines in the write operation. | 07-01-2010 |
20100182865 | Negative-Voltage Generator with Power Tracking for Improved SRAM Write Ability - An integrated circuit structure includes a static random access memory (SRAM) cell; a first power supply node connected to the SRAM cell, wherein the first power supply node is configured to provide a first positive power supply voltage to the SRAM cell; and a bit-line connected to the SRAM cell. A negative-voltage generator is coupled to, and configured to output a negative voltage to, the bit-line, wherein the negative-voltage generator is so configured that the negative voltage decreases in response to a decrease in the first positive power supply voltage and increases in response to an increase in the first positive supply voltage. | 07-22-2010 |
20120250440 | Differential read write back sense amplifier circuits and methods - A differential read write back sense amplifier circuit and corresponding methods. A memory array comprises a plurality of memory cells arranged in rows and columns; a plurality of read word lines coupled to the memory cells; a plurality of write word lines coupled to the memory cells arranged along rows of the memory array; a plurality of read bit line pairs coupled to the memory cells arranged in columns; a plurality of write bit line pairs coupled to the memory cells arranged in columns; and at least one differential read write back sense amplifier coupled to a read bit line pair and coupled to a write bit line pair corresponding to one of the columns of memory cells, configured to differentially sense small signal read data on the read bit line pair, and output the sensed data onto the write bit line pair. Corresponding methods are disclosed. | 10-04-2012 |
Patent application number | Description | Published |
20100181600 | Programmable Transistor Array Design Methodology - A method of designing integrated circuits includes providing a first chip and a second chip identical to each other. Each of the first chip and the second chip includes a base layer including a Logic Transistor Unit (LTU) array. The LTU array includes LTUs identical to each other and arranged in rows and columns. The method further includes connecting the base layer of the first chip to form a first application chip; and connecting the base layer of the second chip to form a second application chip different from the first application chip. | 07-22-2010 |
20100182042 | Circuits and Methods for Programmable Transistor Array - A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other. The arrangement of the BTUs is subject to restricted design rules. Logical transistor units (LTUs) are formed from the BTUs using first and second layers of metallization. Methods for producing integrated circuits are disclosed forming programmable transistor arrays and implementing customer specified system designs upon the programmable transistor arrays. | 07-22-2010 |
20100225002 | Three-Dimensional System-in-Package Architecture - A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. A semiconductor die is manufactured with both via-first TSVs as well as via-last TSVs in order to establish low resistance paths for die connections between adjacent dies as well as for providing a low resistance path for feedthrough channels between multiple dies. | 09-09-2010 |
20100252934 | Three-Dimensional Semiconductor Architecture - A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. TSVs are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment this allows these connections to be made throughout the substrate instead of on the periphery of the substrate. In another embodiment, the TSVs are used as part of a power matrix to supply power and ground connections to the active devices and metallization layers through the substrate. | 10-07-2010 |
20110001249 | Supplying Power to Integrated Circuits Using a Grid Matrix Formed of Through-Silicon Vias - An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M | 01-06-2011 |
20110084365 | Through Silicon Via (TSV) Wire Bond Architecture - A through silicon via architecture for integrated circuits is provided. The integrated circuit (IC) includes a substrate with a top surface and a bottom surface with circuitry formed on the top surface, a plurality of bonding pads formed along a periphery of the bottom surface, and a backside metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads. A first subset of bonding pads in the plurality of bonding pads is electrically coupled to circuitry on the top surface with through silicon vias (TSV). The BML distributes electrical signals provided by the second subset of bonding pads. | 04-14-2011 |
20120290996 | Supplying Power to Integrated Circuits Using a Grid Matrix Formed of Through-Silicon Vias - An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M | 11-15-2012 |
20130088259 | Circuits and Methods for Programmable Transistor Array - A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other. The arrangement of the BTUs is subject to restricted design rules. Logical transistor units (LTUs) are formed from the BTUs using first and second layers of metallization. Additional embodiments are disclosed incorporating the programmable transistor array circuit. | 04-11-2013 |
20130230985 | Three-Dimensional System-in-Package Architecture - A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. A semiconductor die is manufactured with both via-first TSVs as well as via-last TSVs in order to establish low resistance paths for die connections between adjacent dies as well as for providing a low resistance path for feedthrough channels between multiple dies. | 09-05-2013 |
20130316530 | Three-Dimensional Semiconductor Architecture - A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. TSVs are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment this allows these connections to be made throughout the substrate instead of on the periphery of the substrate. In another embodiment, the TSVs are used as part of a power matrix to supply power and ground connections to the active devices and metallization layers through the substrate. | 11-28-2013 |
20140264941 | Three-Dimensional Semiconductor Architecture - A system and method for making semiconductor die connections with through-substrate vias are disclosed. Through substrate vias are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment the substrate has an interior region and a periphery region surrounding the interior region. A first set of through substrate vias are located within the periphery region, and a second set of through substrate vias are located within the interior region, wherein the second set of through substrate vias are part of a power matrix. The second set of through substrate vias bisect the substrate into a first part and a second part. | 09-18-2014 |
Patent application number | Description | Published |
20100053060 | Control Signal Generation Method of Integrated Gate Driver Circuit Integrated Gate Driver Circuit and Liquid Crystal Display Device - A control signal generation method of integrated gate driver circuit includes the steps of: providing one gate control signal to an integrated gate driver circuit; and generating a plurality of internal control signals by the integrated gate driver circuit according to on the gate control signal to control internal operations of the integrated gate driver circuit. Furthermore, an integrated gate driver circuit is adapted to receive one external gate control signal. The integrated gate driver circuit includes an internal control signal generation circuit for generating a plurality of internal control signals according to the external gate control signal to control internal operations of the integrated gate driver circuit. In addition, a liquid crystal display device using the above-mentioned integrated gate driver circuit also is provided. | 03-04-2010 |
20110227892 | DRIVING APPARATUS FOR DRIVING A DISPLAY PANEL AND SOURCE DRIVER THEREOF - A driving apparatus for driving a display panel includes a timing controller and a plurality of source drivers. The timing controller has a first output port and a second output port. The first output port is employed to output a first clock signal and plural first data signals. The second output port is employed to output a second clock signal and plural second data signals. Each source driver includes at least two operation mode control ends for receiving an operation mode control signal having at least two bits for setting at least first to third operation modes. If the operation mode control signal sets the source driver to operate in the first operation mode, the source driver is electrically connected to both the first and second output ports, for driving the display panel according to the first data signals, the second data signals, the first clock and the second clock. | 09-22-2011 |
20120105500 | PIXEL-DRIVING CIRCUIT - A pixel driving circuit includes a first pixel, a second pixel, and a data driving circuit. Each pixel includes a main region and a sub region. The main region stores a gray level voltage and the sub region stores a gray level voltage corresponding to the gray level voltage stored in the main region when the main region and the sub region display image. In the data driving circuit, first, second, third, and fourth gray level voltages are generated by means of a first selecting circuit outputting first digital data corresponding to the first pixel and second digital data corresponding to the second pixel to the corresponding digital-to-analog converters. The first, second, third, and fourth gray level voltages are distributed to the main and sub regions of the first and second pixels by a second selecting circuit, thereby reducing the number of digital-to-analog converters. | 05-03-2012 |
20120169708 | CONTROL CIRCUIT OF DISPLAY PANEL AND CONTROL METHOD OF THE SAME - A control circuit for driving a display panel is disclosed. The control circuit includes a timing controller, outputting a timing control signal; and a driving module, electrically coupled to the timing controller and the display panel for driving the display panel in response to the timing control signal, and the timing controller is switchable to a modifying state according to a driving condition of the driving module. A control method for driving a display panel is also disclosed. | 07-05-2012 |
20130127806 | DISPLAY PANEL AND METHOD FOR DRIVING THE SAME - A display panel includes a switch control circuit, a first pre-charge switch circuit and a second pre-charge switch circuit. The switch control circuit is used for comparing the most significant bits (MSBs) of data signals to generate switch control signals for controlling the first and second pre-charge switch circuits, such that data lines are pre-charged through the first and second pre-charge switch circuits respectively. A method for driving a display panel is also provided herein. | 05-23-2013 |
20140078190 | DISPLAY-DRIVING STRUCTURE AND SIGNAL TRANSMISSION METHOD THEREOF AND MANUFACTURING METHOD THEREOF - A display-driving structure for driving a display panel is disclosed. The display-driving structure includes a first circuit board, a second circuit board, a transmission wiring, a first circuit, a second circuit, first source driver circuits and second source driver circuits. The transmission wiring is connected between the first circuit board and the second circuit board. The first circuit is disposed on the first circuit board for generating a first signal. The second circuit is disposed on the second circuit board for generating a second signal. The first source driver circuits receive the first signal from the first circuit board, and further receive the second signal via the transmission wiring and the second circuit board. The second source driver circuits receive the second signal from the second circuit board, and further receive the first signal via the transmission wiring and the first circuit board. | 03-20-2014 |
Patent application number | Description | Published |
20100099211 | Method of forming a display panel - A method of forming a display panel includes providing a first substrate having a transparent electrode, and a second substrate having a pixel electrode. Subsequently, an alignment material is provided and covers on the transparent electrode and/or the pixel electrode, and a photoelectric twisting layer is provided between the first substrate and the second substrate. The alignment material is first in a non-aligned state, and is radiation-polymerizable. The photoelectric twisting layer does not include any radiation-polymerizable material. Thereafter, a voltage difference is applied to drive molecules of the photoelectric twisting layer, and a radiating process is performed on the alignment material. The twisted molecules of the photoelectric twisting layer induce the surface molecules of the alignment material to arrange in an ordered state, and the alignment material is polymerized according to the ordered state as a first alignment film. | 04-22-2010 |
20140009457 | LIQUID CRYSTAL DISPLAY PANEL AND DISPLAY DRIVING METHOD - A liquid crystal display panel and a display driving method are disclosed. The liquid crystal display panel includes several pixel units, several scan lines, several common electrode lines coupled with the pixel units and several common electrode control units. The common electrode control units are configured for controlling the voltage levels of the common electrode lines. Each one of the common electrode control units generates a first output signal and a second output signal opposite to the first output signal according to the former common electrode controlling unit and two adjacent scan lines. The to common electrode controlling unit controls a voltage level on one of the common electrode lines according to the first output signal, and outputs the first output signal and the opposite second output signal to the next common electrode control unit. | 01-09-2014 |
20140252964 | DISPLAY DEVICE AND COMMON VOLTAGE GENERATOR THEREOF - A voltage generator includes a latch and a first voltage adjustment circuit. The latch includes a latch input terminal, a trigger terminal, a positive latch output terminal and a negative latch output terminal. The latch is configured to have the latch input terminal thereof for receiving an input signal, the trigger terminal thereof for receiving a trigger signal, the positive latch output terminal thereof for outputting a first latch output signal having a phase same as that of the input signal, and the negative latch output terminal thereof for outputting a second latch output signal having a phase opposite to that of the input signal. The first voltage adjustment circuit is electrically coupled to the latch and configured to output a first common voltage signal. A display device using the aforementioned voltage generator is also provided. | 09-11-2014 |
Patent application number | Description | Published |
20090167212 | Driving Circuit and Method for Preventing Lamp from Blasting - In a driving circuit and method for preventing a lamp from blasting, a driving circuit includes a control circuit module, a voltage conversion circuit module, a driving module and a feedback circuit. The control circuit module outputs a first control signal according to a predetermined setting. The voltage conversion circuit module receives the first control signal and converts the first control signal into a second control signal. The driving module receives the second control signal and generates a driving signal according to the second control signal for driving the lamp. The feedback circuit electrically couples to one of the control circuit module, the voltage conversion circuit module and the driving module for receiving a feedback signal therefrom. The feedback signal is transmitted to the control circuit module, so that the control circuit module may adjust the first control signal according to the feedback signal. | 07-02-2009 |
20100004767 | Method for Controlling Projector and Projection System using the same - In a method for controlling projector and a projection system using the same, the method is adapted to a projector. The projector receives a multimedia data from a host and through a multimedia-data transmitting interface. The projector judges whether the multimedia data includes a predetermined data in advance, and then performs an operation for controlling the projector corresponding to the predetermined data if the multimedia data includes the predetermined data. | 01-07-2010 |
20120032776 | ELECTRONIC SYSTEM AND METHOD OF CONTROLLING THE SAME - An electronic system and a method of controlling the same are provided. The electronic system has an electronic device and a remote controller. The electronic device has a storage unit for storing a first password. The remote controller is used to control the operations of the electronic device. When a switch module of the remote controller is pressed, the remote controller generates a power on signal. The power on signal has a power on command and a second password. When the first password and the second password are the same, the electronic device is permitted to complete a power on operation according to the power on command. Accordingly, the electronic system has an anti-theft function. | 02-09-2012 |
20120228479 | CONTROL CIRCUIT AND OPERATION METHOD FOR PROJECTOR - A control circuit is applied into a projector and an operation method is provided for the projector. The projector includes a photo sensor provided for generating a sensing voltage according to light intensity sensed by the photo sensor. The control circuit includes a first voltage-comparing unit, a reference voltage generating unit and a second voltage-comparing unit. The first voltage-comparing unit is provided for comparing the sensing voltage and a first reference voltage, to generate a first comprising result. The reference-voltage generating unit is provided for generating a second reference voltage and determining whether adjusting the second reference voltage according to the first comparing result. The second reference voltage is relatively larger than the first reference voltage. The second voltage-comparing unit is provided for comparing the sensing voltage and the second reference voltage, to generate a second comparing result. | 09-13-2012 |
Patent application number | Description | Published |
20120199966 | Elongated Bump Structure for Semiconductor Devices - An elongated bump structure for semiconductor devices is provided. An uppermost protective layer has an opening formed therethrough. A pillar is formed within the opening and extending over at least a portion of the uppermost protective layer. The portion extending over the uppermost protective layer exhibits a generally elongated shape. In an embodiment, the position of the opening relative to the portion of the bump structure extending over the uppermost protective layer is such that a ratio of a distance from an edge of the opening to an edge of the bump is greater than or equal to about 0.2. In another embodiment, the position of the opening is offset relative to center of the bump. | 08-09-2012 |
20120299181 | Package-on-Package Process for Applying Molding Compound - A method of packaging includes placing a package component over a release film, wherein solder balls on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder balls remain in physical contact with the release film. | 11-29-2012 |
20120329264 | Reflow System and Method for Conductive Connections - A system and method for forming conductive connections is disclosed. An embodiment comprises forming conductive material on to contacts of a semiconductor substrate. The semiconductor substrate is then inverter such that the conductive material is beneath the semiconductor substrate, and the conductive material is reflowed to form a conductive bump. The reflow is performed using gravity in order to form a more uniform shape for the conductive bump. | 12-27-2012 |
20130009303 | Connecting Function Chips To A Package To Form Package-On-Package - A package-on-package (PoP) comprises a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of bond-on-trace connections, and a second function chip on top of the first function chip, directly connected to the substrate. Another package-on-package (PoP) comprises: a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of solder mask defined (SMD) connections formed on SMD bonding pads connected to solder bumps, and a second function chip on top of the first function chip, directly connected to the substrate by a plurality of bond-on-trace connections. | 01-10-2013 |
20130043583 | Dummy Flip Chip Bumps for Reducing Stress - A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. | 02-21-2013 |
20130062741 | Semiconductor Devices and Methods of Manufacturing and Packaging Thereof - Semiconductor devices and methods of manufacturing and packaging thereof are disclosed. In one embodiment, a semiconductor device includes an integrated circuit and a plurality of copper pillars coupled to a surface of the integrated circuit. The plurality of copper pillars has an elongated shape. At least 50% of the plurality of copper pillars is arranged in a substantially centripetal orientation. | 03-14-2013 |
20130256874 | Elongated Bumps in Integrated Circuit Devices - A device includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. The passivation layer has a first opening overlapping the metal pad, wherein the first opening has a first lateral dimension measured in a direction parallel to a major surface of the substrate. A polymer layer is over the passivation layer and covering the edge portions of the metal pad. The polymer layer has a second opening overlapping the metal pad. The second opening has a second lateral dimension measured in the direction. The first lateral dimension is greater than the second lateral dimension by more than about 7 μm. A Under-Bump metallurgy (UBM) includes a first portion in the second opening, and a second portion overlying portions of the polymer layer. | 10-03-2013 |
20130270693 | Trace Layout Method in Bump-on-Trace Structures - A method and device for preventing the bridging of adjacent metal traces in a bump-on-trace structure. An embodiment comprises determining the coefficient of thermal expansion (CTE) and process parameters of the package components. The design parameters are then analyzed and the design parameters may be modified based on the CTE and process parameters of the package components. | 10-17-2013 |
20130270699 | Conical-Shaped or Tier-Shaped Pillar Connections - A pillar structure for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled. | 10-17-2013 |
20140077360 | Interconnection Structure and Method of Forming Same - An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion. | 03-20-2014 |
20140159232 | Apparatus and Method for Three Dimensional Integrated Circuits - A structure comprises a substrate comprising a plurality of traces on top of the substrate, a plurality of connectors formed on a top surface of a semiconductor die, wherein the semiconductor die is formed on the substrate and coupled to the substrate through the plurality of connectors and a dummy metal structure formed at a corner of a top surface of the substrate, wherein the dummy metal structure has two discontinuous sections. | 06-12-2014 |
20140186591 | Solder Mask Shape for BOT Laminate Packages - A device is provided. The device may comprise an integrated circuit package. The integrated circuit package may comprise a first layer and a solder mask. The first layer may comprise a top surface wherein the solder mask is disposed on the top surface of the first layer. The solder mask may comprise a vertical edge. The vertical edge may form an angle between the top surface of the first layer and the vertical edge of not less than 90 degrees. The angle may be not less than 120 degrees or not less than 150 degrees. | 07-03-2014 |
20140291838 | Design Scheme for Connector Site Spacing and Resulting Structures - A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad. | 10-02-2014 |
20140346673 | Methods and Apparatus for bump-on-trace Chip Packaging - Methods and apparatuses for a attaching a first substrate to a second substrate are provided. In some embodiments, a first substrate has a protective layer, such as a solder mask, around a die attach area, at which a second substrate is attached. A keep-out region (e.g., an area between the second substrate and the protective layer) is a region around the second substrate in which the protective layer is not formed or removed. The keep-out region is sized such that a sufficient gap exists between the second substrate and the protective layer to place an underfill between the first substrate and the second substrate while reducing or preventing voids and while allowing traces in the keep-out region to be covered by the underfill. | 11-27-2014 |
Patent application number | Description | Published |
20110241217 | Multi-Layer Interconnect Structure for Stacked Dies - A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements. | 10-06-2011 |
20110278732 | Interconnect Structures for Substrate - A device for use with integrated circuits is provided. The device includes a substrate having a through-substrate via formed therethrough. Dielectric layers are formed over at least one side of the substrate and metallization layers are formed within the dielectric layers. A first metallization layer closest to the through-substrate via is larger than one or more overlying metallization layers. In an embodiment, a top metallization layer is larger than one or more underlying metallization layers. Integrated circuit dies may be attached to the substrate on either or both sides of the substrate, and either side of the substrate may be attached to another substrate, such as a printed circuit board, a high-density interconnect, a packaging substrate, an organic substrate, a laminate substrate, or the like. | 11-17-2011 |
20120074562 | Three-Dimensional Integrated Circuit Structure with Low-K Materials - A device includes an interposer free from active devices therein. The interposer includes a substrate; a through-substrate via (TSV) penetrating through the substrate; and a low-k dielectric layer over the substrate. | 03-29-2012 |
20120083116 | Cost-Effective TSV Formation - A device includes a substrate having a first surface, and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the substrate. A dielectric layer is disposed over the substrate. A metal pad is disposed in the dielectric layer and physically contacting the TSV, wherein the metal pad and the TSV are formed of a same material, and wherein no layer formed of a material different from the same material is between and spacing the TSV and the metal pad apart from each other. | 04-05-2012 |
20130001783 | Interconnect Barrier Structure and Method - A system and method for forming through substrate vias is provided. An embodiment comprises forming an opening in a substrate and lining the opening with a first barrier layer. The opening is filled with a conductive material and a second barrier layer is formed in contact with the conductive material. The first barrier layer is formed with different materials and different methods of formation than the second barrier layer so that the materials and methods may be tuned to maximize their effectiveness within the device. | 01-03-2013 |
20130001799 | Multi-Layer Interconnect Structure for Stacked Dies - A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements. | 01-03-2013 |
20130023065 | Apparatus and Methods for End Point Determination in Reactive Ion Etching - Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed. | 01-24-2013 |
20130024019 | APPARATUS AND METHODS FOR END POINT DETERMINATION IN SEMICONDUCTOR PROCESSING - Methods and apparatus for performing end point determination are disclosed. An embodiment includes an apparatus comprising a process tool and a programmable processor. The process tool has an output for signaling in-situ measurements of physical parameters during processing of a wafer in the process tool, and the process tool has an input for receiving a signal indicating a modification of a recipe for the processing. The programmable processor is for executing a virtual metrology model of the process tool to estimate an estimated characteristic of the wafer achieved during the processing. The estimated characteristic is based on the in-situ measurements and the virtual metrology model. The programmable processor has an output for transmitting the signal when the estimated characteristic exceeds a predetermined threshold based on a target characteristic. | 01-24-2013 |
20130140690 | TSV Structures and Methods for Forming the Same - A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad. | 06-06-2013 |
20130316528 | Interconnect Barrier Structure and Method - A system and method for forming through substrate vias is provided. An embodiment comprises forming an opening in a substrate and lining the opening with a first barrier layer. The opening is filled with a conductive material and a second barrier layer is formed in contact with the conductive material. The first barrier layer is formed with different materials and different methods of formation than the second barrier layer so that the materials and methods may be tuned to maximize their effectiveness within the device. | 11-28-2013 |
20140061924 | Interconnect Structure and Method - An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line and a dielectric layer formed over the first metallization layer, wherein the dielectric layer comprises a metal structure having a bottom surface coplanr with a top surface of the first metal line. | 03-06-2014 |
20140077374 | Through Via Structure and Method - An apparatus comprises a through via formed in a substrate. The through via is coupled between a first side and a second side of the substrate. The through via comprises a bottom portion adjacent to the second side of the substrate, wherein the bottom portion is formed of a conductive material. The through via further comprises sidewall portions formed of the conductive material and a middle portion formed between the sidewall portions, wherein the middle portion is formed of a dielectric material. | 03-20-2014 |
20140117564 | Interconnect Structures for Substrate - A device for use with integrated circuits is provided. The device includes a substrate having a through-substrate via formed therethrough. Dielectric layers are formed over at least one side of the substrate and metallization layers are formed within the dielectric layers. A first metallization layer closest to the through-substrate via is larger than one or more overlying metallization layers. In an embodiment, a top metallization layer is larger than one or more underlying metallization layers. Integrated circuit dies may be attached to the substrate on either or both sides of the substrate, and either side of the substrate may be attached to another substrate, such as a printed circuit board, a high-density interconnect, a packaging substrate, an organic substrate, a laminate substrate, or the like. | 05-01-2014 |
20140264834 | Low Cost and Ultra-Thin Chip on Wafer on Substrate (CoWoS) Formation - Methods of making and an integrated circuit device. An embodiment method includes patterning a first polymer layer disposed over a first copper seed layer, electroplating a through polymer via in the first polymer layer using the first copper seed layer, a via end surface offset from a first polymer layer surface, forming a second polymer layer over the first polymer layer, the second polymer layer patterned to expose the via end surface, and electroplating an interconnect in the second polymer layer to cap the via end surface using a second copper seed layer. | 09-18-2014 |
20140342547 | TSV Structures and Methods for Forming the Same - A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad. | 11-20-2014 |
20150035159 | SEMICONDUCTOR DEVICE HAVING BACKSIDE INTERCONNECT STRUCTURE ON THROUGH SUBSTRATE VIA AND METHOD OF FORMING THE SAME - A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer. | 02-05-2015 |
20150054174 | Interconnection Structure with Confinement Layer - An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad. | 02-26-2015 |
20150061147 | Device with Through-Substrate Via Structure and Method for Forming the Same - A device including a first dielectric layer on a semiconductor substrate, a gate electrode formed in the first dielectric layer, and a through-substrate via (TSV) structure penetrating the first dielectric layer and extending into the semiconductor substrate. The TSV structure includes a conductive layer, a diffusion barrier layer surrounding the conductive layer and an isolation layer surrounding the diffusion barrier layer. A capping layer including cobalt is formed on the top surface of the conductive layer of the TSV structure. | 03-05-2015 |
Patent application number | Description | Published |
20110241202 | Dummy Metal Design for Packaging Structures - An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad. | 10-06-2011 |
20120178252 | Dummy Metal Design for Packaging Structures - A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern. | 07-12-2012 |
20120305916 | Interposer Test Structures and Methods - An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads. | 12-06-2012 |
20130092231 | PHOTOVOLTAIC PACKAGE - A photovoltaic package includes a substrate, a photovoltaic cell, an electric device, a cover, and an encapsulating material. The photovoltaic cell is disposed on the substrate. The electric device is disposed on the substrate and is electrically connected to the photovoltaic cell. The cover covers the substrate, the photovoltaic cell, and the electric device. The cover has a first depression formed therein. The first depression receives at least a portion of the electric device. The encapsulating material is located between the substrate and the cover. The encapsulating material at least partially encapsulates the photovoltaic cell and the electric device. | 04-18-2013 |
20130092935 | Probe Pad Design for 3DIC Package Yield Analysis - An interposer includes a first surface on a first side of the interposer and a second surface on a second side of the interposer, wherein the first and the second sides are opposite sides. A first probe pad is disposed at the first surface. An electrical connector is disposed at the first surface, wherein the electrical connector is configured to be used for bonding. A through-via is disposed in the interposer. Front-side connections are disposed on the first side of the interposer, wherein the front-side connections electrically couple the through-via to the probe pad. | 04-18-2013 |
20130113070 | Interposers for Semiconductor Devices and Methods of Manufacture Thereof - Interposers for semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, an interposer includes a substrate, a contact pad disposed on the substrate, and a first through-via in the substrate coupled to the contact pad. A first fuse is coupled to the first through-via. A second through-via in the substrate is coupled to the contact pad, and a second fuse is coupled to the second through-via. | 05-09-2013 |
20130120018 | Test Structure and Method of Testing Electrical Characteristics of Through Vias - A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV. | 05-16-2013 |
20130284230 | SOLAR CELL MODULE, ELECTRONIC DEVICE HAVING THE SAME, AND MANUFACTURING METHOD FOR SOLAR CELL - A solar cell module is provided and includes a first solar cell and a second solar cell. The first solar cell includes a first metal substrate, a first photoelectric conversion layer, a first top electrode layer, a first P-N junction semiconductor, and a first bottom electrode layer. The second solar cell includes a second metal substrate, a second photoelectric conversion layer, a second top electrode layer, a second P-N junction semiconductor, and a second bottom electrode layer. The first photoelectric conversion layer and the first P-N junction semiconductor are respectively located on two opposite sides of the first metal substrate. The second photoelectric conversion layer and the second P-N junction semiconductor are respectively located on two opposite sides of the second metal substrate. The second bottom electrode layer is located on the second P-N junction semiconductor, and is electrically coupled to the first metal substrate. | 10-31-2013 |
20130285636 | POWER TRACKING DEVICE AND POWER TRACKING METHOD - A power tracking device and a power tracking method is disclosed herein. The power tracking device includes a power voltage setting circuit, a switch, a switching signal circuit, and a voltage memory circuit. The switching signal circuit is configured for sending a first control signal to the switch. When the switch receives the first control signal and electrically isolates the power source and the power voltage setting circuit, the voltage memory circuit stores an open circuit voltage of the power source and sends a setting voltage relative to the open circuit voltage, and when the switch receives the first control signal and electrically connects the power source and the power voltage setting circuit, the power voltage setting circuit sets an output voltage of the power source to correspond with the setting voltage. | 10-31-2013 |
20130293011 | SOLAR POWER SYSTEM, SOLAR CELL MODULE AND POWER PROVIDING METHOD THEREOF - A solar power system includes a solar cell module, a main system and at least one sub system. The solar cell module includes at least one first solar cell unit and one second solar cell unit coupled in series. The first solar cell unit is configured to have an available maximum output current greater than that of the second solar cell unit. The main system is electrically coupled to the solar cell module and simultaneously supplied with electrical power by the first solar cell unit and the second solar cell unit both. The at least one sub system is electrically coupled to the solar cell module and supplied with electrical power by the first solar cell unit only. A solar cell module and a power providing method thereof are also provided. | 11-07-2013 |
20140106536 | Cylindrical Embedded Capacitors - A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate. | 04-17-2014 |
20140266283 | Chip-on-Wafer Process Control Monitoring for Chip-on-Wafer-on-Substrate Packages - An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure. | 09-18-2014 |
20150048503 | Packages with Interposers and Methods for Forming the Same - A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias. | 02-19-2015 |
Patent application number | Description | Published |
20120162173 | DRIVING METHOD FOR A LIQUID CRYSTAL DISPLAY - A driving method for a liquid crystal display includes providing a first gate pulse to a first gate line for driving adjacent first and second subpixels to perform charging operations, providing a second gate pulse to a second gate line for driving adjacent third and fourth subpixels to perform charging operations, providing a third gate pulse to a third gate line for driving the second subpixel to perform a charge-sharing operation, and providing a fourth gate pulse to a fourth gate line for driving the fourth subpixel to perform a charge-sharing operation. The first and second gate lines are spaced out at least one gate line. The third gate line is adjacent to the first gate line. The fourth gate line is adjacent to the second gate line. The first gate pulse, the second gate pulse, the third gate pulse and the fourth gate pulse are sequentially triggered. | 06-28-2012 |
20120320099 | PIXEL CIRCUIT AND FLAT DISPLAY PANEL USING THE SAME - An exemplary pixel circuit and a flat display panel using the same are provided. The pixel circuit includes three sub-electrode control circuits. The sub-electrode control circuits are controlled by two scan lines to receive data transmitted from two data lines. One of the three sub-electrode control circuits adjusts stored data by charge sharing. Accordingly, a display control of the pixel circuit is achieved by the three sub-electrode control circuits. | 12-20-2012 |
20130044090 | SUB-PIXEL CIRCUIT, DISPLAY PANEL AND DRIVING METHOD OF FLAT DISPLAY PANEL - A sub-pixel circuit, display panel and driving method of the display panel are provided. The display panel has a plurality of data lines, scan lines and sub-pixel circuits. At least one of the sub-pixel circuits is electrically coupled to one data line and three scan lines. The sub-pixel circuit determines whether to receive data from the coupled data line or not according to scan signals transmitted on the coupled three scan lines, and controls transmittance itself accordingly. Specifically, the scan signals transmitted on the coupled three scan lines are different from each other. | 02-21-2013 |
Patent application number | Description | Published |
20120133598 | TOUCH DISPLAY DEVICE - A touch display device includes a display panel, a light guide plate, at least an invisible light emitting device, and a first light path converting device. The light guide plate includes a plurality of microstructures to reflect an invisible light generated by the invisible light emitting device such that the invisible light passes through the display panel, reaching the first light path converting device. | 05-31-2012 |
20120170315 | Three-Dimensional Display Apparatus and Backlight Module Thereof - A three-dimensional display apparatus and a backlight module thereof are provided. The display apparatus further includes a display panel disposed on the backlight module. The backlight module has a light guide plate, a plurality of microstructures, a first light source, and a second light source. The light guide plate has a bottom surface and a light emitting surface opposite to the bottom surface, wherein the microstructures are disposed on at least one of the two surfaces. The first light source is at a first corner of the light guide plate while the second light source is at a second corner opposite to the first corner. A first surface and a second surface of the microstructure define an orientation direction (or form a distribution direction) along or parallel to the diagonal line through the first and second corners. | 07-05-2012 |
20130094243 | Sheetless Backlight Module, A Light Guide Plate for the Sheetless Backlight and Manufacturing Method Thereof - A sheetless backlight module and a light guide plate thereof are provided. The light guide plate includes a body and a plurality of light scattering units. The body has a bottom and a plurality of microstructures formed on the bottom and recessed in the body from the bottom. The pluralities of light scattering units are disposed in a plurality of spaces formed due to the plurality of microstructures recessed in the body. A manufacturing method of the light guide plate mentioned above includes forming the plurality of microstructures on the bottom of the body; preparing a fluid solution containing at least a diffusive reflective material; distributing the fluid solution on the bottom; driving the fluid solution to flow into the microstructures; removing the part of the fluid solution outside the microstructures; and solidifying the fluid solution to form the plurality of light scattering units. | 04-18-2013 |
20130188393 | BACKLIGHT MODULE - A backlight module includes a light guide plate, a light coupling unit and a plurality of light emitting devices. The light guide plate has a light incident side. The light coupling unit includes a plurality of light coupling devices arranged in a side-by-side manner. Each light coupling device has a first side and a second side, and the first and second sides are opposite to each other. The second side is adjacent to the light incident side. Each light coupling device is configured to have a thickness gradually decreasing from the first side toward the second side. The light emitting devices are disposed beside the first sides of the light coupling devices. Another backlight module is also provided. | 07-25-2013 |
Patent application number | Description | Published |
20120097246 | SOLAR CELL AND METHOD OF MAKING THE SAME - A solar cell includes a crystalline semiconductor substrate; a first crystalline semiconductor layer; an amorphous semiconductor layer; a first metal electrode layer and a second metal electrode layer. The crystalline semiconductor substrate has a first surface and a second surface, and the crystalline semiconductor substrate has a first doped type. The first crystalline semiconductor layer is disposed on the first surface of the crystalline semiconductor substrate, where the first crystalline semiconductor layer has a second doped type contrary to the first doped type. The amorphous semiconductor layer is disposed on the first crystalline semiconductor layer, and the amorphous semiconductor layer has the second doped type. The first metal electrode layer is disposed on the amorphous semiconductor layer. The second metal electrode layer is disposed on the second surface of the crystalline semiconductor substrate. | 04-26-2012 |
20120167966 | SOLAR CELL AND METHOD OF FABRICATING THE SAME - A solar cell includes a semiconductor base, a first doped semiconductor layer, an insulating layer, a second doped semiconductor layer and a first electrode layer. The semiconductor base has a first doped type. The first doped semiconductor layer, disposed on the semiconductor base, has a doped contact region. The insulating layer is disposed on the first doped semiconductor layer, exposing the doped contact region. The second doped semiconductor layer is disposed on the insulating layer and the doped contact region. The first doped semiconductor layer, the doped contact region and the second doped semiconductor layer have a second doped type, and a dopant concentration of the second doped semiconductor layer is between that of the first doped semiconductor layer and that of the doped contact region. The first electrode layer is disposed corresponding to the doped contact region. | 07-05-2012 |
20130167919 | SOLAR CELL HAVING BURIED ELECTRODE - Disclosed herein is a solar cell, which includes a first electrode, a buried electrode, a photoelectric conversion layer and a second electrode. The buried electrode is disposed on the first electrode. The photoelectric conversion layer is disposed over the first electrode and the buried electrode. The buried electrode is embedded in the photoelectric conversion layer. The second electrode is arranged in a way such that the photoelectric conversion layer is positioned between the first electrode and the second electrode. | 07-04-2013 |
20130192658 | SOLAR PANEL MODULE - A solar panel module includes a solar panel, a supporting stand and a deflecting device. The supporting stand is structurally connected to the solar panel for supporting the solar panel. The solar panel is disposed inclinedly, and the solar panel has a tilt angle with respect to a horizontal plane. The deflecting device is disposed underneath the solar panel for deflecting wind blowing from lateral directions toward a wind exiting direction, which faces a bottom surface of the solar panel. | 08-01-2013 |
20130312820 | SOLAR CELL AND MANUFACTURING METHOD THEREOF - A solar cell includes a semiconductor substrate and a first antireflective layer. The semiconductor substrate has a first-type semiconductor surface and a second-type semiconductor surface opposite to each other. The first antireflective layer includes a plurality of refraction convexes and a coverage layer. The refraction convexes are formed on the second-type semiconductor surface. Each refraction convex includes a first refraction part and a second refraction part. The first refraction parts are conformally coated with the respective second refraction parts, and the first refraction part is configured to have a refractive index greater than the refractive index of the second refraction part. The coverage layer is formed to cover the second-type semiconductor surface and the refraction convexes, and the coverage layer is configured to have a refractive index smaller than the refractive index of the second refraction part. A solar cell manufacturing method is also provided. | 11-28-2013 |
20140048129 | SOLAR CELL AND FABRICATING METHOD THEREOF - A solar cell includes a substrate. The substrate has a light-receiving surface and a back surface opposite to the light-receiving surface. The substrate includes plural trenches formed on the back surface. The solar cell includes plural n-type diffusion areas and plural p-type diffusion areas alternately disposed on the back surface and the surface of the trenches. The possibility of recombination of the electron-hole pair while moving can be reduced because of the trenches, which are formed in the substrate. | 02-20-2014 |
20140060629 | SOLAR CELL AND METHOD FOR FABRICATING THE SAME - A solar cell includes a substrate, a first lightly-doped region, a second lightly-doped region, a second heavily-doped region, a first electrode and a second electrode. The first lightly-doped region having a first doping type is disposed in a first surface of the substrate. The second lightly-doped region and the second heavily-doped region having a second doping type different from the first doping type are disposed in a second surface of the substrate. The first electrode is disposed on the first surface of the substrate, and the second electrode is disposed on the second surface of the substrate. | 03-06-2014 |