Patent application number | Description | Published |
20090098901 | Memory emulation in a cellular telephone - A cellular telephone using a memory array that is directly addressed and non-volatile is disclosed. The memory array can be used to replace and emulate multiple memory types such as DRAM, SRAM, non-volatile RAM, FLASH memory, and a non-volatile memory card, for example. The memory array may be randomly accessed. Data stored in the memory array is retained in the absence of electrical power. One or more memory arrays may be used in the cellular telephone. At least one of the memory arrays may be in the form of a removable memory card. | 04-16-2009 |
20090106013 | Memory emulation using resistivity-sensitive memory - Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another. | 04-23-2009 |
20090106014 | Transient storage device emulation using resistivity-sensitive memory - Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another. | 04-23-2009 |
20090141545 | Planar third dimensional memory with multi-port access - Embodiments of the invention relate generally to a planar third dimensional memory with multi-port access, the planar third dimensional memory including memory planes composed of a plurality of memory layers. The memory layers can include non-volatile memory elements. The planar third dimensional memory can also include insulation layers, each being formed to separate a memory layer from another memory layer, and a logic plane configured to control access to the plurality of memory planes. In some cases, the memory planes can be formed vertically above the logic plane. The logic plane can be formed in a substrate, such as a semiconductor wafer, for example. The planar third dimensional memory can include a multi-port interface that can be configured to provide access between a plurality of ports and the plurality of memory planes. | 06-04-2009 |
20090147598 | Integrated circuits and methods to compensate for defective memory in multiple layers of memory - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods to compensate for defective memory in third dimension memory technology. In a specific embodiment, an integrated circuit is configured to compensate for defective memory cells. For example, the integrated circuit can include a memory having memory cells that are disposed in multiple layers of memory. It can also include a memory reclamation circuit configured to substitute a subset of the memory cells for one or more defective memory cells. At least one memory cell in the subset of the memory cells resides in a different plane in the memory than at least one of the one or more defective memory cells. | 06-11-2009 |
20090154232 | Disturb control circuits and methods to control memory disturbs among multiple layers of memory - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for controlling memory disturbs to and among multiple layers of memory that include, for example, third dimensional memory technology. Each layer of memory can include a plurality of non-volatile memory cells that store data as a plurality of conductivity profiles that can be non-destructively read by applying a read voltage across a selected non-volatile memory cell. Data can be written to a selected non-volatile memory cell by applying a write voltage having a predetermined magnitude and polarity across the selected non-volatile memory cell. Stored data is retained in the plurality of non-volatile memory cells in the absence of power. | 06-18-2009 |
20090158918 | Media player with non-volatile memory - A media player is provided that includes a processor configured to execute a media player program, a non-volatile memory electrically coupled with the processor, the non-volatile memory being vertically configured, an input/output module electrically coupled with the processor and the non-volatile memory and configured to communicate with an input/output device, and an analog/digital module electrically coupled with the processor and the non-volatile memory, the analog/digital module configured to output a media signal. The input/output module may be in electrical communication with the input/output device (e.g., electrically coupled) and/or signal communication with the input/output device (e.g., wireless and/or optical communication). | 06-25-2009 |
20090164203 | Non-volatile memory compiler - A non-volatile memory compiler for non-volatile memory is disclosed. The non-volatile memory complier may include an input module and a builder module. The input module may accept memory parameters and the builder module may use the inputted memory parameters and its knowledge of the memory to design memory builds. The memory builds may include two-terminal non-volatile memory cells, multiple non-volatile memory layers, a logic plane positioned under one or more non-volatile memory layers, one or more non-volatile memory layers that are partitioned into sub-planes, one or more non-volatile memory layers that emulate one or more memory types such as SRAM, DRAM, ROM, or FLASH, and vertically stacked memory layers. FLASH memory may be emulated without the need to perform an erase operation as part of a write operation. The memory builds can include vias operative to electrically connect one or more non-volatile memory layers with circuitry in a logic plane. | 06-25-2009 |
20090164204 | Solid state drive with non-volatile memory for a media device - A media device is provided that includes a processor configured to execute a media device program, a non-volatile memory electrically coupled with the processor, the non-volatile memory being vertically configured, an input/output module electrically coupled with the processor and the non-volatile memory and configured to communicate with an input/output device, and an analog/digital module electrically coupled with the processor and the non-volatile memory, the analog/digital module configured to output a media signal. The non-volatile memory configured to emulate a hard disk drive. The input/output module may be in electrical communication with the input/output device (e.g., electrically coupled) and/or signal communication with the input/output device (e.g., wireless and/or optical communication). | 06-25-2009 |
20090164706 | Emulation of a NAND memory system - A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example. | 06-25-2009 |
20090164707 | Method and system for accessing non-volatile memory - Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data. | 06-25-2009 |
20090164744 | Memory access protection - A memory system is provided. The memory system includes a memory array and a memory controller in communication with the memory array. The memory controller is configured to receive a first password and to compare the first password with a second password. The second password is stored in the memory controller. If the first password matches the second password, then access is permitted to the memory array. The memory array can include a plurality of vertically stacked memory arrays. The vertically stacked memory arrays can be formed on top of a logic plane that includes active circuitry in communication with the vertically stacked memory arrays. The memory arrays can include two-terminal memory cells that store data as a plurality of conductivity profiles and retain the stored data in the absence of power. The memory arrays may be configured as non-volatile two-terminal cross-point memory arrays. | 06-25-2009 |
20090167352 | Field programmable gate arrays using resistivity sensitive memories - Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane. | 07-02-2009 |
20090167353 | State machines using resistivity-sensitive memories - State machines using resistivity-sensitive memory elements are disclosed. The state machine includes a next state logic comprising a non-volatile memory including a resistivity-sensitive memory element and receiving an input, a state storage device connected to the next state logic including a connection to provide a state of the state machine to the next state logic, and an output connect to the state register to output the state of the state machine. The resistivity-sensitive memory elements may be two-terminal resistivity-sensitive memory elements. The two-terminal resistivity-sensitive memory elements may store data as a plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory elements, and new data can be written by applying a write voltage across the terminals. The two-terminal resistivity-sensitive memory elements retain stored data in the absence of power and may be configured into a two-terminal cross-point memory array. | 07-02-2009 |
20090167496 | Radio frequency identification transponder memory - A radio frequency identification (RFID) transponder includes a vertically configured non-volatile memory array. The RFID transponder additionally includes a logic circuitry connected with the vertically configured non-volatile memory array. The logic circuitry is configured to read data from the vertically configured non-volatile memory array. Additionally included is an antenna, which is connected with the logic circuitry. The antenna is configured to collect power from a radio frequency signal and to transmit the data. The non-volatile memory array may include a plurality of two-terminal memory cells that store data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the terminals of the cell. The logic circuitry can be positioned in a logic plane and at least one non-volatile memory array may be positioned on top of the logic plane and the non-volatile memory arrays may be vertically stacked upon one another. | 07-02-2009 |
20090171650 | Non-Volatile memories in interactive entertainment systems - In accordance with an aspect of the present invention, an interactive entertainment system includes a processor configured to operate interactive entertainment programs, a non-volatile memory connected with the processor including a first portion for random access memory (RAM) emulation, an input/output (I/O) interface connected with the processor and the non-volatile memory to connect a user controller with the processor and the non-volatile memory, and a display interface connected to the processor and the non-volatile memory to output a display signal. The non-volatile memory may include additional portions for emulating read only memory (ROM) and Flash memory. The RAM may be emulated without a refresh operation and Flash memory may be emulated without an erase operation or an operating system. The non-volatile memory may include a plurality of two-terminal memory elements and may be vertically configured. The two-terminal memory elements may be resistivity-sensitive and store data in the absence of power. | 07-02-2009 |
20090172251 | Memory Sanitization - Apparatus and method for memory sanitization is disclosed, including a memory, the memory including—in whole or in part—multiple layers of memory, and control logic configured to perform a sanitize operation on a portion of the memory. In one example, a third dimensional memory array can constitute at least a portion of the multiple layers of memory. The multiple layers of memory may include non-volatile two-terminal cross-point memory arrays. Each non-volatile two-terminal cross-point memory array can include a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the terminals of the two-terminal memory element. The two-terminal memory elements retain stored data in the absence of power. The non-volatile two-terminal cross-point memory arrays can be vertically stacked upon one another and may be positioned on top of a logic plane that includes active circuitry. | 07-02-2009 |
20090172350 | Non-volatile processor register - A processor using a vertically configured non-volatile memory array that can retain values through a power failure is disclosed. The processor may include a register block configured to store and retrieve one or more values, the register block being a vertically configured non-volatile memory array, an arithmetic block configured to perform an arithmetic operation on the one or more values, and a control block configured to control the register block, the arithmetic block, and a memory block. The vertically configured non-volatile memory array may include a plurality of two-terminal memory elements. The two-terminal memory elements may be resistivity-sensitive and store data in the absence of power. The two-terminal memory elements store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written by applying a write voltage across the terminals. | 07-02-2009 |
20090174429 | Programmable logic device structure using third dimensional memory - A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate. | 07-09-2009 |
20090175084 | Buffering systems for accessing multiple layers of memory in integrated circuits - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles. | 07-09-2009 |
20090177833 | Buffering systems methods for accessing multiple layers of memory in integrated circuits - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles. | 07-09-2009 |
20090182965 | Securing data in memory device - The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the invention relate to memory devices, systems, and methods that protect data stored in one or more memory devices from unauthorized access. The memory device may include third dimension memory that is positioned on top of a logic layer that includes active circuitry in communication with the third dimension memory. The third dimension memory may include multiple layers of memory that are vertically stacked upon each other. Each layer of memory may include a plurality of two-terminal memory elements and the two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. At least a portion of one or more of the multiple layers of memory may include an obfuscation layer configured to conceal data stored in one or more of the multiple layers of memory. | 07-16-2009 |
20090196083 | Integrated circuits to control access to multiple layers of memory - Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. | 08-06-2009 |
20090196087 | Non-volatile register - A non-volatile register is disclosed. The non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations. | 08-06-2009 |
20090198485 | Integrated circults to control access to multiple layers of memory in a solid state drive - Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. | 08-06-2009 |
20090198847 | Serial memory interface - A serial memory interface is described, including a memory array, a plurality of serial ports in data communication with the memory array, transferring data between the memory array and at least one of the plurality of serial ports, and a logic block that is configured to control access to the memory array by the plurality of serial ports, the logic block using the serial ports to transfer data between the memory array and at least one of the plurality of serial ports. | 08-06-2009 |
20090204777 | Integated circuits and methods to control access to multiple layers of memory - Circuits and methods to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. | 08-13-2009 |
20090237995 | Scaleable memory Systems Using Third Dimension Memory - A non-volatile scalable memory circuit is described, including a bus formed on a substrate that includes active circuitry, metallization layers, and a plurality of high density third dimension memory arrays formed over the substrate. Each memory circuit can include an embedded controller for controlling data access to the memory arrays and optionally a control node that allows data access to be controlled by an external memory controller or by the embedded controller. The memory circuits can be chained together to increase memory capacity. The memory arrays can be two-terminal cross-point arrays that may be stacked upon one another. | 09-24-2009 |
20100011161 | Memory emulation using resistivity sensitive memory - Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as HDD, DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another. | 01-14-2010 |
20100027314 | Preservation circuit and methods to maintain values representing data in one or more layers of memory - Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer. | 02-04-2010 |
20100134138 | Programmable logic device structure using third dimensional memory - A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate. | 06-03-2010 |
20100134144 | Field programmable gate arrays using resistivity sensitive memories - Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane. | 06-03-2010 |
20100142248 | Buffering systems for accessing multiple layers of memory in integrated circuits - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles. | 06-10-2010 |
20100157644 | Configurable memory interface to provide serial and parallel access to memories - The invention relates to an interface for providing multiple modes of accessing data, including serial and parallel modes. Controllable non-volatile memory interfaces are described, including a serial module configured to provide a serial connection between a non-volatile memory array and another non-volatile memory array. The serial module can provide access to the non-volatile memory array. A mode module can be configured to determine which type of interface operation (i.e., serial mode or parallel mode) will be used for the non-volatile memory array and the another non-volatile memory array. In some cases, a controller can be configured to select the serial module independent of the mode module. Circuitry for performing data operations on the non-volatile memories can be fabricated FEOL on a substrate and the non-volatile memories can be fabricated BEOL directly on top of the substrate in one or more layers of memory. | 06-24-2010 |
20100157659 | Digital potentiometer using third dimensional memory - A digital potentiometer using third dimensional memory includes a switch configured to electrically couple one or more resistive elements with a first pin and a second pin, and a non-volatile register configured to control the switch. In one example, the non-volatile register can include a BEOL non-volatile memory element, such as a third dimensional memory element. The non-volatile register can include a FEOL active circuitry portion that is electrically coupled with the BEOL non-volatile memory element to implement the non-volatile register. The resistive elements can be BEOL resistive elements that can be fabricated on the same plane or a different plane than the BEOL non-volatile memory elements. The BEOL non-volatile memory elements and the BEOL resistive elements can retain stored data in the absence of power and the stored data can be non-destructively determined by application of a read voltage. | 06-24-2010 |
20100161308 | Multi-structured memory - Multi-structured memory is described, including a first memory configured to emulate a first memory type, a second memory configured to emulate a second memory type, the first and second memories disposed in one or more third dimensional memory arrays, and an interface configured to access the first memory or the second memory for data operations. The one or more third dimensional memory arrays are formed on the same component and can be fabricated BEOL on top of a substrate (e.g., a silicon wafer or other semiconductor substrates) including active circuitry (e.g., CMOS devices) fabricated FEOL and operative to perform data operations on the memory arrays and to communicate with external systems configured to access the memory arrays. The third dimensional memory(s) can include two-terminal non-volatile re-writeable cross-point memory arrays including two-terminal non-volatile re-writeable memory cells having their respective terminals electrically coupled with a pair of conductive array lines. | 06-24-2010 |
20100161918 | Third dimensional memory with compress engine - An integrated circuit and method for modifying data by compressing the data in third dimensional memory technology is disclosed. In a specific embodiment, an integrated circuit is configured to perform compression of data disposed in third dimensional memory. For example, the integrated circuit can include a third dimensional memory array configured to store an input independent of storing a compressed copy of the input, a processor configured to compress the input to form the compressed copy of the input, and a controller configured to control access between the processor and the third dimensional memory array. The third dimension memory array can include one or more layers of non-volatile re-writeable two-terminal cross-point memory arrays fabricated back-end-of-the-line (BEOL) over a logic layer fabricated front-end-of-the-line (FEOL). The logic layer includes active circuitry for data operations (e.g., read and write operations) and data compression operations on the third dimension memory array. | 06-24-2010 |
20100162065 | Protecting integrity of data in multi-layered memory with data redundancy - Systems, integrated circuits, and methods for protecting data stored in third dimensional vertically stacked memory technology are disclosed. An integrated circuit is configured to perform duplication of data disposed in multi-layered memory that can comprise two-terminal cross-point memory arrays fabricated BEOL on top of a FEOL logic layer that includes active circuitry for performing data operations (e.g., read, write, program, and erase) on the multi-layered memory. For example, the integrated circuit can include a first subset of BEOL memory layers configured to store data, a second subset of the BEOL memory layers configured to store a copy of the data from the first subset of memory layers, a FEOL redundancy circuit coupled to the first subset of the memory layers and the second subset of the memory layers, the redundancy circuit being configured to provide both a portion of the data and a copy of the portion of the data. | 06-24-2010 |
20100162067 | Memory scrubbing in third dimension memory - A method for memory scrubbing is provided. In this method, a first resistance of a reference memory element is read. A second resistance of a memory element also is read. A difference between the first resistance and the second resistance is sensed and a programming error associated with the second resistance is detected based on the difference. Each memory element is non-volatile and re-writeable, and can be positioned in a two-terminal memory cell that is one of a plurality of memory cells positioned in a two-terminal cross-point memory array. Active circuitry for performing the memory scrubbing can be fabricated FEOL in a logic layer and one or more layers of the two-terminal cross-point memory arrays can be fabricated BEOL over the logic layer. Each memory cell can optionally include non-ohmic device (NOD) electrically in series with the memory element and the two terminals of the memory cell. | 06-24-2010 |
20100195362 | Non-volatile dual port third dimensional memory - Non-volatile dual port memory with third dimension memory is described, including a non-volatile third dimensional memory array comprising a memory element, the memory element is configured to change from a first resistive state to a second resistive state in response to a voltage, a transceiver gate configured to gate the voltage to the memory element, the voltage being configured to change the memory element from the first resistive state to the second resistive state, the transceiver gate is configured to receive another voltage from a bit line and a bit bar line, the bit line and the bit bar line being coupled to the memory element and configured to provide the another voltage, and a plurality of word lines coupled to the memory element, the plurality of word lines are configured to provide substantially simultaneous access to the non-volatile third dimensional memory array using two or more ports. | 08-05-2010 |
20100195363 | Multiple layers of memory implemented as different memory technology - Circuits and methods that use third dimension memory as a different memory technology are described. The third dimension memory can be used for application specific data storage and/or to emulate conventional memory types such as DRAM, FLASH, SRAM, and ROM or new memory types as they become available. A processor-memory system implements a memory operable as different memory technologies. The processor-memory system includes a logic subsystem and a memory subsystem, which includes third dimension memory cells. The logic subsystem implements memory technology-specific signals to interact with the third dimension memory cells as memory cells of a different memory technology. As such, the memory subsystem can emulate different memory technologies. The logic subsystem can be fabricated FEOL on a substrate and the memory subsystem can be fabricated BEOL directly on top of the substrate. An interlayer interconnect structure can electrically couple the logic subsystem with the memory subsystem. | 08-05-2010 |
20100220527 | Non-volatile FIFO with third dimension memory - A FIFO with data storage implemented with non-volatile third dimension memory cells is disclosed. The non-volatile third dimension memory cells can be fabricated BEOL on top of a substrate that includes FEOL fabricated active circuitry configured for data operations on the BEOL memory cells. Other components of the FIFO that require non-volatile data storage can also be implemented as registers or the like using the BEOL non-volatile third dimension memory cells so that power to the FIFO can be cycled and data is retained. The BEOL non-volatile third dimension memory cells can be configured in a single layer of memory or in multiple layers of memory. An IC that includes the FIFO can also include one or more other memory types that are emulated using the BEOL non-volatile third dimension memory cells and associated FEOL circuitry configured for data operations on those memory cells. | 09-02-2010 |
20100220543 | Circuitry and method for indicating a memory - Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of vertically stacked memory planes. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power. | 09-02-2010 |
20100232240 | Columnar replacement of defective memory cells - Circuits and methods to compensate for defective memory in BEOL third dimensional memory technology are described. An integrated circuit is configured to perform columnar replacement of defective BEOL multi-layered memory. For example, the integrated circuit can include a primary BEOL memory array having a plurality of BEOL memory cells being configured to change resistivity, a secondary BEOL memory array having another plurality of BEOL memory cells being configured to change resistivity, and a FEOL restoration module associated with the primary BEOL memory array and the secondary BEOL memory array, the FEOL restoration module being configured to locate a BEOL memory cell within the secondary BEOL memory array to replace a defective BEOL memory cell within the primary BEOL memory array. The FEOL portion can be fabricated on a substrate and the BEOL portion can be fabricated above and in contact with the FEOL portion to form the integrated circuit. | 09-16-2010 |
20100238713 | Non-volatile register - A non-volatile register is disclosed. The non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations. | 09-23-2010 |
20100259969 | Preservation circuit and methods to maintain values representing data in one or more layers of memory - Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer. | 10-14-2010 |
20100274968 | Performing data operations using non-volatile third dimension memory - Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the disk drive, the access request being routed to the non-volatile third dimension memory array to perform a data operation, wherein data from the data operation is used to create a map of the disk drive. In some examples, an address in the non-volatile third dimension memory array provides an alias for another address in a disk drive. | 10-28-2010 |
20100277962 | Media player with non-volatile memory - A media player is provided that includes a processor configured to execute a media player program, a non-volatile memory electrically coupled with the processor, the non-volatile memory being vertically configured, an input/output module electrically coupled with the processor and the non-volatile memory and configured to communicate with an input/output device, and an analog/digital module electrically coupled with the processor and the non-volatile memory, the analog/digital module configured to output a media signal. The input/output module may be in electrical communication with the input/output device (e.g., electrically coupled) and/or signal communication with the input/output device (e.g., wireless and/or optical communication). | 11-04-2010 |
20100293355 | Fast data access through page manipulation - A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data and to generate aligned data, and a page buffer module configured to store the aligned data and, when the page buffer module is full with aligned data, transferring the aligned data to the memory. The method includes receiving data at an interface, aligning the data to generate aligned data, storing aligned data in a page buffer module configured to store aligned data for a write access and retrieved data from a read access, writing aligned data to a memory, and transferring retrieved data to the interface. Data can be transferred by the interface at a first rate and aligned data can be written to or retrieved from the memory at substantially the first rate. | 11-18-2010 |
20110007589 | Integrated circuits and methods to compensate for defective non-volatile embedded memory in one or more layers of vertically stacked non-volatile embedded memory - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods to compensate for defective memory in third dimension memory technology. In a specific embodiment, an integrated circuit is configured to compensate for defective memory cells. For example, the integrated circuit can include a memory having memory cells that are disposed in multiple layers of memory. It can also include a memory reclamation circuit configured to substitute a subset of the memory cells for one or more defective memory cells. At least one memory cell in the subset of the memory cells resides in a different plane in the memory than at least one of the one or more defective memory cells. | 01-13-2011 |
20110026291 | System using non-volatile resistivity-sensitive memory for emulation of embedded flash memory - Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another. | 02-03-2011 |
20110035542 | ASIC including vertically stacked embedded non-flash re-writable non-volatile memory - A multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of memory planes that are vertically stacked upon one another. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power. | 02-10-2011 |
20110040945 | SECURING NON-VOLATILE DATA IN AN EMBEDDED MEMORY DEVICE - The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the invention relate to memory devices, systems, and methods that protect data stored in one or more memory devices from unauthorized access. The memory device may include third dimension memory that is positioned on top of a logic layer that includes active circuitry in communication with the third dimension memory. The third dimension memory may include multiple layers of memory that are vertically stacked upon each other. Each layer of memory may include a plurality of two-terminal memory elements and the two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. At least a portion of one or more of the multiple layers of memory may include an obfuscation layer configured to conceal data stored in one or more of the multiple layers of memory. | 02-17-2011 |
20110047324 | Memory device with vertically embedded non-Flash non-volatile memory for emulation of nand flash memory - A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example. | 02-24-2011 |
20110062989 | State machines using non-volatile re-writeable two-terminal resistivity-sensitive memories - State machines using resistivity-sensitive memory elements are disclosed. The state machine includes a next state logic comprising a non-volatile memory including a resistivity-sensitive memory element and receiving an input, a state storage device connected to the next state logic including a connection to provide a state of the state machine to the next state logic, and an output connect to the state register to output the state of the state machine. The resistivity-sensitive memory elements may be two-terminal resistivity-sensitive memory elements. The two-terminal resistivity-sensitive memory elements may store data as a plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory elements, and new data can be written by applying a write voltage across the terminals. The two-terminal resistivity-sensitive memory elements retain stored data in the absence of power and may be configured into a two-terminal cross-point memory array. | 03-17-2011 |
20110107001 | Performing data operations using non-volatile third dimension memory - Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the disk drive, the access request being routed to the non-volatile third dimension memory array to perform a data operation, wherein data from the data operation is used to create a map of the disk drive. In some examples, an address in the non-volatile third dimension memory array provides an alias for another address in a disk drive. | 05-05-2011 |
20110125957 | System for accessing non-volatile memory - Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data. | 05-26-2011 |
20110134715 | Method for accessing vertically stacked embedded non-flash re-writable non-volatile memory - A multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of memory planes that are vertically stacked upon one another. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power. | 06-09-2011 |
20110141831 | READ BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGRATED CIRCUITS - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles. | 06-16-2011 |
20110163780 | Field programmable gate arrays using resistivity-sensitive memories - Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane. | 07-07-2011 |
20110164450 | Integrated circuits and methods to compensate for defective non-volatile embedded memory in one or more layers of vertically stacked non-volatile embedded memory - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods to compensate for defective memory in third dimension memory technology. In a specific embodiment, an integrated circuit is configured to compensate for defective memory cells. For example, the integrated circuit can include a memory having memory cells that are disposed in multiple layers of memory. It can also include a memory reclamation circuit configured to substitute a subset of the memory cells for one or more defective memory cells. At least one memory cell in the subset of the memory cells resides in a different plane in the memory than at least one of the one or more defective memory cells. | 07-07-2011 |
20110173408 | Securing non-volatile data in an embedded memory device - The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the invention relate to memory devices, systems, and methods that protect data stored in one or more memory devices from unauthorized access. The memory device may include third dimension memory that is positioned on top of a logic layer that includes active circuitry in communication with the third dimension memory. The third dimension memory may include multiple layers of memory that are vertically stacked upon each other. Each layer of memory may include a plurality of two-terminal memory elements and the two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. At least a portion of one or more of the multiple layers of memory may include an obfuscation layer configured to conceal data stored in one or more of the multiple layers of memory. | 07-14-2011 |
20110185116 | Memory device with vertically embedded non-flash non-volatile memory for emulation of NAND flash memory - A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example. | 07-28-2011 |
20110188291 | Preservation circuit and methods to maintain values representing data in one or more layers of memory - Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer. | 08-04-2011 |
20110242871 | Vertically stacked third-dimensional embedded re-writeable non-volatile memory and registers - A non-volatile register is disclosed. The non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations. | 10-06-2011 |
20110242876 | Buffering systems for accessing multiple layers of memory in integrated circuits - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles. | 10-06-2011 |
20110246700 | Integrated circuits to control access to multiple layers of memory in a solid state drive - Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. | 10-06-2011 |
20110280060 | WRITE BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGRATED CIRCUITS - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles. | 11-17-2011 |
20110304355 | Programmable Logic Device Structure Using Third Dimensional Memory - A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate. | 12-15-2011 |
20110310658 | Combined Memories In Integrated Circuits - Combined memories in integrated circuits are described, including determining a first requirement for logic blocks, determining a second requirement for memory blocks including a vertical configuration for the memory blocks, and compiling a design for the integrated circuit using the first requirement and the second requirement. The memory blocks may include non-volatile two-terminal cross-point memory arrays. The non-volatile two-terminal cross-point memory arrays can be formed on top of a logic plane. The logic plane can be fabricated in a substrate. The non-volatile two-terminal cross-point memory arrays may be vertically stacked upon one another to form a plurality of memory planes. The memory planes can be portioned into sub-planes. One or more different memory types such as Flash, SRAM, DRAM, and ROM can be emulated by the plurality of memory planes and/or sub-planes. The non-volatile two-terminal cross-point memory arrays can include a plurality of two-terminal memory elements. | 12-22-2011 |
20120023288 | System For Accessing Non Volatile Memory - Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data. | 01-26-2012 |
20120057394 | Securing Non Volatile Data In An Embedded Memory Device - The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the invention relate to memory devices, systems, and methods that protect data stored in one or more memory devices from unauthorized access. The memory device may include third dimension memory that is positioned on top of a logic layer that includes active circuitry in communication with the third dimension memory. The third dimension memory may include multiple layers of memory that are vertically stacked upon each other. Each layer of memory may include a plurality of two-terminal memory elements and the two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. At least a portion of one or more of the multiple layers of memory may include an obfuscation layer configured to conceal data stored in one or more of the multiple layers of memory. | 03-08-2012 |
20120063191 | Performing Data Operations Using Non Volatile Third Dimension Memory - Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the disk drive, the access request being routed to the non-volatile third dimension memory array to perform a data operation, wherein data from the data operation is used to create a map of the disk drive. In some examples, an address in the non-volatile third dimension memory array provides an alias for another address in a disk drive. | 03-15-2012 |
20120063200 | Dual Ported Non Volatile FIFO With Third Dimension Memory - A FIFO with data storage implemented with non-volatile third dimension memory cells is disclosed. The non-volatile third dimension memory cells can be fabricated BEOL on top of a substrate that includes FEOL fabricated active circuitry configured for data operations on the BEOL memory cells. Other components of the FIFO that require non-volatile data storage can also be implemented as registers or the like using the BEOL non-volatile third dimension memory cells so that power to the FIFO can be cycled and data is retained. The BEOL non-volatile third dimension memory cells can be configured in a single layer of memory or in multiple layers of memory. An IC that includes the FIFO can also include one or more other memory types that are emulated using the BEOL non-volatile third dimension memory cells and associated FEOL circuitry configured for data operations on those memory cells. | 03-15-2012 |
20120063239 | Circuitry And Method For Indicating A Memory - Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of vertically stacked memory planes. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power. | 03-15-2012 |
20120069620 | System Including Vertically Stacked Embedded Non Flash Re Writable Non Volatile Memory - A multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of memory planes that are vertically stacked upon one another. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power. | 03-22-2012 |
20120069621 | Integrated Circuits Using Non Volatile Resistivity Sensitive Memory For Emulation Of Embedded Flash Memory - Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another. | 03-22-2012 |
20120069665 | Memory Device With Vertically Embedded Non Flash Non Volatile Memory For Emulation Of Nand Flash Memory - A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example. | 03-22-2012 |
20120147660 | Preservation Circuit And Methods To Maintain Values Representing Data In One Or More Layers Of Memory - Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer. | 06-14-2012 |
20120147678 | Buffering Systems For Accessing Multiple Layers Of Memory In Integrated Circuits - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles. | 06-14-2012 |
20120176840 | Combined Memories In Integrated Circuits - Combined memories in integrated circuits are described, including determining a first requirement for logic blocks, determining a second requirement for memory blocks including a vertical configuration for the memory bocks, and compiling a design for the integrated circuit using the first requirement and the second requirement. The memory blocks may include non-volatile two-terminal cross-point memory arrays. The non-volatile two-terminal cross-point memory arrays can be formed on top of a logic plane. The logic plane can be fabricated in a substrate. The non-volatile two-terminal cross-point memory arrays may be vertically stacked upon one another to form a plurality of memory planes. The memory planes can be portioned into sub-planes. One or more different memory types such as Flash, SRAM, DRAM, and ROM can be emulated by the plurality of memory planes and/or sub-planes. The non-volatile two-terminal cross-point memory arrays can include a plurality of two-terminal memory elements. | 07-12-2012 |
20120179862 | System For Accessing Non-Volatile Memory - Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data. | 07-12-2012 |
20120206980 | BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGRATED CIRCUITS - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles. | 08-16-2012 |
20120208595 | Memory Emulation In A Cellular Telephone - A cellular telephone using a memory array that is directly addressed and non-volatile is disclosed. The memory array can be used to replace and emulate multiple memory types such as DRAM, SRAM, non-volatile RAM, FLASH memory, and a non-volatile memory card, for example. The memory array may be randomly accessed. Data stored in the memory array is retained in the absence of electrical power. One or more memory arrays may be used in the cellular telephone. At least one of the memory arrays may be in the form of a removable memory card. | 08-16-2012 |
20120210052 | INTEGRATED CIRCUIT WITH COMPRESS ENGINE - An integrated circuit and method for modifying data by compressing the data in third dimensional memory technology is disclosed. In a specific embodiment, an integrated circuit is configured to perform compression of data disposed in third dimensional memory. For example, the integrated circuit can include a third dimensional memory array configured to store an input independent of storing a compressed copy of the input, a processor configured to compress the input to form the compressed copy of the input, and a controller configured to control access between the processor and the third dimensional memory array. The third dimension memory array can include one or more layers of non-volatile re-writeable two-terminal cross-point memory arrays fabricated back-end-of-the-line (BEOL) over a logic layer fabricated front-end-of-the-line (FEOL). The logic layer includes active circuitry for data operations (e.g., read and write operations) and data compression operations on the third dimension memory array. | 08-16-2012 |
20120210053 | Securing Non Volatile Data In RRAM - The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the invention relate to memory devices, systems, and methods that protect data stored in one or more memory devices from unauthorized access. The memory device may include third dimension memory that is positioned on top of a logic layer that includes active circuitry in communication with the third dimension memory. The third dimension memory may include multiple layers of memory that are vertically stacked upon each other. Each layer of memory may include a plurality of two-terminal memory elements and the two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. At least a portion of one or more of the multiple layers of memory may include an obfuscation layer configured to conceal data stored in one or more of the multiple layers of memory. | 08-16-2012 |
20120212646 | Memory Emulation In An Image Capture Device - An image capture device using a memory array that is directly addressed and non-volatile is disclosed. The memory array can be used to replace and emulate multiple memory types such as DRAM, SRAM, non-volatile RAM, a non-volatile memory card, and FLASH memory, for example. The memory array may be randomly accessed. Data stored in the memory array is retained in the absence of electrical power. One or more memory arrays may be used in the image capture device. At least one of the memory arrays may be in the form of a removable memory card. | 08-23-2012 |
20120217466 | Digital Potentiometer Using Third Dimensional Memory - A digital potentiometer using third dimensional memory includes a switch configured to electrically couple one or more resistive elements with a first pin and a second pin, and a non-volatile register configured to control the switch. In one example, the non-volatile register can include a BEOL non-volatile memory element, such as a third dimensional memory element. The non-volatile register can include a FEOL active circuitry portion that is electrically coupled with the BEOL non-volatile memory element to implement the non-volatile register. The resistive elements can be BEOL resistive elements that can be fabricated on the same plane or a different plane than the BEOL non-volatile memory elements. The BEOL non-volatile memory elements and the BEOL resistive elements can retain stored data in the absence of power and the stored data can be non-destructively determined by application of a read voltage. | 08-30-2012 |
20120257460 | METHOD FOR INDICATING A NON-FLASH NONVOLATILE MULTIPLE-TYPE THREE-DIMENSIONAL MEMORY - Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of vertically stacked memory planes. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power. | 10-11-2012 |
20120265929 | INTEGRATED CIRCUITS TO CONTROL ACCESS TO MULTIPLE LAYERS OF MEMORY IN A SOLID STATE DRIVE - Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. | 10-18-2012 |
20140139264 | PROGRAMMABLE LOGIC DEVICE STRUCTURE USING THIRD DIMENSIONAL MEMORY - A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate. | 05-22-2014 |
20140140123 | PRESERVATION CIRCUIT AND METHODS TO MAINTAIN VALUES REPRESENTING DATA IN ONE OR MORE LAYERS OF MEMORY - Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer. | 05-22-2014 |
20140198584 | BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGRATED CIRCUITS - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles. | 07-17-2014 |