Patent application number | Description | Published |
20140017894 | Methods of Manufacturing Semiconductor Devices - Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a material layer is formed over a workpiece. The workpiece includes a first portion, a second portion, and a hard mask disposed between the first portion and the second portion. The material layer is patterned, and first spacers are formed on sidewalls of the patterned material layer. The patterned material layer is removed, and the second portion of the workpiece is patterned using the first spacers as an etch mask. The first spacers are removed, and second spacers are formed on sidewalls of the patterned second portion of the workpiece. The patterned second portion of the workpiece is removed, and the hard mask of the workpiece is patterned using the second spacers as an etch mask. The first portion of the workpiece is patterned using the hard mask as an etch mask. | 01-16-2014 |
20140027908 | Integrated Circuit Interconnects and Methods of Making Same - A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween. | 01-30-2014 |
20140138801 | SEMICONDUCTOR PATTERNING - One or more techniques or systems for forming a pattern during semiconductor fabrication are provided herein. In some embodiments, a photo resist (PR) region is patterned and a spacer region is formed above or surrounding at least a portion of the patterned PR region. Additionally, at least some of the spacer region and the patterned PR region are removed to form one or more spacers. Additionally, a block co-polymer (BCP) is filled between the spacers. In some embodiments, the BCP comprises a first polymer and a second polymer. In some embodiments, the second polymer is removed, thus forming a pattern comprising the first polymer and the spacers. In this manner, a method for forming a pattern during semiconductor fabrication is provided, such that a width of the spacer or the first polymer is controlled. | 05-22-2014 |
20140151888 | Air-Gap Formation in Interconnect Structures - A structure includes a substrate, and a first metal line and a second metal line over the substrate, with a space therebetween. A first air gap is on a sidewall of the first metal line and in the space, wherein an edge of the first metal line is exposed to the first air gap. A second air gap is on a sidewall of the second metal line and in the space, wherein an edge of the second metal line is exposed to the second air gap. A dielectric material is disposed in the space and between the first and the second air gaps. | 06-05-2014 |
20140239501 | INTEGRATED CIRCUIT INTERCONNECTS AND METHODS OF MAKING SAME - A dielectric layer is formed on a substrate and patterned to form an opening. The opening is filled and the dielectric layer is covered with a metal layer. The metal layer is thereafter planarized so that the metal layer is co-planar with the top of the dielectric layer. The metal layer is etched back a predetermined thickness from the top of the dielectric layer to expose the inside sidewalls thereof. A sidewall barrier layer is formed on the sidewalls of the dielectric layer. A copper-containing layer is formed over the metal layer, the dielectric layer, and the sidewall barrier layers. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the sidewall barrier layers at approximately the juncture of the sidewall of the dielectric layer and the copper-containing layer and does not etch into the underlying metal layer. | 08-28-2014 |
20140273442 | Spacer Etching Process For Integrated Circuit Design - A method of forming a target pattern includes forming a first material layer on a substrate; performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer; performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer; forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness; removing the first material layer; etching the substrate using the spacer features as an etch mask; and thereafter removing the spacer features. The target pattern is to be formed with the first layout and the second layout. | 09-18-2014 |
20150056812 | Method of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A first dielectric layer is deposited on the substrate. A patterned photoresist layer is formed on the first dielectric layer. The patterned photoresist layer is trimmed. The first dielectric layer is etched through the trimmed patterned photoresist layer to form a dielectric feature. A sacrificing energy decomposable layer (SEDL) is deposited on the dielectric feature and etched to form a SEDL spacer on sides of the dielectric feature. A second dielectric layer is deposited on the SEDL spacer and etched to form a dielectric spacer. The SEDL spacer is decomposed to form a trench. | 02-26-2015 |
20150155184 | SEMICONDUCTOR PATTERNING - One or more techniques or systems for forming a pattern during semiconductor fabrication are provided herein. In some embodiments, a photo resist (PR) region is patterned and a spacer region is formed above or surrounding at least a portion of the patterned PR region. Additionally, at least some of the spacer region and the patterned PR region are removed to form one or more spacers. Additionally, a block co-polymer (BCP) is filled between the spacers. In some embodiments, the BCP comprises a first polymer and a second polymer. In some embodiments, the second polymer is removed, thus forming a pattern comprising the first polymer and the spacers. In this manner, a method for forming a pattern during semiconductor fabrication is provided, such that a width of the spacer or the first polymer is controlled. | 06-04-2015 |
20150179435 | Method For Integrated Circuit Patterning - A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches. | 06-25-2015 |
20150214143 | Semiconductor Integrated Circuit With Nano Gap - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A substrate having a dielectric layer over it is provided. A block co-polymer (BCP) layer is deposited over the dielectric layer. The BCP layer is then annealed to form a first polymer nanostructures surrounded by a second polymer nanostructures over the dielectric layer. The second polymer nanostructure is selectively etched using the first polymer nanostructure as an etch mask to form a nano-block. The dielectric layer is selectively etched using the nano-block as an etch mask to form a nano-trench. The nano-trenched is sealed to form a nano-air-gap. | 07-30-2015 |
Patent application number | Description | Published |
20080266007 | OSCILLATING APPARATUS HAVING CURRENT COMPENSATING DEVICE FOR PROVIDING COMPENSATING CURRENT TO COMPENSATE FOR CURRENT REDUCTION OF TRANSCONDUCTIVE DEVICE AND METHOD THEREOF - According to an embodiment of the present invention, an oscillating apparatus is provided. The oscillating apparatus generates an oscillating signal, and the oscillating apparatus includes a resonating device, a transconductive device, a biasing device, and a current compensating device. The resonating device generates the oscillating signal; the transconductive device is coupled to the resonating device for providing the resonating device with a positive feedback loop; the biasing device is coupled to the transconductive device for providing the transconductive device with a biasing current; and the current compensating device is coupled between the resonating device and the biasing device for providing the biasing device with a compensating current to compensate for a current reduction of the transconductive device. | 10-30-2008 |
20090278624 | REFLECTION-TYPE PHASE SHIFTER HAVING REFLECTION LOADS IMPLEMENTED USING TRANSMISSION LINES AND PHASED-ARRAY RECEIVER/TRANSMITTER UTILIZING THE SAME - A reflection-type phase shifter is provided. The reflection-type phase shifter has a coupler, a first reflection load, and a second reflection load. The coupler has an input port for receiving an input signal and an isolated port for outputting an output signal due to a first reflected signal at a through port and a second reflected signal at a coupled port. The first reflection load reflects the first fraction of the input signal to thereby generate the first reflected signal. The second reflection load reflects the second fraction of the input signal to thereby generate the second reflected signal. In addition, at least one of the first and second reflection loads is equivalent to a transmission line. | 11-12-2009 |
20100033148 | Voltage Reference Circuit with Fast Enable and Disable Capabilities - A circuit for providing an output voltage substantially equal to a reference voltage includes: a low drop-out (LDO) regulator coupled to the reference voltage for producing the output voltage at an output terminal; a reference current source having a first end and a second end for providing a predetermined reference current; a first transistor having a first terminal coupled to a first supply voltage, a second terminal, and a control terminal coupled to the second terminal of the first transistor; a first switch for selectively coupling the second terminal of the first transistor to the first end of the reference current source according to a first control signal; and a second transistor having a first terminal coupled to the first supply voltage, a control terminal coupled to the control terminal of the first transistor, and a second terminal coupled to the output terminal. | 02-11-2010 |
20100244969 | TEMPERATURE COMPENSATED OSCILLATION CIRCUITS - A temperature compensated oscillation circuit capable of providing a stable frequency output over temperature is provided, in which an oscillator with a crystal resonator is arranged to generate an oscillation signal with an output frequency, and a temperature sensor provides a temperature compensation voltage of which a function is linear with respect to an ambient temperature of the oscillator. A first accumulation mode MOS varactor is coupled to the oscillator, and the first accumulation mode MOS varactor adjusts a capacitance thereof in response to the temperature compensation voltage, such that the coupled oscillator has a frequency compensation over temperature for the oscillation signal, wherein the frequency compensation substantially varies as an inverse function of a deviation of the crystal resonator over temperature when the ambient temperature is within a predetermined temperature range. | 09-30-2010 |
20110230151 | FREQUENCY-SELECTIVE CIRCUIT WITH MIXER MODULE IMPLEMENTED FOR CONTROLLING FREQUENCY RESPONSE, AND RELATED SIGNAL PROCESSING APPARATUS AND METHOD - A frequency-selective circuit includes a signal input port, a signal output port, and a frequency response control block. The frequency response control block includes a mixer module and a filter module. The mixer module has a first port electrically connected to a signal path between the signal input port and the signal output port, a second port electrically connected to the filter module, and a local oscillator (LO) port. The mixer module operates according to an LO input received by the LO port. The filter module is electrically connected to the second port of the mixer module. | 09-22-2011 |
20110230152 | SIGNAL PROCESSING APPARATUS HAVING FREQUENCY-SELECTIVE CIRCUIT WITH MIXER MODULE IMPLEMENTED FOR CONTROLLING FREQUENCY RESPONSE AND RELATED METHOD THEREOF - A method of setting filtering characteristic of a signal processing apparatus includes following steps: configuring a first signal processing path, included in the signal processing apparatus and electrically connected to a signal input port of the signal processing apparatus, to have a first filtering characteristic; and configuring a second signal processing path, included in the signal processing apparatus and electrically connected between the signal input port and the first signal processing path, to have a second filtering characteristic different from the first filtering characteristic. When an input signal received at the signal input port includes a first signal component with a first frequency and a second signal component with a second frequency, most of the first signal component is processed by the first signal processing path, and most of the second signal component is processed by the second signal processing path. | 09-22-2011 |
20110234266 | FREQUENCY DIVIDER FOR GENERATING OUTPUT CLOCK SIGNAL WITH DUTY CYCLE DIFFERENT FROM DUTY CYCLE OF INPUT CLOCK SIGNAL - A frequency divider includes a plurality of logic circuit blocks. Each of the logic circuit blocks has a plurality of control terminals. At least one of the control terminals of one of the logic circuit blocks is arranged to receive an input clock signal having a first duty cycle. At least one of the remaining control terminals of the one of the logic circuit blocks is arranged to couple another one of the logic circuit blocks by a positive feedback. A clock signal at the at least one of the remaining control terminals has a second duty cycle different from the first duty cycle. | 09-29-2011 |
20120105172 | PHASE SHIFTER AND RELATED LOAD DEVICE WITH LINEARIZATION TECHNIQUE EMPLOYED THEREIN - A phase shifter and related load device are provided. The phase shifter includes a phase shifter core and load devices. The phase shifter core has an input port for receiving an input signal, an output port for outputting an output signal, and connection ports. The load devices are coupled to the connection ports, respectively. At least one of the load devices includes first varactor units each having a first node and a second node, where first nodes of the first varactor units are coupled to a first voltage, second nodes of the first varactor units are respectively coupled to a plurality of second voltages, and the second voltages include at least two voltages different from each other. The phase shifter and related load device are capable of mitigating effects resulted from varactor's non-linear C-V curve. | 05-03-2012 |
20120154045 | PUSH-PULL LOW NOISE AMPLIFIER WITH VARIABLE GAIN, PUSH-PULL LOW NOISE AMPLIFIER WITH COMMON GATE BIAS CIRCUIT AND AMPLIFIER WITH AUXILIARY MATCHING - A push-pull low noise amplifier (LNA) includes at least one amplifier block. Each amplifier block includes a bypass stage and at least one gain cell. The bypass stage has a first node and a second node. The gain cell has an input terminal and an output terminal, comprising a loading stage and a driving stage. When the push-pull LNA is in a first gain mode, the loading stage is enabled and the bypassing stage is disabled; and when the push-pull LNA is in a second gain mode, the loading stage is disabled and the bypassing stage is enabled. | 06-21-2012 |
20130043913 | FREQUENCY DIVIDER FOR GENERATING OUTPUT CLOCK SIGNAL WITH DUTY CYCLE DIFFERENT FROM DUTY CYCLE OF INPUT CLOCK SIGNAL - A frequency divider includes a plurality of logic circuit blocks. Each of the logic circuit blocks has a plurality of control terminals. At least one of the control terminals of one of the logic circuit blocks is arranged to receive an input clock signal having a first duty cycle. At least one of the remaining control terminals of the one of the logic circuit blocks is arranged to couple another one of the logic circuit blocks by a positive feedback. A clock signal at the at least one of the remaining control terminals has a second duty cycle different from the first duty cycle. Each of the logic circuit blocks includes a plurality of first transistors coupled in parallel between a first reference voltage and an output terminal, and a plurality of second transistors coupled in series between a second reference voltage and the output terminal. | 02-21-2013 |
20130314160 | LOW NOISE AMPLIFIER AND SAW-LESS RECEIVER WITH LOW-NOISE AMPLIFIER - A low noise amplifier is used to amplify a differential input pair to generate a differential output pair. The low noise amplifier includes two main paths, two assistant circuits and two adders to make noise carried on two output signals of the differential output pair be the same; therefore, the noise of the two output signals can be fully cancelled in the following operations. | 11-28-2013 |
20140035096 | METHOD FOR CONTROLLING ELECTRICAL PROPERTY OF PASSIVE DEVICE DURING FABRICATION OF INTEGRATED COMPONENT AND RELATED INTEGRATED COMPONENT - A method for controlling an electrical property of a passive device during a fabrication of an integrated component includes providing a substrate, manufacturing the passive device on the substrate, measuring the electrical property of the passive device to obtain a measuring result, determining at least one layout pattern corresponding to at least one later manufacturing process by the measuring result for adjusting the electrical property of the passive device, and continuing the rest of the fabrication including the at least one later manufacturing process of the integrated component. | 02-06-2014 |
20140233441 | Diplexer and Transceiver thereof - A diplexer, for coupling a first radio frequency (RF) signal corresponding to a first carrier frequency and a second RF signal corresponding to a second carrier frequency is disclosed. The diplexer includes a first port arranged to couple the first RF signal; a second port arranged to couple the second RF signal; a third port capable of connecting an antenna; a first impedance unit coupled to the first port and the third port; and a second impedance unit coupled to the second port and the third port; wherein the first port, the second port and the third port are coupled to a direct current (DC) ground; wherein the first impedance unit is arranged to provide an first open-circuit impedance against the second RF signal, and the second impedance unit is arranged to provide a second open-circuit impedance against the first RF signal. | 08-21-2014 |
20140354371 | RADIO FREQUENCY TRANSMITTER, POWER COMBINERS AND TERMINATIONS THEREFOR - A power combiner includes a primary winding and a secondary winding, wherein at least the primary winding comprises a centre-tap; and a termination module operably coupled to the centre-tapped primary winding and arranged to provide harmonic terminations on a plurality of frequencies. In addition, there is provided a radio frequency transmitter having a power combiner, where the power combiner includes a primary winding and a secondary winding, wherein at least the primary winding includes a centre-tap; and a termination module operably coupled to the centre-tapped primary winding and arranged to provide harmonic terminations on a plurality of frequencies. | 12-04-2014 |
20140355728 | RECEIVER FRONT-END CIRCUIT, COMMUNICATION UNIT AND METHOD THEREFOR - A receiver front end circuit includes a low-noise amplifier including: a first receiver path having: a first low-noise transconductor to amplify a received signal and output the amplified received signal; and a first mixer to down-convert the amplified received signal. A second receiver path includes: an auxiliary receiver having: a second transconductor to output an amplified received signal; a baseband amplifier having an input port and an output port; a first resistance coupling the input port to the output port of the baseband amplifier and to convert the amplified received signal from current to voltage and set a voltage gain of the second receiver path; and a second resistance coupled from the output port of the baseband amplifier to the first mixer output. In some examples, frequency-upconversion feedback path includes a third mixer to frequency up-convert the amplified received signal at an output of the second receiver path. | 12-04-2014 |
20140357206 | RADIO FREQUENCY TRANSMITTER, POWER COMBINERS AND TERMINATIONS THEREFOR - A power combiner includes a planar figure-8 shaped primary winding and a planar figure-8 shaped secondary winding; wherein, the planar figure-8 shaped primary winding is substantially overlaid with the planar figure-8 shaped secondary winding. In addition, there is provided a radio frequency (RF) transmitter having a power combiner, where the power combiner includes a planar figure-8 shaped primary winding and a planar figure-8 shaped secondary winding, wherein the planar figure-8 shaped primary winding is substantially overlaid with the planar figure-8 shaped secondary winding. | 12-04-2014 |
20140357208 | RADIO FREQUENCY TRANSMITTER, POWER COMBINERS AND WIRELESS COMMUNICATION UNIT THEREFOR - A radio frequency transmitter includes: power amplifier stages having paired output terminals, where a pair of output terminals is coupled to a respective amplifier stage. A power combining arrangement includes: first paired input terminals, second input terminals, such that each input of the first paired input terminals is coupled to the same second input terminal; and a power transfer circuit coupling the second input terminals. A first pair of cross coupled bond wires couples a pair of amplifier stage output terminals with a different second input terminal via terminals of different pairs of the first paired input terminals; and a second pair of cross coupled bond wires overlays the first pair of cross coupled bond wires and couples a further pair of amplifier stage output terminals with a different second input terminal via terminals of different pairs of the first paired input terminals. | 12-04-2014 |
Patent application number | Description | Published |
20110012823 | LIQUID CRYSTAL DISPLAY AND SHIFT REGISTER DEVICE THEREOF - A liquid crystal display and a shift register device thereof are provided. The shift register device includes a plurality of shift registers connected in series. In the invention, the channel lengths of the transistors, which are responsible to stop outputting scan signal, in the shift register are manufactured greater than the channel lengths of the transistors, which are responsible to output the scan signal, in the shift register. As a result, the degree of influence that the leakage currents of the N-type transistors being responsible to stop outputting the scan signal in the shift register affect the transistors being responsible to output the scan signal when the transistors being responsible to stop outputting the scan signal are in the sub-threshold region is reduced. And thus each of the shift registers is able to output the scan signal normally. | 01-20-2011 |
20110227077 | REPAIR METHOD AND ACTIVE DEVICE ARRAY SUBSTRATE - A repair method for repairing an active device array substrate is provided. The active device array substrate includes a substrate, scan lines, data lines, active devices, pixel electrodes, and common lines. At least one of the scan line has an open defect. The scan lines and the data lines are intersected to define sub-pixel regions. The active devices are electrically connected with the scan lines and the data lines correspondingly. Each pixel electrode is disposed in one of the sub-pixel regions and electrically connected with one of the active devices. The repair method includes cutting one of the common lines neighboring to the open defect to form a cutting block that is electrically insulated from the common lines; and welding the cutting block, the scan line having the open defect and two active devices located at two opposite sides of the open defect. | 09-22-2011 |
20130134428 | ACTIVE DEVICE ARRAY SUBSTRATE - A repair method for repairing an active device array substrate is provided. The active device array substrate includes a substrate, scan lines, data lines, active devices, pixel electrodes, and common lines. At least one of the scan line has an open defect. The scan lines and the data lines are intersected to define sub-pixel regions. The active devices are electrically connected with the scan lines and the data lines correspondingly. Each pixel electrode is disposed in one of the sub-pixel regions and electrically connected with one of the active devices. The repair method includes cutting one of the common lines neighboring to the open defect to form a cutting block that is electrically insulated from the common lines; and welding the cutting block, the scan line having the open defect and two active devices located at two opposite sides of the open defect. | 05-30-2013 |