Patent application number | Description | Published |
20090054231 | METHOD FOR PREPARING NANOSTRUCTURED VANADIA-TITANIA CATALYSTS USEFUL FOR DEGRADING CHLORINATED ORGANIC COMPOUNDS BY A FLAME SPRAY PROCESS - The present invention discloses methods for preparing vanadia-titania catalysts in the form of nanostructured particles, where vanadia particles are dispersed at the surface of a titanium dioxide carrier and attached thereto, which are useful for degrading chlorinated organic compounds. The method of the present invention has a number of advantages in that: (i) it is capable of producing vanadia-titania catalysts by a relatively simple process as compared to the conventional wet-type method; (ii) the size of the catalyst particles can be easily regulated; and (iii) the vanadia-titania catalysts prepared according to the method of the present invention exhibit excellent degradation efficiency with respect to chlorinated organic compounds even at a low temperature, compared to catalysts prepared by the wet-type method, due to their nanostructure that provides the catalysts with large reactive surface area and high physical stability. | 02-26-2009 |
20090097332 | Semiconductor memory device - A semiconductor memory device includes a memory cell array including a plurality of memory cells having a transistor with a floating body, a source line driver configured to control the source lines to select the memory cells in response to an address signal, a source line voltage generation unit configured to generate a source line target voltage, receive an source line output voltage from the source line driver, compare the level of the source line output voltage with the level of the source line target voltage, generate a source line voltage of which the level is adaptively varied according to a temperature, and a sense amplifier configured to sense a difference in current flowing through the bit lines in response to data read from a selected memory cell, amplify the difference to a level having high output driving capability and output the amplified current. | 04-16-2009 |
20090300515 | Web server for supporting collaborative animation production service and method thereof - A web server for supporting a collaborative animation production service. The web server includes a user interface (UI) unit to provide a UI to receive direction data for each scene required for animation production in parallel to users connected to the web server, and a generating unit to combine the direction data input to the UI for each scene and generate an animation corresponding to the combined direction data. A plurality of users thereby collaborate to produce an animation in real time, making it possible to shorten the production time of the animation and produce a high quality animation. | 12-03-2009 |
20090302897 | Driver circuit having high reliability and performance and semiconductor memory device including the same - Example embodiments relate to a driver circuit and a semiconductor memory device including the driver circuit. The driver circuit includes a pull-up unit configured to connect an output node to a first power supply voltage in response to an input signal, an interface unit connected between the output node and a first node to decrease a voltage of the output node in response to a control signal, and a pull-down unit configured to connect the first node to a second power supply voltage. The interface unit includes a first transistor configured to connect the output node with the first node in response to the control signal and a first resistor connected between the output node and the first node. The interface unit may also include a second resistor and a second transistor connected in series between the output node and the first node. | 12-10-2009 |
20100091913 | APPARATUS AND METHOD FOR ESTIMATING PHASE ERROR BASED ON VARIABLE STEP SIZE - Disclosed is a phase error estimating an apparatus and a method which provides improved convergence speed and tracking speed even in mobile channel environment by variably applying the step size for phase error estimation according to channel status. The apparatus for estimating a phase error includes: a posterior probability (APP) average calculating unit for calculating an APP average value from a soft decision result of a currently received symbol; a step size determining unit for determining a step size variably according to channel status; and a phase error estimating unit for estimating a phase error of the currently received symbol from a phase error of a previously received symbol and the APP average value by using the variably determined step size. | 04-15-2010 |
20100118034 | APPARATUS AND METHOD OF AUTHORING ANIMATION THROUGH STORYBOARD - An animation authoring apparatus and method of authoring an animation including a storyboard editor to provide a storyboard editing screen, to interact with a user to edit a storyboard, and to store the edited storyboard, a parser to parse syntax of the edited storyboard, and a rendering engine to convert the edited storyboard into a graphic animation based on the parsed syntax of the edited storyboard. | 05-13-2010 |
20100118631 | Semiconductor memory devices with mismatch cells - A semiconductor memory device having the mismatch cell makes a capacitance difference between a bit line pair relatively large during a read operation using at least one dummy memory cell as a mismatch cell selected together with a corresponding memory cell. Therefore, data of a semiconductor memory device may be detected more easily. | 05-13-2010 |
20100124135 | Semiconductor memory devices having hierarchical bit-line structures - The semiconductor memory device includes a memory cell array and a switching circuit. The memory cell array includes a plurality of first memory cells connected between word lines and first local bit lines, and a plurality of second memory cells connected between the word lines and second local bit lines. The switching circuit is configured to respectively connect the first local bit lines to first global bit lines during a first sensing period, and to respectively connect the second local bit lines to second global bit lines during a second sensing period of a reading operation. The semiconductor memory device further includes a sensing circuit configured to sense and amplify data from the first global bit lines during the first sensing period, and to sense and amplify data from the second global bit lines during the second sensing period of the reading operation. | 05-20-2010 |
20110013464 | Semiconductor memory device having hierarchical bit line structure and method of driving the semiconductor memory device - The semiconductor memory device includes a first memory cell array including at least one first memory cell and at least one second memory cell corresponding to the at least one first memory cell, a first low bit line connected to the at least one first memory cell, a first low complementary bit line connected to the at least one second memory cell, a first switch unit having a first terminal connected to the first low bit line, a second switch unit having a first terminal connected to the first low complementary bit line, a first global bit line connected to a second terminal of the first switch unit, a first global complementary bit line connected to a second terminal of the second switch unit, and a plurality of sensing amplifying units connected to the first global bit line and the first global complementary bit line. | 01-20-2011 |
20110029891 | MOBILE TERMINAL AND METHOD OF CONTROLLING OPERATION OF THE MOBILE TERMINAL - A mobile terminal and an operating method of the mobile terminal are provided. The mobile terminal may be coupled, either wirelessly or by wire, to an external terminal and the mobile terminal may thus receive sync data including information regarding a webpage currently being displayed by the external terminal from the external terminal or a server. The mobile terminal may display the same webpage as is currently being displayed by the external terminal based on the received sync data. | 02-03-2011 |
20110069569 | SEMICONDUCTOR MEMORY DEVICE COMPRISING TRANSISTOR HAVING VERTICAL CHANNEL STRUCTURE - A semiconductor memory device including a transistor having a vertical channel structure is provided. The device includes a first sub memory cell array including a first memory cell connected to a first bit lines and including a transistor having a vertical channel structure, a second sub memory cell array including a second memory cell connected to a first inverted bit lines and including a transistor having a vertical channel structure, and a plurality of precharge blocks. In addition, first and second precharge blocks are disposed at first and second sides of the first bit line and precharge the first bit line, and third and fourth precharge blocks are disposed at first and second sides of the first inverted bit line and precharge the first inverted bit line. | 03-24-2011 |
20110216602 | FLASH MEMORY DEVICES WITH SELECTIVE BIT LINE DISCHARGE PATHS AND METHODS OF OPERATING THE SAME - Provided is a flash memory device that can include a memory cell configured to store data, a local bit line that is connected to the memory cell, a global bit line that is connected to the local bit line, a discharge transistor that is connected to the global bit line, and that is configured to selectively connect the global bit line to a reference level responsive to a discharge control signal, and a discharge control circuit, that is connected to the discharge transistor via the discharge control signal, and that is configured to selectively disable the discharge transistor during an erase interval occurring before a verify interval of an erase verification operation carried out by the flash memory device. | 09-08-2011 |
20110305069 | NONVOLATILE MEMORY DEVICE USING RESISTANCE MATERIAL AND MEMORY SYSTEM INCLUDING THE NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes: a memory array including a plurality of memory banks which are arranged in a first direction; a write global bit line and a read global bit line extending in the first direction to be shared by the memory banks; a write circuit connected to the write global bit line and disposed on a first side of the memory array; and a read circuit connected to the read global bit line and disposed on a second side of the memory array opposite the first side of the memory array, wherein each of the memory banks extends in a second direction different from the first direction and comprises a plurality of nonvolatile memory cells, each of the nonvolatile memory cells having a variable resistive element whose resistance value varies according to data stored therein. | 12-15-2011 |
20120033489 | MEMORY DEVICE, PRECHARGE CONTROLLING METHOD THEREOF, AND DEVICES HAVING THE SAME - A pre-charge controlling method and device are provided. The pre-charge controlling method includes pre-charging a first global bit line with a first pre-charge voltage by using at least a first pre-charge circuit located between a plurality of sub arrays included in a memory cell array and pre-charging the first global bit line with a second pre-charge voltage by using a second pre-charge circuit located outside the memory cell array. | 02-09-2012 |
20120092946 | MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING DISCHARGE LINES AND METHODS OF FORMING - A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line. | 04-19-2012 |
20120307680 | APPARATUS AND METHOD FOR CONTROLLING DATA TRANSMISSION/RECEPTION PATH BETWEEN SERVER AND MOBILE TERMINAL IN HETEROGENEOUS NETWORK ENVIRONMENT - A data transmission/reception path between a server and a mobile terminal in a heterogeneous network environment is controlled by mapping at least one actual Internet protocol (IP) address available to the mobile terminal in the heterogeneous network environment to at least one virtual IP to generate a path mapping table, and determining a data transmission/reception path between the server and the mobile terminal with reference to the generated path mapping table. This virtualization of terminal actual addresses with respect to a server improves service continuity in an efficient, low cost manner, independent of the need to modify the OS kernel in various devices. | 12-06-2012 |
20130098171 | APPARATUS FOR SAMPLING CARBON PARTICLE - Disclosed is an apparatus for sampling carbon particles emitted, for example, from a charcoal kiln, including: a sampling tube introducing samples including carbon particles from a carbon particle emission source; a first manifold collecting the samples introduced from the sampling tube; a first suction means transferring the samples from the carbon particle emission source to the first manifold through the sampling tube; a discharge tube discharging the samples from the first manifold; a second manifold collecting the samples introduced from the discharge tube and supplying them to a carbon particle collection unit; a second suction means transferring the samples introduced to the first manifold to the second manifold through the discharge tube; the carbon particle collection unit receiving the samples from the second manifold and collecting the carbon particles included in the samples; and a third suction means transferring the samples introduced to the second manifold to the carbon particle collection unit. | 04-25-2013 |
20130266314 | APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING VISIBLE LIGHT COMMUNICATION - A visible light communication (VLC) transmitting apparatus modulates source data to an orthogonal frequency division multiplexing (OFDM) symbol according to an OFDM modulation method, inserts a diffusion code that is allocated to the VLC transmitting apparatus into a frequency axis of the OFDM symbol, converts the OFDM symbol in which the diffusion code is inserted to a visible light modulation signal, and transmits the converted visible light modulation signal. Thereby, a signal of the VLC transmitting apparatus in which a VLC receiving apparatus wants can be easily detected. | 10-10-2013 |
20130305458 | Functional Pillow for Preventing Head Deformation of Infants Due to Posture - The present invention relates to a functional pillow for preventing positional head deformity of an infant. The functional pillow includes an inner foam member which is porous, an outer cover which encloses the inner foam member and includes a plurality of through-holes formed thereon, a head seating portion which is formed on at least one of a top surface and a bottom surface of a pillow body which includes the inner foam member and the outer cover in an eccentric position to allow a head to be placed thereon, and at least one layered auxiliary pillow which is inserted into the head seating portion and includes an auxiliary head seating portion of a different size formed on a surface. A degree of layering of the auxiliary pillow is different according to a head size. | 11-21-2013 |
20140022831 | Semiconductor Memory Device Having Dummy Bit Line - A semiconductor memory device includes a plurality of functional bit lines, at least one dummy bit line, and a dummy bit line selection unit. The at least one dummy bit line is adjacent to an outermost bit line of the functional bit lines. The dummy bit line selection unit activates the at least one dummy bit line in response to a selection control signal of one of the plurality of functional bit lines that is not adjacent to the at least one dummy bit line. The semiconductor memory device may ensure a photo margin, so that the pattern size of the functional bit lines can be made uniform. | 01-23-2014 |
20140042600 | Semiconductor Package and Manufacturing Method Thereof - A semiconductor package and manufacturing method thereof are disclosed and may include a first semiconductor device comprising a first bond pad on a first surface of the first semiconductor device, a first encapsulant material surrounding side edges of the first semiconductor device, and a redistribution layer (RDL) formed on the first surface of the first semiconductor device and on a first surface of the encapsulant material. The RDL may electrically couple the first bond pad to a second bond pad formed above the first surface of the encapsulant material. A second semiconductor device comprising a third bond pad on a first surface of the second semiconductor device may face the first surface of the first semiconductor device and be electrically coupled to the first bond pad on the first semiconductor device. The first surface of the first semiconductor device may be coplanar with the first surface of the encapsulant material. | 02-13-2014 |
20140077366 | Wafer Level Fan-Out Package With a Fiducial Die - A wafer level fan-out package with a fiducial die is disclosed and may include a semiconductor die and a transparent fiducial die both encapsulated in a molding compound resin, passivation layers on an upper surface and a lower surface of the molding compound resin except where redistribution layers are formed on upper and lower surfaces of the molding compound resin, and a metal pattern on a lower surface of the transparent fiducial die that is visible through an exposed upper surface of the transparent fiducial die. The pattern may comprise a standard coordinate for forming a through mold via utilizing laser drilling. | 03-20-2014 |
20140138788 | PACKAGE OF FINGER PRINT SENSOR AND FABRICATING METHOD THEREOF - Various aspects of the present disclosure provide a semiconductor device, for example comprising a finger print sensor, and a method for manufacturing thereof. Various aspects of the present disclosure may, for example, provide an ultra-slim finger print sensor having a thickness of 500 μm or less that does not include a separate printed circuit board (PCB), and a method for manufacturing thereof. | 05-22-2014 |
20140147970 | SEMICONDUCTOR DEVICE USING EMC WAFER SUPPORT SYSTEM AND FABRICATING METHOD THEREOF - Provided are a semiconductor device using, for example, an epoxy molding compound (EMC) wafer support system and a fabricating method thereof, which can, for example, adjust a thickness of the overall package in a final stage of completing the device while shortening a fabricating process and considerably reducing the fabrication cost. An example semiconductor device may comprise a first semiconductor die that comprises a bond pad and a through silicon via (TSV) connected to the bond pad; an interposer comprising a redistribution layer connected to the bond pad or the TSV and formed on the first semiconductor die, a second semiconductor die connected to the redistribution layer of the interposer and positioned on the interposer; an encapsulation unit encapsulating the second semiconductor die, and a solder ball connected to the bond pad or the TSV of the first semiconductor die. | 05-29-2014 |
20140342467 | APPARATUS AND METHOD FOR CONTINUOUSLY MONITORING SUBAQUEOUS TARGET HARMFUL SUBSTANCES - The present invention relates to an apparatus and method for continuously monitoring subaqueous target harmful substances. More particularly, it relates to an apparatus and method for continuously monitoring subaqueous target harmful substances by continuously measuring the concentration of the subaqueous target harmful substances. The present invention provides an apparatus and method for continuously monitoring subaqueous target harmful substances, which can continuously measure the concentration of subaqueous target harmful substances using a receptor that can selectively recognize the target harmful substances, a porous membrane fixed with the receptor, and a sensing unit that continuously measures the intensity of fluorescent signals of the target harmful substance reacting with the receptor, and can be utilized as various apparatuses and methods for continuously sensing various harmful substances necessary to continuously monitor for the management of the water quality. | 11-20-2014 |
20150027896 | METHOD FOR PRODUCING Cu2ZnSnS4-xSex (0 LESS THAN-EQUAL TO X LESS THAN-EQUAL TO 4) THIN FILM BY ONE STEP ELECTRODEPOSITION IN ELECTROLYTIC BATH CONTAINING IONIC LIQUID | 01-29-2015 |
20150029600 | Image Pickup Lens - Embodiments relate to an image pickup lens including a first lens having both convex surfaces, a second lens in the form of a positive meniscus lens and a third lens in the form of a negative meniscus lens, the first lens to the third lens being arranged in sequence from an object side to an image side. The first lens to the third lens are formed of the same material. | 01-29-2015 |