Patent application number | Description | Published |
20090263268 | Raw Magnesium Alloy Powder Material, Magnesium Alloy with High Proof Stress, Manufacturing Method of Raw Magnesium Alloy Powder Material and Manufacturing Method of Magnesium Alloy with High Proof Stress - A raw magnesium alloy powder material having a relatively small crystal grain diameter is obtained by subjecting a starting material powder having a relatively large crystal grain diameter to a plastic working in which the powder is passed through a pair of rolls to undergo compressive deformation or shear deformation. The starting material powder is a magnesium alloy powder having a fine intermetallic compound ( | 10-22-2009 |
20090304800 | Dry Coating using Twin-Screw Kneader - An object of the present invention is to provide a dry coating process that can produce a dry-coated preparation in a large amount. A large amount of dry-coated preparation can be produced more efficiently, than by prior-art processes, by a process in which a material containing core particles and a dry binder (lauric acid, myristic acid, or the like) is kneaded in a twin-screw kneader to produce dry binder particles in which the surfaces of the core particles are dry-coated with the dry binder. Further, a dry coating particle production process in which a material containing core particles, a dry binder, and a coating powder is kneaded in a twin-screw kneader can also produce a large amount of dry-coated preparation more efficiently than prior-art processes. | 12-10-2009 |
20100166593 | PRODUCTION METHOD OF EXTRUSION BILLET AND PRODUCTION METHOD OF MAGNESIUM ALLOY MATERIAL - A production method of an extrusion billet includes a step of preparing a plate or lump starting material comprising a magnesium alloy, a step of performing a plastic deformation process at a rolling reduction of 70% or more to the starting material at a temperature of 250° C. or lower to introduce a strain without generating dynamic recrystallization, a step of producing powder by granulating the material after the plastic deformation process, and a step of producing a powder billet by compressing the powder. | 07-01-2010 |
20110089272 | MANUFACTURING METHOD OF MAGNESIUM ALLOY MATERIAL - A method for manufacturing a magnesium alloy material includes the steps of: preparing a sheet or block of starting material that is made of a magnesium alloy; subjecting the starting material to a plastic working process at a temperature of 250° C. or less and a reduction ratio of 70% or more to introduce strain without causing dynamic recrystallization; pulverizing the material subjected to said plastic working process into powder; compressively deforming said powder by passing said powder between a pair of rotating rolls; and successively crushing the compressively deformed powder, which has passed between the pair of rotating rolls, into granular powder. | 04-21-2011 |
20110142710 | Ti PARTICLE-DISPERSED MAGNESIUM-BASED COMPOSITE MATERIAL, AND MANUFACTURING METHOD THEREOF - A Ti particle-dispersed magnesium-based composite material is a material having titanium particles uniformly dispersed in a magnesium matrix, and is characterized by having a titanium-aluminum compound layer at an interface between the magnesium alloy matrix and the titanium particles dispersed in the magnesium alloy matrix. | 06-16-2011 |
20110150694 | METHOD FOR MANUFACTURING Ti PARTICLE-DISPERSED MAGNESIUM-BASED COMPOSITE MATERIAL - A Ti particle-dispersed magnesium-based composite material is a material having titanium particles uniformly dispersed in a magnesium matrix. Magnesium that forms the matrix and titanium particles are bonded together,) with satisfactory wettability without titanium oxide at an interface therebetween. The Ti particle-dispersed magnesium-based composite material has a tensile strength of 230 MPa or more. | 06-23-2011 |
Patent application number | Description | Published |
20080294765 | DEVICE MANAGEMENT PROGRAM, COMMUNICATION DEVICE, AND DEVICE MANAGEMENT METHOD - The present invention teaches and claims a communication device including a communication section that performs communication with respect to a peripheral device for exchanging information; a delay time measuring section that measures a delay time elapsed from when the peripheral device is inquired for information acquisition until the peripheral device returns a response; and a delay time determining section that controls the number of communication sessions based on the delay time. The present invention further claims and teaches a device management method to maximizing communications sessions and minimizes response time. | 11-27-2008 |
20110289591 | Software Validity Period Changing Apparatus, Method,and Installation Package - A software validity period changing apparatus includes a password information storage unit, an input device, an authentication unit, and a validity period changing unit. The authentication unit calculates a first hash value of the password stored in the password information storage unit, calculates a second hash value of a password input via the input device, and determines whether the first hash value matches the second hash value. The validity period changing unit decompresses an installation package into components, the installation package including a validity period and version information on each of the components, detects a position of the validity period if it is determined that the first hash value matches the second hash value, changes the validity period identified by the position to a validity period input through the input device, changes the version information, and combines the components to reproduce the installation package. | 11-24-2011 |
20120036505 | Information Processing Apparatus that Automatically and Sequentially Displays Graphical User Interface Images and Recording Medium Storing Program - An information processing apparatus includes a display device; a storage device storing a program that includes a main program and N subsequent programs, and a subsequent processing code; and a processor displaying a GUI screen on the display device in accordance with the programs and writing program termination information in the storage device. The processor (a) terminates the main program after displaying a first GUI screen in accordance with the main program and executing the subsequent processing code, (b) displays a second GUI screen in accordance with a first subsequent program that is specified by the subsequent processing code on the basis of the program termination information and that is executed after the main program, and (c) sequentially displays third and subsequent GUI screens, in accordance with N-1 subsequent programs subsequent to the second subsequent program that is executed after the first subsequent program, until a termination condition is satisfied. | 02-09-2012 |
20140215434 | NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM STORING USER INTERFACE PROGRAM FOR DEVELOPING APPLICATION SOFTWARE - A non-transitory computer-readable recording medium that stores a user interface program for developing application software using a graphical user interface (GUI) developing unit configured to cause a user to develop application software via a GUI. The user interface program causes a computer to function as a command-line user interface (CUI)-based GUI control unit configured to control the GUI developing unit via a CUI. The GUI developing unit is configured to operate in response to an input event generated by manipulation of an input device, and the CUI-based GUI control unit is configured to pseudo-generate the input event via the CUI. | 07-31-2014 |
20150178074 | METHOD, A SYSTEM, AND A NON-TRANSITORY COMPUTER-READABLE MEDIUM FOR SUPPORTING APPLICATION DEVELOPMENT - An application development support method of the present disclosure is for generating an application by building resources including a library and a manifest file. The method includes extracting, when there are a plurality of versions of a platform being an operation target for the application, the library commonly required by all the versions of the platform from a specified resource storing area. The method includes identifying and extracting the library that is required other than commonly required by all the versions of the platform from the specified resource storing area. The method includes inquiring about a public interface relating to an un-extracted library in the specified resource storing area. The method includes generating a manifest file for a difference detected when inquiring about the public interface. The method includes connecting the generated manifest file with an existing manifest file. | 06-25-2015 |
Patent application number | Description | Published |
20110263805 | ALPHA-ALLYLOXYMETHYLACRYLIC ACID-BASED COPOLYMER, RESIN COMPOSITIONS, AND USE THEREOF - The present invention provides: resins which can be used for various applications such as radical curable resin compositions, colorant-dispersed compositions, and photosensitive resin compositions; resin compositions; and means for producing the resins. Specifically, the present invention provides an α-allyloxymethylacrylic copolymer having in its main chain a structural unit represented by formula (1): | 10-27-2011 |
20120016095 | a-(UNSATURATED ALKOXYALKYL) ACRYLATE COMPOSITION AND PROCESS FOR PRODUCTION THEREOF - An α-(unsaturated alkoxyalkyl)acrylate composition is provided which enables an α-(unsaturated alkoxyalkyl)acrylate product to be stored at a high purity for an extended period of time and can fully suppress problems such as coloration and gelation from arising during polymerization, and also a method of preparing α-(unsaturated alkoxyalkyl)acrylate compositions for enabling to obtain industrially α-(unsaturated alkoxyalkyl)acrylates safely in a high purity is also provided. | 01-19-2012 |
20130197123 | DIENE-BASED CARBOXYLATE ANION AND SALT THEREOF, AND POLYMERIZABLE OR CURABLE COMPOSITION THEREOF - The claimed invention provides a novel compound not having been studied before, that is, a diene carboxylate anion that contains a specific structure, and a salt thereof. The claimed invention further provides a diene carboxylate anion and a salt thereof, especially a metal salt thereof, which are easily soluble in general organic solvents, reactive diluents, and resins, may be in a liquid state at normal temperature depending on the structure, and have high polymerizability. Polymerization/curing of these produces a resin to which many ionic bonds and a metal are introduced, providing various properties such as hardness, scratch resistance, anti-fingerprint property, gas-barrier property, water vapor barrier property, oxygen absorption property, ultraviolet protection, infrared protection, color development and coloring, high refractive index, adhesion, various catalytic abilities, fluorescence ability and light-emitting ability, optical amplification, dispersibility, and antistatic properties. In addition, the anion and the salt can be used for raw materials for functional fine particles and for metal nanoparticle composites, and also for MOD materials. The claimed invention also provides an advantageous method for producing the diene carboxylate anion and the salt thereof. | 08-01-2013 |
Patent application number | Description | Published |
20080251816 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device is composed of a field effect transistor using the interface between a ferroelectric film and a semiconductor film as the channel and including a gate electrode to which a voltage for controlling the polarization state of the ferroelectric film is applied and source/drain electrodes provided on both ends of the channel to detect a current flowing in the channel in accordance with the polarization state. The semiconductor film is made of a material having a spontaneous polarization and the direction of the spontaneous polarization is parallel with the interface between the ferroelectric film and the semiconductor film. | 10-16-2008 |
20090097299 | SEMICONDUCTOR MEMORY DEVICE, METHOD FOR FABRICATING THE SAME AND SEMICONDUCTOR SWITCHING DEVICE - A first electrode is formed on a stacked-layer film, which is formed of a ferroelectric layer and a semiconductor layer, at the ferroelectric layer and a plurality of second electrodes are formed on the stacked-layer film at the semiconductor layer side. Each of parts of the semiconductor layer located in regions in which the second electrodes are formed functions as a resistance modulation element (memory) using the polarization assist effect of the ferroelectric layer. Information (a low resistance state or a high resistance state) held in a memory is read by detecting a value of a current flowing in each part of the semiconductor layer. Information is written in a memory by inverting a polarization of the ferroelectric layer. | 04-16-2009 |
20090152607 | FERROELECTRIC STACKED-LAYER STRUCTURE, FIELD EFFECT TRANSISTOR, AND FERROELECTRIC CAPACITOR AND FABRICATION METHODS THEREOF - A ferroelectric stacked-layer structure is fabricated by forming a first polycrystalline ferroelectric film on a polycrystalline or amorphous substrate, and after planarizing a surface of the first ferroelectric film, laminating on the first ferroelectric film a second thin ferroelectric film having the same crystalline structure as the first ferroelectric film. A field effect transistor or a ferroelectric capacitor includes the ferroelectric stacked-layer structure as a gate insulating film or a capacitor film. | 06-18-2009 |
20090290404 | SEMICONDUCTOR MEMORY DEVICE - A memory cell includes a memory element including a MFSFET having a gate insulating film made of a ferroelectric film, and a selection switching element including a MISFET having a gate insulating film made of a paraelectric film. A load element for a read operation is connected in series to the memory cell. The ferroelectric film and the paraelectric film are stacked with a semiconductor film being interposed therebetween. The semiconductor film forms a common channel shared by the MFSFET and the MISFET. The load element includes a MISFET having a channel made of the semiconductor film or a resistance element having a resistor made of the semiconductor film. | 11-26-2009 |
20110299318 | SEMICONDUCTOR MEMORY CELL AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICES - A semiconductor memory cell includes: a memory element formed by a first field effect transistor having a gate insulating film made of a ferroelectric film; and a select switching element formed by a second field effect transistor having a gate insulating film made of a paraelectric film. The ferroelectric film and the paraelectric film are stacked together with a semiconductor film of a compound semiconductor interposed therebetween. A first gate electrode of the first field effect transistor is formed on a side of the ferroelectric film, and a second gate electrode of the second field effect transistor is formed on a side of the paraelectric film so as to face the first gate electrode. The semiconductor film forms a common channel layer of the first and second field effect transistors. | 12-08-2011 |
20110299566 | PYROELECTRIC TEMPERATURE SENSOR AND A METHOD FOR MEASURING A TEMPERATURE WITH THE PYROELECTRIC TEMPERATURE SENSOR - A temperature sensor includes first and second lower electrodes, a ferroelectric layer having polarization, a semiconductor layer; and first to third upper electrodes. The second upper electrode is interposed between the first upper electrode and the third upper electrode in a plan view. The semiconductor layer includes a first channel disposed between the first upper electrode and the second upper electrode, and a second channel disposed between the second upper electrode and the third upper electrode. The ferroelectric layer includes a first ferroelectric part disposed below the first channel and a second ferroelectric part disposed below the second channel. A polarization direction of the first ferroelectric part is opposite to a polarization direction of the second first ferroelectric part. The temperature is calculated based on the output voltage from the second upper electrode and the voltage applied to the first upper electrode. | 12-08-2011 |
20110309858 | NON-VOLATILE LOGIC CIRCUIT AND A METHOD FOR OPERATING THE SAME - In a non-volatile logic circuit, a first input electrode and a second input electrode are formed on a semiconductor layer and interposed between an electric current source electrode and an output electrode in a plan view. The first input electrode is next to the second input electrode along the a direction orthogonal to the direction between the electric current source electrode and the output electrode. A method of operating the non-volatile logic circuit includes a step of writing one state selected from four states by applying voltages to the first input electrode and the second input electrode, respectively, and a step of measuring current generated by applying the voltage between the electric current power electrode and the output electrode to determine on the basis of the current, which of the high or low resistant state the non-volatile logic circuit has. | 12-22-2011 |
20110309859 | METHOD FOR OPERATING A NON-VOLATILE LOGIC CIRCUIT - In a non-volatile logic circuit, a first input electrode and a second input electrode are formed on a semiconductor layer and interposed between an electric current source electrode and an output electrode in a plan view. The semiconductor layer is disposed on a ferroelectric layer. A method of operating the non-volatile logic circuit includes a step of writing one state selected from four states by applying voltages to the first and second input electrode, respectively, a step of measuring current generated by applying the voltage between the electric current source electrode and the output electrode to determine, on the basis of the measured current, which of the high or low resistant state the non-volatile logic circuit has. | 12-22-2011 |
20110309860 | NONVOLATILE LOGIC CIRCUIT AND A METHOD FOR OPERATING THE SAME AS AN EXCLUSIVE-OR (XOR) CIRCUIT - A non-volatile logic circuit includes a control electrode, a ferroelectric layer disposed on the control electrode, a semiconductor layer disposed on the ferroelectric layer, a power electrode and an output electrode disposed on the semiconductor layer, and first to fourth input electrodes disposed on the semiconductor layer. The first and second input electrodes receive first and second inputs, respectively. The third and fourth input electrodes receive inversion signals of the second and first input signal, respectively. A resistance value of the semiconductor layer between the power electrode and the output electrode varies according to the first input signal and the second input signal so that an exclusive-OR signal of the first and second input signals is output from the output electrode. | 12-22-2011 |
20110310650 | SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF OPERATING THEREOF - In the operating method of the semiconductor memory device, (1) voltages V | 12-22-2011 |
20120008365 | METHOD FOR OPERATING A NONVOLATILE SWITCHING DEVICE - A method of flowing a current selectively with a nonvolatile switching device according to the present disclosure includes a step of configuring, in the nonvolatile switching device, any one of a first state in which a current does not flow between the electrode group, a second state in which a current flows selectively between the first electrode and the second electrode, and a third state in which a current flows selectively between the first electrode and the third electrode. When any one of the first state, the second state and the third state is configured, voltages V | 01-12-2012 |
20120068732 | NONVOLATILE LOGIC CIRCUIT AND A METHOD FOR OPERATING THE SAME - A nonvolatile logic circuit includes logic configuration electrodes and input electrodes. The nonvolatile logic circuit is programmable to any one of the logics between the input signals selected from logical conjunction (AND), logical disjunction (OR), logical non-conjunction (NAND), logical non-disjunction (NOR), and logical exclusive disjunction (XOR) by changing applied voltages to the logic configuration electrodes. | 03-22-2012 |
20120112787 | NONVOLATILE LOGIC CIRCUIT AND A METHOD FOR OPERATING THE SAME - A nonvolatile logic circuit includes logic configuration electrodes and input electrodes. The nonvolatile logic circuit is programmable to any one of the logics between the input signals selected from logical conjunction (AND), logical disjunction (OR), logical non-conjunction (NAND), logical non-disjunction (NOR), and logical exclusive disjunction (XOR) by changing applied voltages to the logic configuration electrodes. | 05-10-2012 |
20120217996 | NONVOLATILE LOGIC CIRCUIT AND A METHOD FOR OPERATING THE SAME - A nonvolatile logic circuit includes logic configuration electrodes and input electrodes. The nonvolatile logic circuit is programmable to any one of the logics between the input signals selected from logical conjunction (AND), logical disjunction (OR), logical non-conjunction (NAND), logical non-disjunction (NOR), and logical exclusive disjunction (XOR) by changing applied voltages to the logic configuration electrodes. | 08-30-2012 |
20120217997 | NONVOLATILE LOGIC CIRCUIT AND A METHOD FOR OPERATING THE SAME - A nonvolatile logic circuit includes logic configuration electrodes and input electrodes. The nonvolatile logic circuit is programmable to any one of the logics between the input signals selected from logical conjunction (AND), logical disjunction (OR), logical non-conjunction (NAND), logical non-disjunction (NOR), and logical exclusive disjunction (XOR) by changing applied voltages to the logic configuration electrodes. | 08-30-2012 |
20130009713 | RESISTANCE-CAPACITANCE OSCILLATION CIRCUIT - A resistance-capacitance oscillation circuit comprises an amplifier and a phase shifting circuit. The phase shifting circuit comprises at least three resistance-capacitance circuit elements, which comprise a resistance and a capacitance. At least one of the resistance-capacitance circuit elements comprises a variable resistance and a variable capacitance. The variable resistance is formed of a first electrode, a second electrode, a part of a semiconductor film, a part of a ferroelectric film, and a fourth electrode. The variable capacitor is formed of the second electrode, a third electrode, a fifth electrode, another part of the ferroelectric film, another part of the semiconductor film, and a paraelectric film. | 01-10-2013 |
20130009714 | RESISTANCE-CAPACITANCE OSCILLATION CIRCUIT - A resistance-capacitance oscillation circuit comprises an amplifier and a phase shifting circuit. The phase shifting circuit comprises at least three resistance-capacitance circuit elements, each of which comprises a resistance and a capacitor. At least one of the resistance-capacitance circuit elements comprises a variable resistance and a variable capacitor. The variable resistance is formed of a first electrode, a second electrode, a part of a semiconductor film, a part of a ferroelectric film, and a fourth electrode. The variable capacitor is formed of the second electrode, a third electrode, a fifth electrode, another part of the ferroelectric film, another part of the semiconductor film, and a paraelectric film. | 01-10-2013 |
20130094274 | METHOD FOR DRIVING SEMICONDUCTOR MEMORY DEVICE - An object of the present invention is to provide a novel method for driving a semiconductor memory device. | 04-18-2013 |
20130311414 | LEARNING METHOD OF NEURAL NETWORK CIRCUIT - A neuron circuit in a neural network circuit element includes a waveform generating circuit for generating a predetermined pulse voltage, and a first input signal has a waveform of the predetermined pulse voltage. For a period having a predetermined duration of the predetermined pulse voltage generated within the neural network circuit element including the variable resistance element which is applied with the first input signal from another neural network circuit element, the first input signal is permitted to be input to the control electrode of the variable resistance element, to change the resistance value of the variable resistance element due to an electric potential difference generated between the first electrode and the control electrode which occurs depending on an input timing of the first input signal with respect to the period during which the first input signal is permitted to be input to the control electrode. | 11-21-2013 |
20130311415 | LEARNING METHOD OF NEURAL NETWORK CIRCUIT - A neuron circuit in a neural network circuit element includes a waveform generating circuit for generating a bipolar sawtooth pulse voltage, and a first input signal has a bipolar sawtooth pulse waveform. For a period during which the first input signal is permitted to be input to a first electrode of a variable resistance element, the bipolar sawtooth pulse voltage generated within the neural network circuit element including the variable resistance element which is applied with the first input signal from another neural network circuit element is input to a control electrode of the variable resistance element. The resistance value of the variable resistance element changes due to an electric potential difference between the first electrode and the control electrode, the electric potential difference being generated depending on an input timing difference between a voltage applied to the first electrode and the voltage applied to the control electrode. | 11-21-2013 |
20140016395 | METHOD OF DRIVING NONVOLATILE SEMICONDUCTOR DEVICE - Pulse voltages V1 and V2 are applied to the first upper gate electrode and the second upper gate electrode, respectively, for a period T1 which is shorter than a period necessary to invert all the polarizations included in the ferroelectric film, while voltages Vs, Vd, and V3 are applied to the source electrode, the drain electrode, and the lower gate electrode film, respectively, so as to increase the values of the widths WRH1 and WRH2 and so as to decrease the value of the width WRL. The pulse voltages V1 and V2 have a smaller voltage than a voltage necessary to invert all the polarizations included in the ferroelectric film. The voltage Vs, the voltage Vd, the voltage V3, the pulse voltage V1, and the pulse voltage V2 satisfy the following relationship: Vs, Vd, V301-16-2014 | |
20140112051 | METHOD OF DRIVING NONVOLATILE SEMICONDUCTOR DEVICE - Pulse voltages V | 04-24-2014 |
20150100614 | RANDOM NUMBER GENERATING DEVICE - A random number generating device of the present disclosure includes: an arithmetic random number generator that generates an arithmetic random number sequence; an arithmetic random number converter that sequentially reads at least one arithmetic random number from the arithmetic random number sequence and converts a value of the read arithmetic random number into a voltage or current value of at least two predetermined levels of gray scale having an identical polarity; a hysteresis unit that outputs values depending on a presently-input voltage or current value and a previously-input voltage or current value with respect to the sequentially-input voltage or current value; and a threshold processor that binarizes the output of the hysteresis unit. | 04-09-2015 |
20150155467 | ELECTROCALORIC MATERIAL - Provided is an electrocaloric material formed of a crystal represented by the composition formula Hf | 06-04-2015 |
20150178619 | NEURAL NETWORK CIRCUIT AND LEARNING METHOD THEREOF - In a neural network circuit element, a neuron circuit includes a waveform generating circuit for generating an analog pulse voltage, and a switching pulse voltage which is input as a first input signal to another neural network circuit element; a synapse circuit is configured such that the analog pulse voltage generated in the neuron circuit of the neural network circuit element including the synapse circuit is input to a third terminal of a variable resistance element of the synapse circuit, for a permissible input period, in the first input signal from another neural network circuit element; and the synapse circuit is configured such that the resistance value of the variable resistance element is changed in response to an electric potential difference between a first terminal and the third terminal, which occurs depending on a magnitude of the analog pulse voltage for the permissible input period. | 06-25-2015 |