Patent application number | Description | Published |
20130131483 | HEART RATE ALARM SYSTEM - A heart rate alarm system includes an article of clothing, at least two conductive units, at least one alarm device, a heart rate measurement unit, a first transmission unit, a second transmission unit, and an operation unit. The at least two conductive units are coupled to each other through at least one conductive fibric. The heart rate measurement unit measures a heart rate through the at least two conductive units, and generates a control signal and a heart rate value according to the heart rate. The first transmission unit transmits the control signal to the at least one alarm device and transmits the heart rate value. The at least one alarm device generates at least one alarm signal according to the control signal. The operation unit calculates a heart beat period, a heart physiological age, indicators of autonomic nervous system, and/or a calorie consumption indicator. | 05-23-2013 |
20130131524 | BLOOD PRESSURE MEASUREMENT SYSTEM - A blood pressure measurement system includes an article of clothing, an occluding cuff, a blood pressure measurement unit, a first transmission module, and an operation module. The clothing includes tarpaulin. The occluding cuff is disposed at an inner side of the tarpaulin. The blood pressure measurement unit is disposed at the inner side of the tarpaulin for measuring blood pressure of a user to generate a blood pressure measurement result of the user, controlling a removable inflation module to inflate the occluding cuff, controlling a deflate valve to deflate the occluding cuff, and transmitting the blood pressure measurement result. The first transmission module is used for receiving the blood pressure measurement result. The operation module is coupled to the first transmission module for calculating diastolic blood pressure, systolic blood pressure, and/or pulses of the user according to the blood pressure measurement result. | 05-23-2013 |
20140264872 | Metal Capping Layer for Interconnect Applications - An integrated circuit structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The integrated circuit structure further includes a conductive wiring in the dielectric layer. The integrated circuit structure also includes a first metallic capping layer over the conductive wiring and a second metallic capping layer over the first metallic capping layer. The second metallic capping layer has a width substantially the same as a width of the first metallic capping layer. | 09-18-2014 |
Patent application number | Description | Published |
20110017407 | CHIP SORTING APPARATUS - A chip sorting apparatus comprising a chip holder comprising a first surface and an second surface opposite to the first surface; a wafer comprising a first chip disposed on a first position of the first surface; a first chip receiver comprising a third surface and an fourth surface opposite to the third surface, wherein the third surface is opposite to the first surface; a pressurization device making the first chip and the third surface of the first chip receiver adhered to each other through pressuring the second surface at where corresponding to the first position; and a separator decreasing the adhesion between the first chip and the first surface. | 01-27-2011 |
20140027790 | AGGREGATION OF SEMICONDUCTOR DEVICES AND THE METHOD THEREOF - An aggregation of semiconductor devices, comprising: a first layer comprising a first surface and a second surface; a second layer comprising a first region and a second region; and a plurality of semiconductor devices disposed between the first layer and the second region wherein a shape of the second region comprises a curve and a mark. | 01-30-2014 |
20140202627 | CHIP SORTING APPARATUS - A method of chip sorting comprises providing a chip holder having a first surface; providing multiple chips on the first surface; providing a chip receiver having a second surface, wherein the second surface faces the first surface; attaching the multiple chips to the second surface; decreasing an adhesion between the multiple chips and the first surface; and separating the multiple chips from the first surface after the step of decreasing the adhesion between the multiple chips and the first surface. | 07-24-2014 |
20150187986 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method of fabricating an optoelectronic device, comprising: providing a substrate, wherein the substrate comprises a first major surface and a second major surface opposite to the first major surface; forming a light emitting stack on the second major surface of the substrate; forming a supporting layer covering the light emitting stack; forming a plurality of first modified regions in the substrate by employing a first energy into the substrate after forming the supporting layer; and cleaving the substrate. | 07-02-2015 |
20150194581 | AGGREGATION OF SEMICONDUCTOR DEVICES AND THE METHOD THEREOF - A method of manufacturing an aggregation of semiconductor devices comprising the steps of providing a first layer; sequentially addressing and adhering a plurality of semiconductor devices to the first layer to form a shape having a curve; providing a second layer; and adhering the second layer to the first layer. | 07-09-2015 |
Patent application number | Description | Published |
20130137266 | MANUFACTURING TECHNIQUES TO LIMIT DAMAGE ON WORKPIECE WITH VARYING TOPOGRAPHIES - Some embodiments relate to a method for processing a workpiece. In the method, a first photoresist layer is provided over the workpiece, wherein the first photoresist layer has a first photoresist tone. The first photoresist layer is patterned to provide a first opening exposing a first portion of the workpiece. A second photoresist layer is then provided over the patterned first photoresist layer, wherein the second photoresist layer has a second photoresist tone opposite the first photoresist tone. The second photoresist layer is then patterned to provide a second opening that at least partially overlaps the first opening to define a coincidentally exposed workpiece region. A treatment is then performed on the coincidentally exposed workpiece region. Other embodiments are also disclosed. | 05-30-2013 |
20130181320 | Manufacturing Techniques for Workpieces with Varying Topographies - Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist tone opposite the first photoresist tone, is provided over the first patterned photoresist layer. An opening extends through the first and second patterned photoresist layers to allow a treatment to be applied to the workpiece through the opening. Other embodiments are also disclosed. | 07-18-2013 |
20130207163 | Semiconductor Devices and Manufacturing Methods Thereof - Semiconductor devices and manufacturing methods thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece with a first region having a plurality of first features and a second region having a plurality of second features proximate the first region. The first region and the second region share a patterning overlap region disposed between the first region and the second region. The patterning overlap region includes a residue feature with an aspect ratio of about 4 or less. | 08-15-2013 |
20130302985 | METHOD OF REMOVING RESIDUE DURING SEMICONDUCTOR DEVICE FABRICATION - A method is described including forming a first photoresist feature and a second photoresist feature on a semiconductor substrate. A chemical material coating is formed on the semiconductor substrate. The chemical material coating interposes the first and second photoresist features. The semiconductor substrate is then rinsed; the rinsing removes the chemical material coating from the semiconductor substrate. The chemical material may mix with a residue disposed on the substrate between the first and second photoresist features. Removing the chemical material coating from the substrate may also remove the residue. | 11-14-2013 |
20140080067 | METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate having two different topography areas adjacent to each other. A step-forming material (SFM) is deposited over the substrate. A patterned SFM is formed in the low topography area of the two areas. The formation of the patterned SFM provides a fairly planar surface across over the substrate. | 03-20-2014 |
20140151699 | Test Structure Placement on a Semiconductor Wafer - A method of fabricating integrated circuit devices is provided. The method includes forming a plurality of spaced integrated circuit dies on a semiconductor wafer and forming a dedicated test die on the semiconductor wafer adjacent the plurality of spaced integrated circuit dies, the dedicated test die including a test structure having a first width when viewed in a top view and being operable to generate wafer evaluation data. Further, the method includes forming a scribe line region interposed between the plurality of spaced integrated circuit dies, the scribe line region having a second width defined by a distance between adjacent integrated circuit dies when viewed in a top view, the second width being smaller than the first width, and the scribe line region being free of test structures. | 06-05-2014 |
20140272715 | Lithography Process on High Topology Features - A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist. | 09-18-2014 |
20150249109 | METHOD OF FABRICATING A METAL GRID FOR SEMICONDUCTOR DEVICE - A method for manufacturing the image sensor device is provided. The method includes depositing a first dielectric layer over a back surface of a substrate, forming a ridge over the first dielectric layer, depositing a second dielectric layer over the first dielectric layer, including filling in a space between two adjacent ridges. The method also includes removing the ridge to form a trench in the second dielectric layer and forming a metal grid in the trench. | 09-03-2015 |
Patent application number | Description | Published |
20120033404 | ILLUMINATION DEVICE - An illumination device includes a base, a light-emitting module, a first layer, and a second layer. The light-emitting module is disposed on the base for generating a progressive-type light-emitting intensity. The first layer encapsulates the light-emitting module. The second layer encloses the first layer. The second layer has a progressive-type thickness corresponding to the progressive-type light-emitting intensity, and both the progressive-type light-emitting intensity and the progressive-type thickness are decreased or increased gradually, thus the progressive-type light-emitting intensity can be transformed into the same light-emitting intensity through the progressive-type thickness of the second layer. | 02-09-2012 |
20130087816 | ILLUMINATION DEVICE - An illumination device includes a base, a light-emitting module, a first layer, and a second layer. The light-emitting module is disposed on the base for generating a progressive-type light-emitting intensity. The first layer encapsulates the light-emitting module. The second layer encloses the first layer. The second layer has a progressive-type thickness corresponding to the progressive-type light-emitting intensity, and both the progressive-type light-emitting intensity and the progressive-type thickness are decreased or increased gradually, thus the progressive-type light-emitting intensity can be transformed into the same light-emitting intensity through the progressive-type thickness of the second layer. | 04-11-2013 |
20150084499 | ILLUMINATION DEVICE - An illumination device includes a base, a light-emitting module, a first layer, and a second layer. The light-emitting module is disposed on the base for generating a progressive-type light-emitting intensity. The first layer encapsulates the light-emitting module. The second layer encloses the first layer. The second layer has a progressive-type thickness corresponding to the progressive-type light-emitting intensity, and both the progressive-type light-emitting intensity and the progressive-type thickness are decreased or increased gradually, thus the progressive-type light-emitting intensity can be transformed into the same light-emitting intensity through the progressive-type thickness of the second layer. | 03-26-2015 |
Patent application number | Description | Published |
20100207716 | Overcurrent protection structure and method and apparatus for making the same - The overcurrent protection structure according to the present invention mainly comprises a fusible fuse structure unit disposed in a coating, and the both ends of the fusible fuse structure unit extend outwardly beyond the coating and form a first electrode and a second electrode. In the manufacturing process, the gas-assisted injection molding process enables at least one space for accommodating gas disposed between the fusible fuse structure unit and the coating such that the heat generated by the electrically energized the fusible fuse structure unit will not dissipate through the heat conduction of the coating in order to ensure that it will blow at high temperature when reaching a specific current or a specific temperature and the circuit protection effect. | 08-19-2010 |
20100265031 | Surface mount thin film fuse structure and method of manufacturing the same - The present invention discloses a surface mount thin film fuse structure including a fusible fuse circuit structure disposed on a side of an insulating substrate, and the fusible fuse circuit structure has a fusible link portion electrically connected between two opposite electrode portions. If an overload current is passed through the fusible link portion, the fusible link portion will be melted down by a high temperature or a specific temperature to achieve the over current protection effect. At least one space is defined between the fusible link portion and the insulating substrate, such that a heat generated by the electrically energized the fusible link portion will not be dissipated through the heat conduction of the insulating substrate to achieve the circuit protection effect. | 10-21-2010 |
20110285497 | THERMAL FUSE - The thermal fuse according to the present invention has its conducting element made of red brass and, additionally, a thin layer of silver is coated over the conducting element. As such, the conducting element has substantially identical thermal coefficient as that of a red-brass casing, and the robustness against heat of the conducting element's petals is compatible with that of the casing. In this way, the conducting element will not be stuck with the casing when an overloading current emerges. The thermal fuse therefore is significantly more reliable than a conventional thermal fuse. | 11-24-2011 |
20130057382 | THERMAL FUSE - A thermal fuse which has its conducting element made of red brass. As such, the conducting element has an identical thermal coefficient as that of a red-brass casing, and the robustness against heat of the conducting element's petals is compatible with that of the casing. In this way, the conducting element will not be stuck with the casing when an overloading current emerges. The thermal fuse therefore is significantly more reliable than a conventional thermal fuse. | 03-07-2013 |
20130212874 | METHOD OF MANUFACTURING FUSE ASSEMBLY - A method of manufacturing a fuse assembly having a main body, two metal legs, and a meltable rod, the meltable rod having two outer ends connected with two inner ends of the metal legs, consisting of following steps: pre-coating a tin layer on an inner surface of respective one of the inner ends of the metal legs; winding the upper ends of the metal legs around the outer ends of the meltable rod; and applying predetermined temperature and pressure on both sides of the inner ends of the metal legs thereby melting the tin layer and completely filling the tin layer between the upper ends of the metal legs and the outer ends of the meltable rod without any space. | 08-22-2013 |