Patent application number | Description | Published |
20080254233 | PLASMA-INDUCED CHARGE DAMAGE CONTROL FOR PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION PROCESSES - Methods of depositing amorphous carbon films on substrates are provided herein. The methods reduce or prevent plasma-induced charge damage to the substrates from the deposition of the amorphous carbon films. In one aspect, an initiation layer of amorphous carbon is deposited at a low RF power level and/or at a low hydrocarbon compound/inert gas flow rate ratio before a bulk layer of amorphous carbon is deposited. After the deposition of the initiation layer, the RF power, hydrocarbon flow rate, and inert gas flow rate may be ramped to final values for the deposition of the bulk layer, wherein the RF power ramp rate is typically greater than the ramp rates of the hydrocarbon compound and of the inert gas. In another aspect, a method of minimizing plasma-induced charge damage includes depositing a seasoning layer on one or more interior surfaces of a chamber before the deposition of the amorphous carbon film on a substrate therein or coating the interior surfaces with an oxide or dielectric layer during manufacturing. | 10-16-2008 |
20090014127 | SYSTEMS FOR PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION AND BEVEL EDGE ETCHING - Embodiments described herein relate to a substrate processing system that integrates substrate edge processing capabilities. Illustrated examples of the processing system include, without limitations, a factory interface, a loadlock chamber, a transfer chamber, and one or more twin process chambers having two or more processing regions that are isolatable from each other and share a common gas supply and a common exhaust pump. The processing regions in each twin process chamber include separate gas distribution assemblies and RF power sources to provide plasma at selective regions on a substrate surface in each processing region. Each twin process chamber is thereby configured to allow multiple, isolated processes to be performed concurrently on at least two substrates in the processing regions. | 01-15-2009 |
20090017635 | APPARATUS AND METHOD FOR PROCESSING A SUBSTRATE EDGE REGION - The present invention comprises an apparatus and method for etching at a substrate edge region. In one embodiment, the apparatus comprises a chamber having a process volume, a substrate support arranged inside the process volume and having a substrate support surface, a plasma generator coupled to the chamber and configured to supply an etching agent in a plasma phase to a peripheral region of the substrate support surface, and a gas delivery assembly coupled to a gas source for generating a radial gas flow over the substrate support surface from an approximately central region of the substrate support surface toward the peripheral region of the substrate support surface. | 01-15-2009 |
20090093112 | METHODS AND APPARATUS OF CREATING AIRGAP IN DIELECTRIC LAYERS FOR THE REDUCTION OF RC DELAY - A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches. | 04-09-2009 |
20090093128 | METHODS FOR HIGH TEMPERATURE DEPOSITION OF AN AMORPHOUS CARBON LAYER - Methods for high temperature deposition an amorphous carbon film with improved step coverage are provided. In one embodiment, a method for of depositing an amorphous carbon film includes providing a substrate in a process chamber, heating the substrate at a temperature greater than 500 degrees Celsius, supplying a gas mixture comprising a hydrocarbon compound and an inert gas into the process chamber containing the heated substrate, and depositing an amorphous carbon film on the heated substrate having a stress of between 100 mega-pascal (MPa) tensile and about 100 mega-pascal (MPa) compressive. | 04-09-2009 |
20100051098 | HIGH QUALITY TCO-SILICON INTERFACE CONTACT STRUCTURE FOR HIGH EFFICIENCY THIN FILM SILICON SOLAR CELLS - A method and apparatus for forming solar cells is provided. In one embodiment, a photovoltaic device includes a first TCO layer disposed on a substrate, a second TCO layer disposed on the first TCO layer, and a p-type silicon containing layer formed on the second TCO layer. In another embodiment, a method of forming a photovoltaic device includes forming a first TCO layer on a substrate, forming a second TCO layer on the first TCO layer, and forming a first p-i-n junction on the second TCO layer. | 03-04-2010 |
20100096687 | NON-VOLATILE MEMORY HAVING SILICON NITRIDE CHARGE TRAP LAYER - A flash memory device and methods of forming a flash memory device are provided. The flash memory device includes a doped silicon nitride layer having a dopant comprising carbon, boron or oxygen. The doped silicon nitride layer generates a higher number and higher concentration of nitrogen and silicon dangling bonds in the layer and provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device. | 04-22-2010 |
20100096688 | NON-VOLATILE MEMORY HAVING CHARGE TRAP LAYER WITH COMPOSITIONAL GRADIENT - A flash memory device and method of forming a flash memory device are provided. The flash memory device includes a silicon nitride layer having a compositional gradient in which the ratio of silicon to nitrogen varies through the thickness of the layer. The silicon nitride layer having a compositional gradient of silicon and nitrogen provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device. | 04-22-2010 |
20100099247 | FLASH MEMORY WITH TREATED CHARGE TRAP LAYER - A methods of forming a flash memory device are provided. The flash memory device comprises a silicon dioxide layer on a substrate and a silicon nitride layer that is formed on the silicon dioxide layer. The properties of the silicon nitride layer can be modified by any of: exposing the silicon nitride layer to ultraviolet radiation, exposing the silicon nitride layer to an electron beam, and by plasma treating the silicon nitride layer. A dielectric material is deposited on the silicon nitride layer and a conductive date is formed over the dielectric material. The flash memory device with modified silicon nitride layer provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device. | 04-22-2010 |
20110090613 | APPARATUS AND METHOD FOR SUBSTRATE CLAMPING IN A PLASMA CHAMBER - The present invention generally provides methods and apparatus for monitoring and maintaining flatness of a substrate in a plasma reactor. Certain embodiments of the present invention provide a method for processing a substrate comprising positioning the substrate on an electrostatic chuck, applying an RF power between the an electrode in the electrostatic chuck and a counter electrode positioned parallel to the electrostatic chuck, applying a DC bias to the electrode in the electrostatic chuck to clamp the substrate on the electrostatic chuck, and measuring an imaginary impedance of the electrostatic chuck. | 04-21-2011 |
20110092077 | METHOD TO MINIMIZE WET ETCH UNDERCUTS AND PROVIDE PORE SEALING OF EXTREME LOW K (K<2.5) DIELECTRICS - Methods of processing films on substrates are provided. In one aspect, the methods comprise treating a patterned low dielectric constant film after a photoresist is removed form the film by depositing a thin layer comprising silicon, carbon, and optionally oxygen and/or nitrogen on the film. The thin layer provides a carbon-rich, hydrophobic surface for the patterned low dielectric constant film. The thin layer also protects the low dielectric constant film from subsequent wet cleaning processes and penetration by precursors for layers that are subsequently deposited on the low dielectric constant film. | 04-21-2011 |
20110104891 | METHODS AND APPARATUS OF CREATING AIRGAP IN DIELECTRIC LAYERS FOR THE REDUCTION OF RC DELAY - A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches. | 05-05-2011 |
20110263074 | APPARATUS AND METHODS FOR REDUCING LIGHT INDUCED DAMAGE IN THIN FILM SOLAR CELLS - Apparatus and methods for forming a silicon-containing i-layer on a substrate for a thin film photovoltaic cell are disclosed. The apparatus includes a chamber body defining a processing region containing the substrate, a hydrogen source and a silane source coupled to a plasma generation region, an RF power source that applies power at a power level in the plasma generation region to generate a plasma and deposit the silicon-containing i-layer at a selected deposition rate to a selected thickness and a controller. The controller controls the power level and the deposition rate of the i-layer on the substrate such that the thin film solar cell exhibits light induced damage that conforms to a linear fit of the product of the RF power, the deposition rate and the selected thickness of the i-layer. In accordance with further aspects of the present invention, the controller controls the RF power and the deposition rate so that a product (x) of the RF power in watts, the deposition rate of the i-layer in nm per min and the thickness of the i-layer in nm is less than a predetermined number y and satisfies the equation y=5E11*x+3.3749 plus or minus a margin. | 10-27-2011 |
20120199071 | PLASMA IMMERSION CHAMBER - Embodiments described herein relate to a plasma chamber and processing system utilizing robust components. In one embodiment, a chamber is provided. The chamber includes a body having an interior volume, a gas distribution assembly disposed in the interior volume opposing a substrate support, the gas distribution assembly having a coolant channel disposed thereon, and a first hollow conduit and a second hollow conduit coupled to the body and in fluid communication with the interior volume. | 08-09-2012 |
20120211164 | SYSTEMS FOR PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION AND BEVEL EDGE ETCHING - Embodiments described herein relate to a substrate processing system that integrates substrate edge processing capabilities. Illustrated examples of the processing system include, without limitations, a factory interface, a loadlock chamber, a transfer chamber, and one or more twin process chambers having two or more processing regions that are isolatable from each other and share a common gas supply and a common exhaust pump. The processing regions in each twin process chamber include separate gas distribution assemblies and RF power sources to provide plasma at selective regions on a substrate surface in each processing region. Each twin process chamber is thereby configured to allow multiple, isolated processes to be performed concurrently on at least two substrates in the processing regions. | 08-23-2012 |
20130008878 | THERMAL FLUX ANNEALING INFLUENCE OF BURIED SPECIES - A method including introducing a species into a substrate including semiconductor material; and translating linearly focused electromagnetic radiation across a surface of the substrate, the electromagnetic radiation being sufficient to thermally influence the species. An apparatus including an electromagnetic radiation source; a stage having dimensions suitable for accommodating a semiconductor substrate within a chamber; an optical element disposed between the electromagnetic radiation source and the stage to focus radiation from the electromagnetic radiation source into a line having a length determined by the diameter of a substrate to be placed on the stage; and a controller coupled to the electromagnetic radiation source including machine readable program instructions that allow the controller to control the depth into which a substrate is exposed to the radiation. | 01-10-2013 |
20130242287 | Process and Apparatus for Measuring the Crystal Fraction of Crystalline Silicon Casted Mono Wafers - Provided are methods and apparatus for determining the crystal fraction of a casted-mono silicon wafer. A light source is directed at the wafer and the transmission or reflection is measured by a detector. An image of the wafer is generated by a processor and the crystal fraction is calculated from the generated image. The crystal fraction is correlated to the efficiency of the solar cell produced, allowing for the rejection of inferior wafers prior to processing. | 09-19-2013 |