Plevridis
Sofoklis Plevridis, Athens GR
Patent application number | Description | Published |
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20090088086 | MODIFIED DUAL BAND DIRECT CONVERSION ARCHITECTURE THAT ALLOWS EXTENSIVE DIGITAL CALIBRATION - A communication device may include one or more circuits in an integrated transmitter and receiver that includes a transmit path and a receive path. The transmit path may include an I processing baseband transmit path and a Q processing baseband transmit path. The receive path may include an I processing baseband receive path and a Q processing baseband receive path. The one or more circuits may enable sharing a first common filter by the I processing baseband transmit path and the I processing baseband receive path. The one or more circuits may also enable sharing a second common filter by the Q processing baseband transmit path and the Q processing baseband receive path. The first common filter and the second common filter are independently programmable to adjust a phase and/or a gain of the said first common filter, and/or a phase and/or a gain of the second common filter. | 04-02-2009 |
20100233971 | DIRECT-CONVERSION TRANSCEIVER ENABLING DIGITAL CALIBRATION - A method for calibrating a transceiver includes selecting one of a plurality of available calibration paths on the transceiver to be active. The transceiver includes a transmitter and a receiver. The selected one of the plurality of available calibration paths couples the transmitter to the receiver through a circuit that is external to the transceiver. A calibration signal may be provided to enable calibration of the transceiver via the selected one of the plurality of available calibration paths. The calibration signal may be received after it has passed through the selected one of the plurality of calibration paths. Characteristics of the transceiver may be measured using the received calibration signal. | 09-16-2010 |
Sofoklis E. Plevridis, Glyfada GR
Patent application number | Description | Published |
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20090156149 | Multi-mode transmit and receive PLL - A local oscillator (LO) signal generator that has a reference phase-locked loop (PLL), a receiver LO PLL and a transmitter LO PLL. A reference PLL is coupled to receive a reference clock input and to generate a reference PLL signal at its output, which then drives a receiver PLL and a transmitter PLL. The receiver PLL is coupled to receive the reference PLL signal and to use the reference PLL signal as its reference input to generate a receiver LO signal at its output. The transmitter PLL is coupled to receive the reference PLL signal and to use the reference PLL signal as its reference input to generate a transmitter LO signal at its output. | 06-18-2009 |
Sofoklis Emmanouel Plevridis, Glyfada GR
Patent application number | Description | Published |
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20090195958 | METHOD AND SYSTEM FOR VARACTOR LINEARIZATION - Aspects of a method and system for varactor linearization are provided. In this regard, a relationship between control voltage and capacitance of a variable capacitor may be controlled utilizing a plurality of bias voltages communicatively coupled to a corresponding plurality of bias terminals of said variable capacitor. The variable capacitor may comprise a plurality of two-terminal unit varactors and a first terminal of each unit varactor may be coupled to an RF terminal of the variable capacitor, a second terminal of one of the unit varactors may be coupled to the control voltage, and a second terminal of each of the remaining unit varactors may be coupled to one of the bias voltages. The bias voltages may be generated via a resistor ladder and/or via the resistive nature of a portion of semiconductor substrate. The bias voltages may linearize the relationship between the control voltage and the capacitance. | 08-06-2009 |