Kulkarni, NY
Ambarish Kulkarni, Niskayuna, NY US
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20140272164 | TUBE COATERS AND METHODS OF USING SAME - The present application provides for coaters, and methods of using coaters, configured to coat tubes, rods or like members. The coaters may include a coating reservoir configured to apply a coating to the exterior surface of such members. The coating reservoir may include at least one void, first and second ends with first and second apertures, respectively, in communication with the at least one void, at least one port in communication with the at least one void, and coating delivery material positioned within the at least one void. The first aperture, second aperture, and coating delivery material may define a coating passageway through the coating reservoir. An engagement portion of the coating delivery material may define the narrowest portion of the coating pathway and be effective in supporting and coating the exterior surface of a member as the member passes, or is passed, through the coating passageway. | 09-18-2014 |
Ambarish Jayant Kulkarni, Glenville, NY US
Patent application number | Description | Published |
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20130105027 | ARTICLES COMPRISING A HYDRATE-INHIBITING SILICONE COATING | 05-02-2013 |
20130108810 | METHOD OF COATING A SURFACE AND ARTICLE INCORPORATING COATED SURFACE | 05-02-2013 |
20140178641 | METHODS OF COATING A SURFACE AND ARTICLES WITH COATED SURFACE - A method of coating a surface is provided. The method comprises feeding a feedstock to a thermal spray torch, the feedstock comprising a liquid, disposing the feedstock on a substrate by thermal spray under conditions selected to produce a textured surface comprising a hierarchical structure, wherein the hierarchical structure comprises agglomerations of at least partially melted and solidified particles derived from the feedstock with individual at least partially melted and solidified particles derived from the feedstock disposed on a surface of the agglomerations; and applying a surface energy modification material over the textured surface. An article comprising a component having a coated surface is also provided. | 06-26-2014 |
20150083227 | REDUCED FLUID DRAG ACROSS A SOLID SURFACE WITH A TEXTURED COATING - An article includes a substrate with a coating having asperities such that an average spacing between the asperities is between about 0.01 and about 1.5 micron. An average surface roughness of the coating is up to about 2 microns, and an average porosity of the coating is in the range from about 35% to about 70%. A material to reduce surface energy is disposed on the coating. A method for making such an article and a method for decreasing fluid drag across such an article are also provided. | 03-26-2015 |
20150114903 | ARTICLE AND APPARATUS FOR ENHANCING THE COALESCENCE OF A DISPERSED PHASE FROM A CONTINUOUS PHASE IN AN EMULSION - An apparatus for enhancing the coalescence of a dispersed phase from a continuous phase in an emulsion is presented. The apparatus includes at least one inlet for receiving the emulsion, at least one outlet for discharging the emulsion after coalescing the dispersed phase, and at least one article disposed between the inlet and the outlet. The article includes a plurality of regions disposed on a surface in a predefined pattern, wherein a portion of the plurality of regions is substantially wetting with respect to the dispersed phase, and a portion of the plurality of regions is substantially non-wetting with respect to the dispersed phase, and wherein the pattern includes a plurality of inter-connected regions that are substantially non-wetting with respect to the dispersed phase. A related article is also presented. | 04-30-2015 |
Ambarish Jayant Kulkarni, Niskayuna, NY US
Patent application number | Description | Published |
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20100086397 | Surface Treatments for Turbine Components to Reduce Particle Accumulation During Use Thereof - A turbine engine component includes at least one treated surface wherein the treated surface has a surface roughness (Ra) of less than 12 microinches; and a hard coating disposed on the superfinished surface, wherein the hard coating is a nitride and/or a carbide material at a thickness of less than 50 microns formed using electron beam physical vapor deposition, cathodic arc evaporation, or magnetron sputtering. disclosed are methods for substantially preventing micropitting on a surface of a turbine engine component. | 04-08-2010 |
20100247321 | ANTI-FOULING COATINGS AND ARTICLES COATED THEREWITH - An article including a metallic substrate is presented. The article further includes a sacrificial layer disposed on a surface of the substrate and an anti-fouling layer disposed on the sacrificial layer. The anti-fouling layer includes a metal-polymer composite. An article including an anti-fouling layer having a nitride is also presented. | 09-30-2010 |
20100294461 | ENCLOSURE FOR HEAT TRANSFER DEVICES, METHODS OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME - Disclosed herein is a heat transfer device that includes a shell; the shell being an enclosure that prevents matter from within the shell from being exchanged with matter outside the shell during the operation of the heat transfer device; the shell having an outer surface and an inner surface; and a porous layer disposed on the inner surface of the shell; the porous particle layer having a thickness effective to enclose a vapor space between opposing faces; the vapor space being effective to provide a passage for the transport of a fluid; the heat transfer device having a thermal conductivity of greater than or equal to about 10 watts per meter-Kelvin and a coefficient of thermal expansion that is substantially similar to that of a semiconductor. | 11-25-2010 |
20100294467 | HIGH PERFORMANCE HEAT TRANSFER DEVICE, METHODS OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME - Disclosed herein is an heat transfer device that includes a shell; the shell being an enclosure that prevents matter from within the shell from being exchanged with matter outside the shell; the shell having an outer surface and an inner surface; and a particle layer disposed on the inner surface of the shell; the particle layer having a thickness effective to enclose a region for transferring a fluid between opposing faces; the particle layer including a first layer and a second layer; the second layer being disposed upon the first layer; the first layer having average particle sizes of about 10 to about 10,000,000 nanometers; the second layer having average particle sizes of about 10 to about 10,000 nanometers. | 11-25-2010 |
20100326922 | OIL WATER SEPARATION APPARATUS - In one aspect, the present invention provides a subsea separation vessel for the separation of a mixture comprising oil and water comprising (a) at least one inlet for introducing a oil-water mixture; (b) a flow path for conducting the oil-water mixture; (c) at least one oil-water separation structure; and (d) at least one fluid outlet. The oil-water separation structure includes a multifunctional surface. The oil-water separation structure is located within the flow path and wherein the multifunctional surface is superhydrophobic with respect to water, and either oleophilic or superoleophilic with respect to oil. A method for separating oil from an oil-water mixture is also provided. | 12-30-2010 |
20130258600 | THERMAL INTERFACE ELEMENT AND ARTICLE INCLUDING THE SAME - An article and method of forming the article is disclosed. The article includes a heat source, a substrate, and a thermal interface element having a plurality of freestanding nanosprings disposed in thermal communication with the substrate and the heat source. The nanosprings of the article include at least one inorganic material and also at least 50% of the nanosprings have a thermal conductivity of at least 1 watt/mK per nano spring. | 10-03-2013 |
Ameet Kulkarni, Fairport, NY US
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20100105264 | GASKET RELEASE AGENT - Various gasket release agents and methods of providing and using the same are provided with a gasket body having a release agent coating on one or more surfaces that contact mating surfaces of a joining assembly. The coating may be provided as a mixture of constituents including hexagonal boron nitride. Other constituents may include a release agent and a binding material that enhances the adhesion of the release agent to the gasket body surfaces. A binding material may include, for example, organic or inorganic materials. Surfactants, in some embodiments, may be added to a gasket release agent dispersion in addition to binder materials and fillers. | 04-29-2010 |
20100331468 | BORON NITRIDE FILLED PTFE - A composition is provided that, in one aspect, may be used in the production of sealing materials, such as gaskets. The composition includes a polytetraflouroethylene matrix and a Boron Nitride filler. In one aspect, the Boron Nitride filler may be provided as a hexagonal, close-packed, Boron Nitride filler that is homogeneously dispersed within the polytetraflouroethylene matrix. In at least one embodiment, the composition is formed by combining quantities of polytetraflouroethylene, Boron Nitride filler, hydrocarbon liquid, and solvent. The liquid and solvent may be removed through various processes prior to sintering the composition to form a full-density, Boron Nitride filled, polytetraflouroethylene matrix that exhibits improved sealability, greater resistance to permeation, and less color contamination. | 12-30-2010 |
Amit Kulkarni, Clifton Park, NY US
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20090016262 | Technique for Low-Overhead Network State Dissemination for Management of Mobile Ad-Hoc Networks - Aspects of the disclosure can provide an ad-hoc network having a clusterhead node and a plurality of nodes associated with the clusterhead, at least one of the plurality of nodes is a remote node and at least one is an intermediate node, the remote node can indirectly communicate with the clusterhead through the intermediate node. The remote node can also transmit network state information at a higher rate, but in lesser amounts, than the intermediate node. | 01-15-2009 |
20090280063 | NOVEL PEI-PEG GRAFT COPOLYMER COATING OF IRON OXIDE NANOPARTICLES FOR INFLAMMATION IMAGING - A nanostructure includes a nanoparticle core ( | 11-12-2009 |
20140126357 | ECN-ENABLED MULTICAST PROTOCOL FOR WIRELESS COMMUNICATION SYSTEMS UNDER BLOCKAGE - A system and method are provided for implementing performance improvements in a multicast protocol for networks that support incipient congestion indications via packet marking in instances of packet loss in the network during time-correlated blockages by providing indications in the physical (PHY) layer. A receiver rate calculation is adjusted so that a loss due to blockage is ignored completely and only packets marked using an Explicit Congestion Notification (ECN) packet marking protocol are treated as losses. Receiver rates are modified based on ECN principles to ignore losses. A NORM receiver rate equation may remain substantially unchanged while a sender is enabled to keep sending at a higher data rate, even in instances of blockage in support of higher system throughputs without defining a completely new receiver rate equation. Time-correlated blockages are not treated as losses. | 05-08-2014 |
Amit Bhavanishankar Kulkarni, Clifton Park, NY US
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20090170483 | SYSTEM AND METHOD FOR TRANSMITTING INFORMATION USING A MOBILE PHONE - A technique is provided for providing information to a customer within a store. A mobile phone is provided that is adapted to communicate with Near Field Communication (NFC) devices and wireless Internet Protocol (IP) based network, or Internet system, as well as operate as a cellular phone. The mobile phone is configured to bridge information between the various protocols used to enable the mobile phone to communicate with an NFC device, a wireless Internet system, and a cellular phone system. For example, information obtained by the mobile phone from a NFC device may be transferred to the portion of the mobile phone that is used to connect the mobile phone to a wireless Internet system to enable the mobile phone to provide the proper authentication to access the wireless Internet system. In addition, the mobile phone may be adapted to communicate using a Bluetooth communication system. Similarly, information from the Bluetooth portion of the mobile phone is shared with the other portions of the phone that communicate using other data protocols. | 07-02-2009 |
Amit Mohan Kulkarni, Clifton Park, NY US
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20090087383 | NANOPARTICLE-BASED IMAGING AGENTS FOR X-RAY/COMPUTED TOMOGRAPHY AND METHODS FOR MAKING SAME - The present invention is generally directed to core/shell nanoparticles, wherein such core/shell nanoparticles comprise a nanoparticle core and a nanoshell disposed about the nanoparticle core such that, in the aggregate, they form a core/shell nanoparticle that is operable for use as an imaging agent in X-ray/computed tomography (CT). Typically, such core/shell nanoparticle-based X-ray CT imaging agents further comprise a targeting species for targeting the imaging agent to diseased sites. Included herein are methods for forming such agents, comprising forming an ensemble of core/shell nanoparticles, wherein the mean diameter of the ensemble of core/shell nanoparticles is selected so as to render the nanoparticles in the ensemble substantially clearable by a mammalian kidney. | 04-02-2009 |
20090246143 | NON-RADIOACTIVE TRACEABLE METAL ISOTOPE-ENRICHED NANOPARTICLES AND METHOD OF THEIR USE FOR DETERMINING BIODISTRIBUTION - Composition of non-radioactive traceable metal isotope-enriched nanoparticles, and methods of their use for determining in-vivo biodistribution are provided. The methods comprise the steps of: (a) introducing the nanoparticles into the biological material, wherein the nanoparticles comprise at least one inorganic core, and the inorganic core comprises at least two metal isotopes in a predetermined ratio; wherein at least one metal isotope is enriched non-radioactive traceable metal isotope and (b) determining the distribution of the nanoparticles in the biological material based on the predetermined ratio of the metal isotopes. | 10-01-2009 |
20100166664 | NANOPARTICLE CONTRAST AGENTS FOR DIAGNOSTIC IMAGING - Compositions of nanoparticles functionalized with at least one zwitterionic moiety, methods for making a plurality of nanoparticles, and methods of their use as diagnostic agents are provided. The nanoparticles have characteristics that result in minimal retention of the particles in the body compared to other nanoparticles. The nanoparticle comprises a core, having a core surface essentially free of silica, and a shell attached to the core surface. The shell comprises at least one silane-functionalized zwitterionic moiety. | 07-01-2010 |
20100166665 | NANOPARTICLE CONTRAST AGENTS FOR DIAGNOSTIC IMAGING - Compositions of nanoparticles functionalized with at least one zwitterionic moiety, methods for making a plurality of nanoparticles, and methods of their use as diagnostic agents are provided. The nanoparticles have characteristics that result in minimal retention of the particles in the body compared to other nanoparticles. The nanoparticle comprises a core, having a core surface essentially free of silica, and a shell attached to the core surface. The shell comprises at least one silane-functionalized zwitterionic moiety. | 07-01-2010 |
20100166666 | NANOPARTICLE CONTRAST AGENTS FOR DIAGNOSTIC IMAGING - Compositions of nanoparticles functionalized with at least one zwitterionic moiety, methods for making a plurality of nanoparticles, and methods of their use as diagnostic agents are provided. The nanoparticles have characteristics that result in minimal retention of the particles in the body compared to other nanoparticles. The nanoparticle comprises a core, having a core surface essentially free of silica, and a shell attached to the core surface. The shell comprises at least one silane-functionalized zwitterionic moiety. | 07-01-2010 |
20100278734 | NANOPARTICLE CONTRAST AGENTS FOR DIAGNOSTIC IMAGING - Compositions of nanoparticles functionalized with at least one net positively charged group and at least one net negatively charged group, methods for making a plurality of nanoparticles, and methods of their use as diagnostic agents are provided. The nanoparticles have characteristics that result in minimal retention of the particles in the body compared to other nanoparticles. The nanoparticle comprises a core and a shell. The shell comprises a plurality of silane moieties; at least one silane moiety of the plurality is functionalized with a net positively charged group and at least one silane moiety of the plurality is functionalized with a net negatively charged group. | 11-04-2010 |
20100278748 | NANOPARTICLE CONTRAST AGENTS FOR DIAGNOSTIC IMAGING - Compositions of nanoparticles functionalized with at least one net positively charged group and at least one net negatively charged group, methods for making a plurality of nanoparticles, and methods of their use as diagnostic agents are provided. The nanoparticles have characteristics that result in minimal retention of the particles in the body compared to other nanoparticles. The nanoparticle comprises a core and a shell. The shell comprises a plurality of silane moieties; at least one silane moiety of the plurality is functionalized with a net positively charged group and at least one silane moiety of the plurality is functionalized with a net negatively charged group. | 11-04-2010 |
20100278749 | NANOPARTICLE CONTRAST AGENTS FOR DIAGNOSTIC IMAGING - Compositions of nanoparticles functionalized with at least one net positively charged group and at least one net negatively charged group, methods for making a plurality of nanoparticles, and methods of their use as diagnostic agents are provided. The nanoparticles have characteristics that result in minimal retention of the particles in the body compared to other nanoparticles. The nanoparticle comprises a core and a shell. The shell comprises a plurality of silane moieties; at least one silane moiety of the plurality is functionalized with a net positively charged group and at least one silane moiety of the plurality is functionalized with a net negatively charged group. | 11-04-2010 |
20140147387 | NANOPARTICLE CONTRAST AGENTS FOR DIAGNOSTIC IMAGING - Compositions of nanoparticles functionalized with at least one zwitterionic moiety, methods for making a plurality of nanoparticles, and methods of their use as diagnostic agents are provided. The nanoparticles have characteristics that result in minimal retention of the particles in the body compared to other nanoparticles. The nanoparticle comprising a nanoparticulate transition metal oxide covalently functionalized with a silane-functionalized non-targeting zwitterionic moiety. | 05-29-2014 |
Bharati S. Kulkarni, Cortlandt Manor, NY US
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20140008697 | Siloxane Compositions Including Titanium Dioxide Nanoparticles Suitable For Forming Encapsulants - A composition includes an organopolysiloxane component (A) comprising at least one of a disiloxane, a trisiloxane, and a tetrasiloxane, and has an average of at least two alkenyl groups per molecule. The composition further includes an organohydrogensiloxane component (B) having an average of at least two silicon-bonded hydrogen atoms per molecule. Components (A) and (B) each independently have at least one of an alkyl group and an aryl group and each independently have a number average molecular weight less than or equal to 1500 (g/mole). The composition yet further includes a catalytic amount of a hydrosilylation catalyst component (C), and titanium dioxide (TiO | 01-09-2014 |
Deepak Kulkarni, Wappinger Falls, NY US
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20130207263 | SEMICONDUCTOR CHIPS INCLUDING PASSIVATION LAYER TRENCH STRUCTURE - An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer. | 08-15-2013 |
Deepak Kulkarni, Wappingers Falls, NY US
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20080233724 | RECYCLING OF ELECTROCHEMICAL-MECHANICAL PLANARIZATION (ECMP) SLURRIES/ELECTROLYTES - A method, process and system for the recycling of electrochemical-mechanical planarization slurries/electrolytes as they are used in the back end of line of the semiconductor wafer manufacturing process is disclosed. The method, process and system includes with the removal of metal ions from slurries using ion exchange media and/or electrochemical deposition. | 09-25-2008 |
20090142994 | ELECTRICAL CONTACT STRUCTURES AND METHODS FOR USE - Methods and structures. A planarization method includes: providing a contact structure, where the contact structure includes an axle configured to rotate about an axis of rotation, a plurality of cantilever arms, each arm having a first end connected to the axle, where each arm extends radially outward from the axle; and a plurality of electrically conductive spheres, where at least one sphere is disposed on a second end of each arm; placing a substrate in contact with the spheres, applying an electric voltage to the axle, where the voltage transfers to the substrate, where responsive to the transfer an electrochemical reaction occurs on the substrate; rotating the axle, wherein the spheres revolve about the axis, wherein at least one sphere remains in electrical contact with the substrate; and electrochemical-mechanically planarizing the substrate. Also included is a contact structure, an electrical contact, and an electrical contact method. | 06-04-2009 |
20100187689 | SEMICONDUCTOR CHIPS INCLUDING PASSIVATION LAYER TRENCH STRUCTURE - An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer. | 07-29-2010 |
20110119908 | ELECTRICAL CONTACT METHOD - An electrical contact method. An axle having an axis of rotation is provided. Cantilever arms are provided. Each cantilever arm has a first end and a second opposing end. The first end is connected to the axle. Each cantilever arm extends radially outward from the axle about perpendicular to the axis of rotation. At least two electrically conductive contacts is provided. At least one electrically conductive contact of the at least two electrically conductive contacts is disposed on the second end of each cantilever arm. A sample is supported on a support member. The electrically conductive contacts are pressed against a first surface of the sample. After the electrically conductive contacts are pressed, the electrically conductive contacts are revolved about the axis of rotation, wherein the at least one electrically conductive contact remains in electrical contact with the first surface. | 05-26-2011 |
Neha Kulkarni, New York, NY US
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20140081861 | SYSTEM AND METHOD FOR CREATING SPEND VARIFIED REVIEWS - The systems, methods, and computer program products (collectively “systems”) described herein are generally configured to monitor actions in digital channels. More specifically, the systems are capable of creating spend verified reviews based on a transaction and/or an action in a channel. The systems are capable of syncing transaction accounts with various digital channels. Moreover, the systems are capable of initiating or completing transaction based on user information. The systems may also be capable of providing rewards based on activities or accomplishments in the digital channels. Moreover, the systems may be capable of verifying activities based on transaction information. | 03-20-2014 |
Parag Parkash Kulkarni, Niskayhuna, NY US
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20110030383 | HYBRID MULTICHANNEL POROUS STRUCTURE FOR HYDROGEN SEPARATION - A hybrid multichannel porous structure for processing between two fluid streams of different compositions includes a housing and one or more structures disposed within the cavity of the housing in a shell and tube configuration. Each structure includes a body made of a porous, inorganic material and a plurality of channels for processing an optional sweep stream. Each channel is coated with a membrane layer. A feed stream introduced into the housing is in direct contact with the structures such that a gas selectively permeates through the body and into the channels. The gas combines with the sweep stream to form a permeate that exits from each channel. The remaining feed stream forms a retentate that exits from the housing. The feed stream may consist of syngas containing hydrogen gas and the sweep stream may contain nitrogen gas. A power plant that incorporates the hybrid structure is disclosed. | 02-10-2011 |
20110099969 | HYBRID MULTICHANNEL POROUS STRUCTURE FOR HYDROGEN SEPARATION - A hybrid multichannel porous structure for processing between two fluid streams of different compositions includes a housing and one or more structures disposed within the cavity of the housing in a shell and tube configuration. Each structure includes a body made of a porous, inorganic material and a plurality of channels for processing an optional sweep stream. Each channel is coated with a membrane layer. A feed stream introduced into the housing is in direct contact with the structures such that a gas selectively permeates through the body and into the channels. The gas combines with the sweep stream to form a permeate that exits from each channel. The remaining feed stream forms a retentate that exits from the housing. The feed stream may consist of syngas containing hydrogen gas and the sweep stream may contain nitrogen gas. A power plant that incorporates the hybrid structure is disclosed. | 05-05-2011 |
Parag Prakash Kulkarni, Niskayuna, NY US
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20110030384 | Syngas cleanup section with carbon capture and hydrogen-selective membrane - A syngas cleanup section includes a water-gas shift reactor, a first operation unit and a second operation unit. The first operation unit includes a high permeance membrane with H | 02-10-2011 |
20120023892 | SYSTEMS AND METHODS FOR CO2 CAPTURE - The present disclosure relates to the separation of CO | 02-02-2012 |
20120023947 | SYSTEMS AND METHODS FOR CO2 CAPTURE - The present disclosure relates to the separation of CO | 02-02-2012 |
20120274078 | HYBRID CONCENTRATED SOLAR COMBINED CYCLE POWER PLANT AND SOLAR REFORMER FOR USE THEREIN - A hybrid concentrated solar combined cycle (CSCC) power plant based on solar reforming technology, method of generating electricity using the system and a solar reformer for use in the system are provided. The system enables integration of a concentrated solar power plant (CSP) and a combined cycle gas turbine (CCGT) power plant, resulting in a hybrid system that corrects known issues related to large-scale concentrated solar power generation. The solar reformer provides for the storage of solar energy in a reformate fuel during the reforming reaction and subsequent release through a gas turbine combustion reaction. Fuels directed into the gas turbine power plant can be alternated between hydrocarbon fluid and the reformate fuel dependent upon available solar thermal energy. | 11-01-2012 |
20130000352 | AIR SEPARATION UNIT AND SYSTEMS INCORPORATING THE SAME - A system comprising an air separation unit (ASU) is provided. The ASU is configured to produce liquid nitrogen and pressurize to higher pressure using a pump. ASU may be further configured to produce liquid oxygen that can be directly pressurized to be used in required applications. System may further include oxy-fuel combustion system, integrated gas turbines and integrated enhanced oil and/or gas recovery units. Methods of operating the system included. | 01-03-2013 |
20130025294 | SYSTEM AND METHOD FOR CARBON DIOXIDE REMOVAL - A carbon dioxide (CO | 01-31-2013 |
20130145771 | SYSTEM AND METHOD USING LOW EMISSIONS GAS TURBINE CYCLE WITH PARTIAL AIR SEPARATION - A system and method of reducing gas turbine nitric oxide emissions includes a first combustion stage configured to burn air vitiated with diluents to generate first combustion stage products. A second combustion stage is configured to burn the first combustion stage products in combination with enriched oxygen to generate second combustion stage products having a lower level of nitric oxide emissions than that achievable through combustion with vitiated air alone or through combustion staging alone. | 06-13-2013 |
20140020388 | SYSTEM FOR IMPROVED CARBON DIOXIDE CAPTURE AND METHOD THEREOF - In one embodiment, a power plant is provided. The power plant includes a power generation system configured to produce an exhaust; a CO | 01-23-2014 |
20150143811 | SYSTEM AND METHOD FOR HEATING A CATALYST IN AN EXHAUST TREATMENT SYSTEM OF A TURBINE ENGINE - A system includes a catalyst system having at least one catalyst to treat an exhaust gas from a gas turbine system, and a thermal storage system having at least one storage tank to store thermal energy in a medium, wherein the system is configured to transfer heat from the medium to the at least one catalyst. | 05-28-2015 |
Parag Prakash Kulkarni, Clifton Park, NY US
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20090057202 | METHODS AND SYSTEMS FOR REMOVING VANADIUM FROM LOW-GRADE FUELS - A method for treating fuel containing vanadium including extracting vanadium from the fuel with an adsorption material and fractionating the fuel into a light oil fraction and a heavy fuel fraction. The light fuel fraction has a reduced amount of vanadium. Systems for fuel preparation are also provided. | 03-05-2009 |
20090158663 | METHOD OF BIOMASS GASIFICATION - A method for the gasification of biomass, wherein the biomass feedstock is combined with a light hydrocarbon composition to form a slurry; followed by feeding the slurry to a gasifier to produce a fuel gas. In another embodiment, a method for the gasification of biomass is described. The method includes the steps of combining a biomass feedstock with water to form a slurry; feeding the slurry to a gasifier to produce a fuel gas; and injecting a light hydrocarbon into the gasifier, to generate gasification temperatures greater than about 900° C., by partial or complete combustion of the light hydrocarbon. In some other embodiments, the biomass gasifier product gas is coupled to a reformer, wherein a light hydrocarbon is injected to generate high temperatures. | 06-25-2009 |
20110072779 | SYSTEM AND METHOD USING LOW EMISSIONS GAS TURBINE CYCLE WITH PARTIAL AIR SEPARATION - A system and method of reducing gas turbine nitric oxide emissions includes a first combustion stage configured to burn air vitiated with diluents to generate first combustion stage products. A second combustion stage is configured to burn the first combustion stage products in combination with enriched oxygen to generate second combustion stage products having a lower level of nitric oxide emissions than that achievable through combustion with vitiated air alone or through combustion staging alone. | 03-31-2011 |
Parag Prakash Kulkarni, Schenectady, NY US
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20130145773 | METHOD AND SYSTEM FOR SEPARATING CO2 FROM N2 AND O2 IN A TURBINE ENGINE SYSTEM - A method of separating carbon dioxide (CO | 06-13-2013 |
Parag Prakesh Kulkarni, Schenectady, NY US
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20160131029 | METHOD AND SYSTEM FOR SEPARATING CO2 FROM N2 AND O2 IN A TURBINE ENGINE SYSTEM - A method of separating carbon dioxide (CO | 05-12-2016 |
Parashuram Kulkarni, New York, NY US
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20100057718 | System And Method For Generating An Approximation Of A Search Engine Ranking Algorithm - A system and method for determining a ranking function for a search engine. A training data processor receives training data, the training data including at least a first page, a first label, a second page and a second label. A feature extraction processor receives the first page, identifies first features in the first page and calculates first values relating to the first features. The feature extraction processor receives the second page and identifies second features and calculates second values relating to the second features. A machine learning processor receives the first features, the first values, the first label, the second features, the second values, and the second label. The machine learning processor generates a ranking function based on first features, the first values, the first label, the second features, the second values, and the second label. | 03-04-2010 |
20100057719 | System And Method For Generating Training Data For Function Approximation Of An Unknown Process Such As A Search Engine Ranking Algorithm - A system and method for generating training data for a machine learning system. A training data generator server sends at least one keyword to a search engine. The training data generator server receives at least a first and a second page from the search engine in response to the keyword, the first page having a first rank, the second page having a second rank, the first and second rank being based on the keyword. The training data generator server assigns a first label to the first page based on the first rank; and assigns a second label to the second page based on the second rank. The first web page, second page, first label and second label are forwarded to a machine learning server. | 03-04-2010 |
Pranita Kulkarni, Sligerlands, NY US
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20120280290 | LOCAL INTERCONNECT STRUCTURE SELF-ALIGNED TO GATE STRUCTURE - A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other. | 11-08-2012 |
Pranita Kulkarni, Singerlands, NY US
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20130095629 | Finfet Parasitic Capacitance Reduction Using Air Gap - Methods are disclosed to fabricate a transistor, for example a FinFET, by forming over a substrate at least one electrically conductive channel between a source region and a drain region; forming a gate structure to be disposed over a portion of the channel, the gate structure having a width and a length and a height defining two opposing sidewalls of the gate structure and being formed such that the channel said passes through the sidewalls; forming spacers on the sidewalls; forming a layer of epitaxial silicon over the channel; removing the spacers; and forming a dielectric layer to be disposed over the gate structure and portions of the channel that are external to the gate structure such that a capacitance-reducing air gap underlies the dielectric layer and is disposed adjacent to the sidewalls of said gate structure in a region formerly occupied by the spacers. | 04-18-2013 |
20130249004 | Same-Chip Multicharacteristic Semiconductor Structures - In one exemplary embodiment, a semiconductor structure includes: a semiconductor-on-insulator substrate with a top semiconductor layer overlying an insulation layer and the insulation layer overlies a bottom substrate layer; at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion has a first thickness, a first width and a first depth; and at least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion has a second thickness, a second width and a second depth, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth. | 09-26-2013 |
Pranita Kulkarni, Slingerlands, NY US
Patent application number | Description | Published |
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20110254090 | RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER - A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion. | 10-20-2011 |
20110284967 | Stressed Fin-FET Devices with Low Contact Resistance - A method for fabricating an FET device is disclosed. The method includes Fin-FET devices with fins that are composed of a first material, and then merged together by epitaxial deposition of a second material. The fins are vertically recesses using a selective etch. A continuous silicide layer is formed over the increased surface areas of the first material and the second material, leading to smaller resistance. A stress liner overlaying the FET device is afterwards deposited. An FET device is also disclosed, which FET device includes a plurality of Fin-FET devices, the fins of which are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device. | 11-24-2011 |
20110298025 | FINFET-COMPATIBLE METAL-INSULATOR-METAL CAPACITOR - At least one semiconductor fin for a capacitor is formed concurrently with other semiconductor fins for field effect transistors. A lower conductive layer is deposited and lithographically patterned to form a lower conductive plate located on the at least one semiconductor fin. A dielectric layer and at least one upper conductive layer are formed and lithographically patterned to form a node dielectric and an upper conductive plate over the lower conductive plate as well as a gate dielectric and a gate conductor over the other semiconductor fins. The lower conductive plate, the node dielectric, and the upper conductive plate collectively form a capacitor. The finFETs may be dual gate finFETs or trigate finFETs. A buried insulator layer may be optionally recessed to increase the capacitance. Alternately, the lower conductive plate may be formed on a planar surface of the buried insulator layer. | 12-08-2011 |
20110303915 | Compressively Stressed FET Device Structures - Methods for fabricating FET device structures are disclosed. The methods include receiving a fin of a Si based material, and converting a region of the fin into an oxide element. The oxide element exerts pressure onto the fin where a Fin-FET device is fabricated. The exerted pressure induces compressive stress in the device channel of the Fin-FET device. The methods also include receiving a rectangular member of a Si based material and converting a region of the member into an oxide element. The methods further include patterning the member that N fins are formed in parallel, while being abutted by the oxide element, which exerts pressure onto the N fins. Fin-FET devices are fabricated in the compressed fins, which results in compressively stressed device channels. FET devices structures are also disclosed. An FET devices structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row each having fins. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins. | 12-15-2011 |
20110309446 | STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER - A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure. | 12-22-2011 |
20110316083 | FET with Self-Aligned Back Gate - A back-gated field effect transistor (FET) includes a substrate, the substrate comprising top semiconductor layer on top of a buried dielectric layer on top of a bottom semiconductor layer; a front gate located on the top semiconductor layer; a channel region located in the top semiconductor layer under the front gate; a source region located in the top semiconductor layer on a side of the channel region, and a drain region located in the top semiconductor layer on the side of the channel region opposite the source regions; and a back gate located in the bottom semiconductor layer, the back gate configured such that the back gate abuts the buried dielectric layer underneath the channel region, and is separated from the buried dielectric layer by a separation distance underneath the source region and the drain region. | 12-29-2011 |
20120025282 | Raised Source/Drain Field Effect Transistor - In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length. | 02-02-2012 |
20120038007 | Field Effect Transistor Device With Self-Aligned Junction - A method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, the source extension portion extending from the source region into the first portion of the substrate, forming an ion doped drain extension portion in the substrate, the drain extension portion extending from the drain region into the first portion of the substrate, removing a portion of the dummy gate stack to expose an interfacial layer of the dummy gate stack, implanting ions in the source extension portion and the drain extension portion to form a channel region in the first portion of the substrate, removing the interfacial layer, and forming a gate stack on the channel region of the substrate. | 02-16-2012 |
20120038008 | Field Effect Transistor Device with Self-Aligned Junction and Spacer - In one aspect of the present invention, a method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, forming an ion doped drain extension portion in the substrate, forming a first spacer portion adjacent to the dummy gate stack, removing the dummy gate stack to expose a channel region of the substrate, a portion of the ion doped source extension portion, and a portion of the ion doped drain extension portion, forming a second spacer portion on the exposed portion of the ion doped source extension portion and on the exposed portion of the ion doped drain extension portion, and forming a gate stack on the exposed channel region of the substrate. | 02-16-2012 |
20120043610 | Controlled Fin-Merging for Fin Type FET Devices - A method for fabricating FET devices is disclosed. The method includes forming continuous fins of a semiconductor material and fabricating gate structures overlaying the continuous fins. After the fabrication of the gate structures, the method uses epitaxial deposition to merge the continuous fins to one another. Next, the continuous fins are cut into segments. The fabricated FET devices are characterized as being non-planar devices. A placement of non-planar FET devices is also disclosed, which includes non- planar devices that have electrodes, and the electrodes contain fins and an epitaxial layer which merges the fins together. The non-planar devices are so placed that their gate structures are in a parallel configuration separated from one another by a first distance, and the fins of differing non-planar devices line up in essentially straight lines. The electrodes of differing FET devices are separated from one another by a cut defined by opposing facets of the electrodes, with the opposing facets also defining the width of the cut. The width of the cut is smaller than one fifth of the first distance which separates the gate structures. | 02-23-2012 |
20120043623 | METHOD AND STRUCTURE FOR FORMING HIGH-K/METAL GATE EXTREMELY THIN SEMICONDUCTOR ON INSULATOR DEVICE - A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers. | 02-23-2012 |
20120068267 | STRAINED DEVICES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe. | 03-22-2012 |
20120074494 | STRAINED THIN BODY SEMICONDUCTOR-ON-INSULATOR SUBSTRATE AND DEVICE - A method of forming a strained, semiconductor-on-insulator substrate includes forming a second semiconductor layer on a first semiconductor substrate. The second semiconductor is lattice matched to the first semiconductor substrate such that the second semiconductor layer is subjected to a first directional stress. An active device semiconductor layer is formed over the second semiconductor layer such that the active device semiconductor layer is initially in a relaxed state. One or more trench isolation structures are formed through the active device layer and through the second semiconductor layer so as to relax the second semiconductor layer below the active device layer and impart a second directional stress on the active device layer opposite the first directional stress. | 03-29-2012 |
20120080802 | THROUGH SILICON VIA IN N+ EPITAXY WAFERS WITH REDUCED PARASITIC CAPACITANCE - A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance. | 04-05-2012 |
20120112207 | METHOD TO REDUCE GROUND-PLANE POISONING OF EXTREMELY-THIN SOI (ETSOI) LAYER WITH THIN BURIED OXIDE - The present disclosure, which is directed to ultra-thin-body-and-BOX and Double BOX fully depleted SOI devices having an epitaxial diffusion-retarding semiconductor layer that slows dopant diffusion into the SOI channel, and a method of making these devices. Dopant concentrations in the SOI channels of the devices of the present disclosure having an epitaxial diffusion-retarding semiconductor layer between the substrate and SOI channel are approximately 50 times less than the dopant concentrations measured in SOI channels of devices without the epitaxial diffusion-retarding semiconductor layer. | 05-10-2012 |
20120119266 | Stressor in Planar Field Effect Transistor Device - A field effect transistor device includes a gate stack portion disposed on a substrate, and a channel region in the substrate having a depth partially defined by the gate stack portion and a silicon region of the substrate, the silicon region having a sloped profile such that a distal regions of the channel region have greater depth than a medial region of the channel region. | 05-17-2012 |
20120153397 | Stressed Fin-FET Devices with Low Contact Resistance - An FET device includes a plurality of Fin-FET devices. The fins of the Fin-FET devices are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device. | 06-21-2012 |
20120175749 | Structure and Method to Fabricate Resistor on FinFET Processes - A structure comprises first and at least second fin structures are formed. Each of the first and at least second fin structures has a vertically oriented semiconductor body. The vertically oriented semiconductor body is comprised of vertical surfaces. A doped region in each of the first and at least second fin structures is comprised of a concentration of dopant ions present in the semiconductor body to form a first resistor and at least a second resistor, and a pair of merged fins formed on outer portions of the doped regions of the first and at least second fin structures. The pair of merged fins is electrically connected so that the first and at least second resistors are electrically connected in parallel with each other. | 07-12-2012 |
20120193713 | FinFET device having reduce capacitance, access resistance, and contact resistance - A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each is second spacer adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers. | 08-02-2012 |
20120205716 | Epitaxially Grown Extension Regions for Scaled CMOS Devices - Epitaxially grown extension regions are disclosed for scaled CMOS devices. Semiconductor devices are provided that comprise a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises at least a channel layer formed below the gate stack. One or more etched extension regions containing an epitaxially grown dopant are provided in the channel layer. | 08-16-2012 |
20120216158 | STRAINED DEVICES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe. | 08-23-2012 |
20120220114 | TENSILE STRESS ENHANCEMENT OF NITRIDE FILM FOR STRESSED CHANNEL FIELD EFFECT TRANSISTOR FABRICATION - A method for inducing a tensile stress in a channel of a field effect transistor (FET) includes forming a nitride film over the FET; forming a contact hole to the FET through the nitride film; and performing ultraviolet (UV) curing of the nitride film after forming the contact hole to the FET through the nitride film, wherein the UV cured nitride film induces the tensile stress in the channel of the FET. | 08-30-2012 |
20120235238 | FULLY-DEPLETED SON - A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a semiconductor substrate, an insulating layer, a first semiconductor layer, a dielectric layer, a second semiconductor layer, a source and drain junction, a gate, and a spacer. The method includes the steps of forming a semiconductor substrate, forming a shallow trench isolation layer, growing a first epitaxial layer, growing a second epitaxial layer, forming a gate, forming a spacer, performing a reactive ion etching, removing a portion of the first epitaxial layer, filling the void with a dielectric, etching back a portion of the dielectric, growing a silicon layer, implanting a source and drain junction, and forming an extension. | 09-20-2012 |
20120235239 | HYBRID MOSFET STRUCTURE HAVING DRAIN SIDE SCHOTTKY JUNCTION - A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined. | 09-20-2012 |
20120256238 | Junction Field Effect Transistor With An Epitaxially Grown Gate Structure - A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs). | 10-11-2012 |
20120261757 | STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER - A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure. | 10-18-2012 |
20120261792 | SOI DEVICE WITH DTI AND STI - An SOI structure including a semiconductor on insulator (SOI) substrate including a top silicon layer, an intermediate buried oxide (BOX) layer and a bottom substrate; at least two wells in the bottom substrate; a deep trench isolation (DTI) separating the two wells, the DTI having a top portion extending through the BOX layer and top silicon layer and a bottom portion within the bottom substrate wherein the bottom portion has a width that is larger than a width of the top portion; and at least two semiconductor devices in the silicon layer located over one of the wells, the at least two semiconductor devices being separated by a shallow trench isolation within the top silicon layer. | 10-18-2012 |
20120267722 | Compressively Stressed FET Device Structures - An FET device structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins. | 10-25-2012 |
20120276695 | Strained thin body CMOS with Si:C and SiGe stressor - A method is disclosed which is characterized as being process integration of raised source/drain and strained body for ultra thin planar and FinFET CMOS devices. NFET and PFET devices have their source/drain raised by selective epitaxy with in-situ p-type doped SiGe for the PFET device, and in-situ n-type doped Si:C for the NFET device. Such raised source/drains offer low parasitic resistance and they impart a strain onto the device bodies of the correct sign for respective carrier, electron or hole, mobility enhancement. | 11-01-2012 |
20120286329 | SOI FET with embedded stressor block - A method and a structure are disclosed relating to strained body UTSOI FET devices. The method includes forming voids in the source/drain regions that penetrate down into the substrate below the insulating layer. The voids are epitaxially filled with a semiconductor material of a differing lattice constant than the one of the SOI layer, thus becoming a stressor block, and imparts a strain onto the FET device body. | 11-15-2012 |
20120286360 | Field Effect Transistor Device with Self-Aligned Junction and Spacer - A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, a first spacer portion disposed on the source region, the drain region and a first portion of the source extension portion, and a first portion of the drain extension portion, a second spacer portion disposed on a second portion of the source extension portion, and a second portion of the drain extension portion, a gate stack portion disposed on the channel region. | 11-15-2012 |
20120286364 | Integrated Circuit Diode - A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process. | 11-15-2012 |
20120286371 | Field Effect Transistor Device With Self-Aligned Junction - A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, wherein the channel region includes a source transition portion including n-type and p-type ions and a drain transition portion including n-type and p-type ions, and a gate stack portion disposed on the channel region. | 11-15-2012 |
20120286375 | PRESERVING STRESS BENEFITS OF UV CURING IN REPLACEMENT GATE TRANSISTOR FABRICATION - A method of forming a semiconductor structure includes forming a stress inducing layer over one or more partially completed field effect transistor (FET) devices disposed over a substrate, the one or more partially completed FET devices including sacrificial dummy gate structures; planarizing the stress inducing layer and removing the sacrificial dummy gate structures; and following the planarizing the stress inducing layer and removing the sacrificial dummy gate structures, performing an ultraviolet (UV) cure of the stress inducing layer so as to enhance a value of an initial applied stress by the stress inducing layer on channel regions of the one or more partially completed FET devices. | 11-15-2012 |
20120292705 | SEMICONDUCTOR STRUCTURE HAVING UNDERLAPPED DEVICES - A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the. SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively. | 11-22-2012 |
20120299075 | SOI Trench Dram Structure With Backside Strap - In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion. | 11-29-2012 |
20120299103 | RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER - A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion. | 11-29-2012 |
20120302019 | NON-RELAXED EMBEDDED STRESSORS WITH SOLID SOURCE EXTENSION REGIONS IN CMOS DEVICES - A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure. | 11-29-2012 |
20120302020 | SOI Trench Dram Structure With Backside Strap - In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion. | 11-29-2012 |
20120313143 | HIGHLY SCALED ETSOI FLOATING BODY MEMORY AND MEMORY CIRCUIT - A floating body memory cell, memory circuit, and method for fabricating floating body memory cells. The floating body memory cell includes a bi-layer heterojunction having a first semiconductor coupled to a second semiconductor. The first semiconductor and the second semiconductor have different energy band gaps. The floating body memory cell includes a buried insulator layer. The floating body memory cell includes a back transistor gate separated from the second semiconductor of the bi-layer heterojunction by at least the buried insulated layer. The floating body memory cell also includes a front transistor gate coupled to the first semiconductor of the bi-layer heterojunction. | 12-13-2012 |
20120313168 | FORMATION OF EMBEDDED STRESSOR THROUGH ION IMPLANTATION - An extremely-thin silicon-on-insulator transistor includes a buried oxide layer above a substrate. The buried oxide layer, for example, has a thickness that is less than 50 nm. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer includes at least a gate dielectric formed on the silicon layer and a gate conductor formed on the gate dielectric. A gate spacer has a first part on the silicon layer and a second part adjacent to the gate stack. A first raised source/drain region and a second raised source/drain region each have a first part that includes a portion of the silicon layer and a second part adjacent to the gate spacer. At least one embedded stressor is formed at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer. | 12-13-2012 |
20120326232 | MOSFET WITH RECESSED CHANNEL FILM AND ABRUPT JUNCTIONS - MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created. | 12-27-2012 |
20120329232 | Raised Source/Drain Field Effect Transistor - In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length. | 12-27-2012 |
20130011975 | RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER - A gate stack is formed on a silicon layer that is above a buried oxide layer. The gate stack comprises a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A first nitride layer is formed on the silicon layer and the gate stack. An oxide layer is formed on the first nitride layer. A second nitride layer is formed on the oxide layer. The first nitride layer and the oxide layer are etched so as to form a nitride liner and an oxide liner adjacent to the gate stack. The second nitride layer is etched so as to form a first nitride spacer adjacent to the oxide liner. A faceted raised source/drain region is epitaxially formed adjacent to the nitride liner, the oxide liner, and first nitride spacer. Ions are implanted into the faceted raised source/drain region using the first nitride spacer. | 01-10-2013 |
20130015534 | THREE DIMENSIONAL FET DEVICES HAVING DIFFERENT DEVICE WIDTHSAANM Cheng; KangguoAACI SchenectadyAAST NYAACO USAAGP Cheng; Kangguo Schenectady NY USAANM Doris; Bruce B.AACI BrewsterAAST NYAACO USAAGP Doris; Bruce B. Brewster NY USAANM Khakifirooz; AliAACI Mountain ViewAAST CAAACO USAAGP Khakifirooz; Ali Mountain View CA USAANM Kulkarni; PranitaAACI SlingerlandsAAST NYAACO USAAGP Kulkarni; Pranita Slingerlands NY US - A three dimensional FET device structure which includes a plurality of three dimensional FET devices. Each of the three dimensional FET devices include an insulating base, a three dimensional fin oriented perpendicular to the insulating base, a gate dielectric wrapped around the three dimensional fin and a gate wrapped around the gate dielectric and extending perpendicularly to the three dimensional fin, the three dimensional fin having a device width being defined as the circumference of the three dimensional fin in contact with the gate dielectric. At least a first of the three dimensional FET devices has a first device width while at least a second of the three dimensional FET devices has a second device width. The first device width is different than the second device width. Also included is a method of making the three dimensional FET device structure. | 01-17-2013 |
20130043520 | Raised Source/Drain Field Effect Transistor - In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length. | 02-21-2013 |
20130062702 | CMOS STRUCTURE HAVING MULTIPLE THRESHOLD VOLTAGE DEVICES - A method of forming a complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes forming a first transistor device and a second transistor device on a semiconductor substrate. The first transistor device and second transistor device initially have sacrificial dummy gate structures. The sacrificial dummy gate structures are removed and a set of vertical oxide spacers are selectively formed for the first transistor device. The set of vertical oxide spacers are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device. | 03-14-2013 |
20130062704 | CMOS STRUCTURE HAVING MULTIPLE THRESHOLD VOLTAGE DEVICES - A complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes a first transistor device and a second transistor device formed on a semiconductor substrate. A set of vertical oxide spacers selectively formed for the first transistor device are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device. | 03-14-2013 |
20130075817 | JUNCTIONLESS TRANSISTOR - A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type. | 03-28-2013 |
20130078777 | METHOD FOR FABRICATING JUNCTIONLESS TRANSISTOR - A method is provided for fabricating a transistor. According to the method, a doped material layer is formed on a semiconductor layer, and dopant is diffused from the doped material layer into the semiconductor layer to form a graded dopant region in the semiconductor layer. The graded dopant region has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer, with a gradual decrease in the doping concentration. The doped material layer is removed, and then a gate stack is formed on the semiconductor layer. Source and drain regions are formed adjacent to an active area that is in the semiconductor layer underneath the gate stack. The active area comprises at least a portion of the graded dopant region, and the source and drain regions and the active area have the same conductivity type. | 03-28-2013 |
20130082306 | ENHANCEMENT OF CHARGE CARRIER MOBILITY IN TRANSISTORS - Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region. | 04-04-2013 |
20130082308 | SEMICONDUCTOR DEVICES WITH RAISED EXTENSIONS - Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate. | 04-04-2013 |
20130082311 | SEMICONDUCTOR DEVICES WITH RAISED EXTENSIONS - Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate. | 04-04-2013 |
20130082328 | ENHANCEMENT OF CHARGE CARRIER MOBILITY IN TRANSISTORS - Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region. | 04-04-2013 |
20130093019 | FINFET PARASITIC CAPACITANCE REDUCTION USING AIR GAP - A transistor, for example a FinFET, includes a gate structure disposed over a substrate. The gate structure has a width and also a length and a height defining two opposing sidewalls of the gate structure. The transistor further includes at least one electrically conductive channel between a source region and a drain region that passes through the sidewalls of the gate structure; a dielectric layer disposed over the gate structure and portions of the electrically conductive channel that are external to the gate structure; and an air gap underlying the dielectric layer. The air gap is disposed adjacent to the sidewalls of the gate structure and functions to reduce parasitic capacitance of the transistor. At least one method to fabricate the transistor is also disclosed. | 04-18-2013 |
20130105818 | MOSFET WITH THIN SEMICONDUCTOR CHANNEL AND EMBEDDED STRESSOR WITH ENHANCED JUNCTION ISOLATION AND METHOD OF FABRICATION | 05-02-2013 |
20130154001 | EMBEDDED STRESSORS FOR MULTIGATE TRANSISTOR DEVICES - Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region. | 06-20-2013 |
20130154029 | EMBEDDED STRESSORS FOR MULTIGATE TRANSISTOR DEVICES - Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region. | 06-20-2013 |
20130175579 | TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN - A transistor includes a first semiconductor layer. A second semiconductor layer is located on the first semiconductor layer. A portion of the second semiconductor layer is removed to expose a first portion of the first semiconductor layer and to provide vertical sidewalls of the second semiconductor layer. A gate spacer is located on the second semiconductor layer. A gate dielectric includes a first portion located on the first portion of the first semiconductor layer and a second portion adjacent to the vertical sidewalls of the second semiconductor layer. A gate conductor is located on the first portion of the gate dielectric and abuts the gate dielectric second portion. A channel region is located in at least part of the first portion of the first semiconductor layer. Raised source/drain regions are located in the second semiconductor layer. At least part of the raised source/drain regions is located below the gate spacer. | 07-11-2013 |
20130175595 | INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC - An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed. | 07-11-2013 |
20130175606 | INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME - A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed. | 07-11-2013 |
20130175626 | INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME - A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed. | 07-11-2013 |
20130175661 | Integrated Circuit Having Back Gating, Improved Isolation And Reduced Well Resistance And Method To Fabricate Same - A structure includes a silicon substrate; at least two wells in the silicon substrate; and a deep trench isolation (DTI) separating the two wells. The DTI has a top portion and a bottom portion having a width that is larger than a width of the top portion. The structure further includes at least two semiconductor devices disposed over one of the wells, where the at least two semiconductor devices are separated by a shallow trench isolation (STI). In the structure sidewalls of the top portion of the DTI and sidewalls of the STI are comprised of doped, re-crystallized silicon. The doped, re-crystallized silicon can be formed by an angled ion implant that uses, for example, one of Xe, In, BF | 07-11-2013 |
20130178022 | METHOD FOR FABRICATING TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN - A method is provided for fabricating a transistor. According to the method, a second semiconductor layer is formed on a first semiconductor layer, and a dummy gate structure is formed on the second semiconductor layer. A gate spacer is formed on sidewalls of the dummy gate structure, and the dummy gate structure is removed to form a cavity. The second semiconductor layer beneath the cavity is removed. A gate dielectric is formed on the first portion of the first semiconductor layer and adjacent to the sidewalls of the second semiconductor layer and sidewalls of the gate spacer. A gate conductor is formed on the first portion of the gate dielectric and abutting the second portion of the gate dielectric. Raised source/drain regions are formed in the second semiconductor layer, with at least part of the raised source/drain regions being below the gate spacer. | 07-11-2013 |
20130178043 | Integrated Circuit Including DRAM and SRAM/Logic - A method includes providing a substrate having an N+ type layer; forming a P type region in the N+ type layer disposed within the N+ type layer; forming a first deep trench isolation structure extending through a silicon layer and into the N+ type layer to a depth that is greater than a depth of the P type layer; forming a dynamic RAM FET in the silicon layer, forming a first logic/static RAM FET in the silicon layer above the P type region, the P type region being functional as a P-type back gate of the first logic/static RAM FET; and forming a first contact through the silicon layer and an insulating layer to electrically connect to the N+ type layer and a second contact through the silicon layer and the insulating layer to electrically connect to the P type region. | 07-11-2013 |
20130193515 | SRAM WITH HYBRID FINFET AND PLANAR TRANSISTORS - An SRAM structure and method which includes a semiconductor on insulator (SOI) substrate which includes a semiconductor substrate, an insulating layer and a semiconductor on insulator (SOI) layer. The SOI layer has a first thickness. The SRAM structure further includes a FinFET transistor formed on the SOI substrate including a first defined portion of the SOI layer of the first thickness forming an active layer of the FinFET transistor and a gate dielectric on the first defined portion of the SOI layer and a planar transistor formed on the SOI substrate including a second defined portion of the SOI layer of a second thickness forming an active layer of the planar transistor and a gate dielectric on the second defined portion of the SOI layer. The first thickness is greater than the second thickness. Also included is a gate electrode on the FinFET transistor and the planar transistor. | 08-01-2013 |
20130207189 | INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME - A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed. | 08-15-2013 |
20130214356 | MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE - An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask. | 08-22-2013 |
20130270627 | FinFET NON-VOLATILE MEMORY AND METHOD OF FABRICATION - A method of manufacturing a FinFET non-volatile memory device and a FinFET non-volatile memory device structure. A substrate is provided and a layer of semiconductor material is deposited over the substrate. A hard mask is deposited over the semiconductor material and the structure is patterned to form fins. A charge storage layer is deposited over the structure, including the fins and the portions of it are damaged using an angled ion implantation process. The damaged portions are removed and gate structures are formed on either side of the fin, with only one side having a charge storage layer. | 10-17-2013 |
20130299906 | BURIED-CHANNEL FIELD-EFFECT TRANSISTORS - A buried-channel field-effect transistor includes a semiconductor layer formed on a substrate. The semiconductor layer includes doped source and drain regions and an undoped channel region. the transistor further includes a gate dielectric formed over the channel region and partially overlapping the source and drain regions; a gate formed over the gate dielectric; and a doped shielding layer between the gate dielectric and the semiconductor layer. | 11-14-2013 |
20130302949 | BURIED-CHANNEL FIELD-EFFECT TRANSISTORS - Methods for forming a buried-channel field-effect transistor include doping source and drain regions on a substrate with a dopant having a first type; forming a doped shielding layer on the substrate in a channel region having a second doping type opposite the first type to displace a conducting channel away from a gate-interface region; forming a gate dielectric over the doped shielding layer; and forming a gate on the gate dielectric. | 11-14-2013 |
20130302962 | MOSFET WITH THIN SEMICONDUCTOR CHANNEL AND EMBEDDED STRESSOR WITH ENHANCED JUNCTION ISOLATION AND METHOD OF FABRICATION - A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage. | 11-14-2013 |
20130313643 | Structure and Method to Modulate Threshold Voltage For High-K Metal Gate Field Effect Transistors (FETs) - A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed. | 11-28-2013 |
20130313651 | INTEGRATED CIRCUIT WITH ON CHIP PLANAR DIODE AND CMOS DEVICES - An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer. | 11-28-2013 |
20130316503 | STRUCTURE AND METHOD TO MODULATE THRESHOLD VOLTAGE FOR HIGH-K METAL GATE FIELD EFFECT TRANSISTORS (FETs) - A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed. | 11-28-2013 |
20130341754 | SHALLOW TRENCH ISOLATION STRUCTURES - Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate. | 12-26-2013 |
20130344677 | SHALLOW TRENCH ISOLATION STRUCTURES - Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate. | 12-26-2013 |
20140017859 | METHOD FOR FABRICATING TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN - A method is provided for fabricating a transistor. According to the method, a second semiconductor layer is formed on a first semiconductor layer, and a dummy gate structure is formed on the second semiconductor layer. A gate spacer is formed on sidewalls of the dummy gate structure, and the dummy gate structure is removed to form a cavity. The second semiconductor layer beneath the cavity is removed. A gate dielectric is formed on the first portion of the first semiconductor layer and adjacent to the sidewalls of the second semiconductor layer and sidewalls of the gate spacer. A gate conductor is formed on the first portion of the gate dielectric and abutting the second portion of the gate dielectric. Raised source/drain regions are formed in the second semiconductor layer, with at least part of the raised source/drain regions being below the gate spacer. | 01-16-2014 |
20140024181 | SEMICONDUCTOR STRUCTURE HAVING NFET EXTENSION LAST IMPLANTS - A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion. | 01-23-2014 |
20140035000 | Source and Drain Doping Profile Control Employing Carbon-Doped Semiconductor Material - Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions locally retard dopant diffusion from the raised source and drain regions into the underlying semiconductor material regions, thereby enabling local tailoring of the dopant profile, and alteration of device parameters for the field effect transistor. | 02-06-2014 |
20140049315 | Inversion Mode Varactor - In one exemplary embodiment of the invention, a method includes: providing an inversion mode varactor having a substrate, a backgate layer overlying the substrate, an insulating layer overlying the backgate layer, a semiconductor layer overlying the insulating layer and at least one metal-oxide semiconductor field effect transistor (MOSFET) device disposed upon the semiconductor layer, where the semiconductor layer includes a source region and a drain region, where the at least one MOSFET device includes a gate stack defining a channel between the source region and the drain region, where the gate stack has a gate dielectric layer overlying the semiconductor layer and a conductive layer overlying the gate dielectric layer; and applying a bias voltage to the backgate layer to form an inversion region in the semiconductor layer at an interface between the semiconductor layer and the insulating layer. | 02-20-2014 |
Pranita Kulkarni, Mount Kisco, NY US
Patent application number | Description | Published |
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20130175594 | INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC - An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region. | 07-11-2013 |
20130292766 | SEMICONDUCTOR SUBSTRATE WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES - A semiconductor integrated circuit is provided and includes a first field effect transistor (FET) device and a second FET device formed on a semiconductor substrate. The first FET device has raised source/drain (RSD) structures grown at a first height. The second FET device has RSD structures grown at a second height greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device. | 11-07-2013 |
20130295730 | SEMICONDUCTOR SUBSTRATE WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES - A method of creating a semiconductor integrated circuit is disclosed. The method includes forming a first field effect transistor (FET) device and a second FET device on a semiconductor substrate. The method includes epitaxially growing raised source/drain (RSD) structures for the first FET device at a first height. The method includes epitaxially growing raised source/drain (RSD) structures for the second FET device at a second height. The second height is greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device. | 11-07-2013 |
Pranita Kulkarni, Albany, NY US
Patent application number | Description | Published |
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20110037128 | METHOD AND STRUCTURE FOR IMPROVING UNIFORMITY OF PASSIVE DEVICES IN METAL GATE TECHNOLOGY - Method of forming a semiconductor device which includes the steps of obtaining a semiconductor substrate having a logic region and an STI region; sequentially depositing layers of high K material, metal gate, first silicon and hardmask; removing the hardmask and first silicon layers from the logic region; applying a second layer of silicon on the semiconductor substrate such that the logic region has layers of high K material, metal gate and second silicon and the STI region has layers of high K material, metal gate, first silicon, hardmask and second silicon. There may also be a second hardmask layer between the metal gate layer and the first silicon layer in the STI region. There may also be a hardmask layer between the metal gate layer and the first silicon layer in the STI region but no hardmask layer between the first and second layers of silicon in the STI region. | 02-17-2011 |
20110042744 | METHOD OF FORMING EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) DEVICE WITHOUT ION IMPLANTATION - A method of fabricating a semiconductor device is provided in which the channel of the device is present in an extremely thin silicon on insulator (ETSOI) layer, i.e., a silicon containing layer having a thickness of less than 10.0 nm. In one embodiment, the method may begin with providing a substrate having at least a first semiconductor layer overlying a dielectric layer, wherein the first semiconductor layer has a thickness of less than 10.0 nm. A gate structure is formed directly on the first semiconductor layer. A in-situ doped semiconductor material is formed on the first semiconductor layer adjacent to the gate structure. The dopant from the in-situ doped semiconductor material is then diffused into the first semiconductor layer to form extension regions. The method is also applicable to finFET structures. | 02-24-2011 |
20110115022 | IMPLANT FREE EXTREMELY THIN SEMICONDUCTOR DEVICES - A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer. Epitaxially growing the extremely thin semiconductor layer on the Ge layer ensures good thickness control across the wafer. This process could be used for SOI or bulk wafers. | 05-19-2011 |
20110121370 | EMBEDDED STRESSOR FOR SEMICONDUCTOR STRUCTURES - A method of fabricating an embedded stressor within a semiconductor structure and a semiconductor structure including the embedded stressor includes forming forming a dummy gate stack over a substrate of stressor material, anistropically etching sidewall portions of the substrate subjacent to the dummy gate stack to form the embedded stressor having angled sidewall portions, forming conductive material onto the angled sidewall portions of the embedded stressor, removing the dummy gate stack, planarizing the conductive material, and forming a gate stack on the conductive material. | 05-26-2011 |
20110221003 | MOSFETs WITH REDUCED CONTACT RESISTANCE - A method and structure for forming a field effect transistor with reduced contact resistance are provided. The reduced contact resistance is manifested by a reduced metal semiconductor alloy contact resistance and a reduced conductively filled via contact-to-metal semiconductor alloy contact resistance. The reduced contact resistance is achieved in this disclosure by texturing the surface of the transistor's source region and/or the transistor's drain region. Typically, both the source region and the drain region are textured in the present disclosure. The textured source region and/or the textured drain region have an increased area as compared to a conventional transistor that includes a flat source region and/or a flat drain region. A metal semiconductor alloy, e.g., a silicide, is formed on the textured surface of the source region and/or the textured surface of the drain region. A conductively filled via contact is formed atop the metal semiconductor alloy. | 09-15-2011 |
20110291100 | DEVICE AND METHOD FOR FABRICATING THIN SEMICONDUCTOR CHANNEL AND BURIED STRAIN MEMORIZATION LAYER - A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material. | 12-01-2011 |
20110291189 | THIN CHANNEL DEVICE AND FABRICATION METHOD WITH A REVERSE EMBEDDED STRESSOR - A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer. A removable buried layer is provided on or in the second semiconductor layer. A gate structure with side spacers is formed on the first semiconductor layer. Recesses are formed down to the removable buried layer in areas for source and drain regions. The removable buried layer is etched away to form an undercut below the dielectric layer below the gate structure. A stressor layer is formed in the undercut, and source and drain regions are formed. | 12-01-2011 |
20110291202 | DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE - A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions. | 12-01-2011 |
20110309445 | SEMICONDUCTOR FABRICATION - Embodiments of the present invention provide the ability to fabricate devices having similar physical dimensions, yet with different operating characteristics due to the different effective channel lengths. The effective channel length is controlled by forming an abrupt junction at the boundary of the gate and at least one source or drain. The abrupt junction impacts the diffusion during an anneal process, which in turn controls the effective channel length, allowing physically similar devices on the same chip to have different operating characteristics. | 12-22-2011 |
20120193710 | DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE - A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions. | 08-02-2012 |
20120261728 | EMBEDDED STRESSOR FOR SEMICONDUCTOR STRUCTURES - A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape. | 10-18-2012 |
20130056802 | IMPLANT FREE EXTREMELY THIN SEMICONDUCTOR DEVICES - A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of | 03-07-2013 |
20130069196 | STRUCTURE AND METHOD TO MINIMIZE REGROWTH AND WORK FUNCTION SHIFT IN HIGH-K GATE STACKS - The present invention provides a semiconductor structure comprising high-k material portions that are self-aligned with respect to the active areas in the semiconductor substrate and a method of fabricating the same. The high-k material is protected from oxidation during the fabrication of the semiconductor structure and regrowth of the high-k material and shifting of the high-k material work function is prevented. | 03-21-2013 |
20130146975 | SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT WITH HIGH-K/METAL GATE WITHOUT HIGH-K DIRECT CONTACT WITH STI - A method, semiconductor device, and integrated circuit with a high-k/metal gate without high-k direct contact with STI. A high-k dielectric and a pad film are deposited directly onto a semiconductor substrate. Shallow trench isolation is performed, with shallow trenches etched directly into the pad film, the high-k material, and the substrate. The shallow trench is lined with an oxygen diffusion barrier and is subsequently filled with an insulating dielectric material. Thereafter the pad film and the insulating dielectric are recessed to a point where the oxygen diffusion barrier still remains between the insulating dielectric and the high-k material, preventing any contact there between. Afterwards a conductive gate is formed overlying the device. | 06-13-2013 |
20150255603 | DEVICE AND METHOD FOR FABRICATING THIN SEMICONDUCTOR CHANNEL AND BURIED STRAIN MEMORIZATION LAYER - A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material. | 09-10-2015 |
Pranita Kulkarni, Hopewell Junction, NY US
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20110254098 | INTEGRATED CIRCUIT WITH REPLACEMENT METAL GATES AND DUAL DIELECTRICS - A replacement gate structure and method of fabrication are disclosed. The method provides for fabrication of both high performance FET and low leakage FET devices within the same integrated circuit. Low leakage FET devices are fabricated with a hybrid gate dielectric comprised of a low-K dielectric layer and a high-K dielectric layer. High performance FET devices are fabricated with a low-K gate dielectric. | 10-20-2011 |
20140264486 | METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE - One method includes forming a recessed gate/spacer structure that partially defines a spacer/gate cap recess, forming a gate cap layer in the spacer/gate cap recess, forming a gate cap protection layer on an upper surface of the gate cap layer, and removing portions of the gate cap protection layer, leaving a portion of the gate cap protection layer positioned on the upper surface of the gate cap layer. A device disclosed herein includes a gate/spacer structure positioned in a layer of insulating material, a gate cap layer positioned on the gate/spacer structure, wherein sidewalls of the gate cap layer contact the layer of insulating material, and a gate cap protection layer positioned on an upper surface of the gate cap layer, wherein the sidewalls of the gate cap protection layer also contact the layer of insulating material. | 09-18-2014 |
20140264487 | METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE - One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material. | 09-18-2014 |
20150041869 | METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE - One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material. | 02-12-2015 |
Prashant Madhukar Kulkarni, Niskayuna, NY US
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20080314878 | APPARATUS AND METHOD FOR CONTROLLING A MACHINING SYSTEM - An apparatus for controlling a machining system is provided. The apparatus include an optical unit configured to capture an image of an object based upon radiation generated from the object and an image processing unit configured to process the image and to obtain real-time estimation of parameters associated with manufacture or repair of the object. The apparatus also includes a process model configured to establish target values for the parameters associated with the manufacture or repair of the object based upon process parameters for the machining system and a controller configured to control the process parameters for the machining system based upon the estimated and target values of the parameters associated with the manufacture or repair of the object. | 12-25-2008 |
Rajendra G. Kulkarni, East Amherst, NY US
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20100203193 | Freezer to Retarder to Oven Dough - A frozen dough comprising flour, a high yeast level comprising one or more yeast with activity covering temperature range of 33-140° F., emulsifiers, dough conditioners, stabilizers, sugar, lipid source and optionally supplemental gluten such that the frozen dough does not require a conventional proofing (proofer) step prior to freezing or prior to baking. When the frozen dough is thawed in a retarder at 33-42° F. for at least 12 hours, or at an elevated temperature of between 43-85° F. for at least 1 hour, and then baked, the baked products have good appearance, taste and texture, and a specific volume of at least 4 cc/gram. | 08-12-2010 |
Rakesh Kulkarni, Webster, NY US
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20120303406 | SYSTEM AND METHOD FOR THE DYNAMIC ALLOCATION OF RESOURCES - A system and method for dynamically allocating resources in a process. A demand pattern change detection unit, a future demand forecasting unit and a process optimization engine can be employed to constantly adjust resource allocation and assist in maintaining processes in a state of peak performance. An initial resource allocation unit generates an initial resource allocation plan based on past experience with respect to the process. The change detection unit detects a shift in the job demand pattern utilizing a statistical data when a change occurs in process requirements. The future demand generation unit accurately generates future demand data based on current job data and the outlook of future demand. The optimization engine acts as a surrogate process expert and provides recommendations to the process owner regarding potential possible resource allocation policies for new job demand data utilizing a simulation process to predict the result of variable staffing configurations. | 11-29-2012 |
20130191190 | METHOD AND SYSTEM FOR MOTIVATING AND OPTIMIZING USAGE OF HIGH OCCUPANCY VEHICLE/HIGH OCCUPANCY TOLL LANE BY DISPLAYING TIME BASED COST METRICS - A method and system for motivating and optimizing usage of a toll lane by displaying a time based cost metric on an electronic display. The real time electronic display can be configured on the toll lane for displaying information with respect to the toll lane to, for example, a driver on a highway. An average speed of vehicles in the toll lane and/or a non-toll lane of the highway over at least one span can be measured and the average speed can be displayed on the electronic display. A toll rate with respect to the usage of the toll lane can be determined and displayed. A time saving value and a cost per unit time with respect to the usage of the toll lane over the span can be calculated and displayed on the electronic display. | 07-25-2013 |
20130226668 | METHOD AND SYSTEM FOR PROVIDING DYNAMIC PRICING ALGORITHM WITH EMBEDDED CONTROLLER FOR HIGH OCCUPANCY TOLL LANES - A method and system for providing a feedback based dynamic pricing algorithm with an embedded controller for a HOT (High Occupancy Toll) lane. An input-output transfer function of a vehicle flow with respect to a HOT lane can be obtained utilizing a simulation module. A feedback controller combined with, for example, a Smith predictor can be designed to avoid an unstable behavior due to a time delay in the HOT lane, a price regulation, and a large transient caused by an integral part of the controller due to traffic jams. A driver behavior preference model can be derived based on a relationship between a toll rate and several characteristics of the HOT lane and a general purpose lane. The feedback controller and the behavior preference model can then be implemented to set the toll rate in real-time in order to satisfy a desired performance metric. | 08-29-2013 |
20140122032 | METHODS, SYSTEMS AND PROCESSOR-READABLE MEDIA FOR OPTIMIZING INTELLIGENT TRANSPORTATION SYSTEM STRATEGIES UTILIZING SYSTEMATIC GENETIC ALGORITHMS - Methods, systems and processor-readable media for modeling and optimizing multiple ITS (Intelligent Transportation System) strategies utilizing a systematic genetic algorithm. A traffic simulation model can be configured in conjunction with a genetic algorithm based optimization engine for optimizing the transportation models. An origin-destination matrix that minimizes discrepancies between a simulated and an observed link traffic count can be estimated by considering a road network and a traffic count with respect to a region. A driver behavior can then be determined utilizing the origin-destination matrix via calibration so that the simulation model can replicate a freeway traffic flow in the region. An optimal parameter with respect to the ITS strategies can be determined to optimize a set goal with respect to a given constraint. Such an approach meets a level of service (LOS) metric as well as a revenue target under the applied ITS strategies. | 05-01-2014 |
20140372163 | METHODS AND SYSTEMS FOR ADJUSTING COMPENSATION FOR TASKS - Method and system for dynamically adjusting compensation for one or more tasks are disclosed. The method includes estimating the compensation for each task in a batch of tasks based on at least one of a minimum wage for a task in the batch of tasks, one or more attributes associated with the worker, a number and type of tasks in the batch of tasks, or a target level of service. The compensation for the each task of the batch of tasks is then adjusted based on at least one of an observed level of service associated with the batch of tasks and the target level of service. The method is performed using a processor. | 12-18-2014 |
Rakesh S. Kulkarni, Webster, NY US
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20100091334 | DIGITAL COMPENSATION METHOD AND APPARATUS - A digital image processing method. The method includes printing a first set of reference marks on one side of a substrate with a first print engine; printing a second set of reference marks on the same side of the substrate as the first set of reference marks with a second print engine; sensing both sets of reference marks on the substrate with an image sensing unit and generating a digital image of the reference marks; performing image analysis on the digital image to obtain an image-to-image distortion map where the image-to-image distortion map is a local measure of difference between the first set of reference marks and the second set of reference marks; and generating a compensated customer image by using the image-to-image distortion map to reduce registration errors when using the first and second print engines. | 04-15-2010 |
20140218771 | SCANNING DOCUMENTS USING ENVELOPES AS DOCUMENT SEPARATORS - Methods and systems remove sheets of media from envelopes, and scan the envelopes and the sheets of media through an optical scanner. Such method and systems use the envelopes as separator sheets between groups of the sheets of media. During the scans each envelope is followed by a corresponding group of sheets of media that were within the envelope when the envelope was received. Further, the exterior of each envelope comprises classification data that classifies the corresponding group of the sheets of media. Such methods and systems produce electronic scan documents of scans of the groups of sheets separated according to the envelopes that act as the separator sheets. The electronic scan documents and the classification data can then be automatically provided to an electronic records system. The electronic records system automatically processes the electronic scan documents using the classification data. | 08-07-2014 |
20140336027 | SYSTEM AND METHOD FOR CREATING CUSTOMIZED BOXES - A computer-based system for creating customized storage boxes, including: a computer with a memory element storing computer readable instructions and a processor to execute the instructions to: receive first data specifying an item for storage; receive second data specifying a number of the item for storage in at least one box or a use of the item; receive third data describing a physical attribute of the item; calculate, using the first, second, and third data, a volume of the at least one box; and transmit fourth data, including the volume. The system includes a packaging device to receive the fourth data and generate, using the fourth data, a two-dimensional layout, on a piece of media, for the at least one box. The layout includes a plurality of lines, on the piece of media for creasing or cutting the piece of media to form the at least one box. | 11-13-2014 |
20150106171 | DYNAMIC PRICING BASED ON SLIDING MODE CONTROL AND ESTIMATION FOR HIGH OCCUPANCY TOLL LANES - Methods and systems for dynamic pricing based on sliding mode control with respect to a HOT (High Occupancy Toll) lane. The controller consists of a feed-forward path and a feedback path. In the feed-forward path, a sliding mode controller in association with a sliding mode control module can be configured to achieve desired performance objectives under time-varying system parameters in real-time. An estimated VOT (Value of Time) distribution can be derived in association with the controller to reduce the difference between an actual and target traffic flow density on the HOT lane. The estimation of the VOT distribution can be updated by the controller at each time interval when the difference in densities is larger than a certain threshold. A low pass filter can also be employed to substantially improve prediction and the calculation of tolls to reduce fluctuations in traffic. | 04-16-2015 |
Rakesh Suresh Kulkarni, Webster, NY US
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20090115124 | METHOD AND SYSTEM FOR CORRECTING LATERAL POSITION ERROR - A method of removing media lateral DC position errors in a long paper path using closed loop correction is disclosed. The amount of lateral DC media shift error generated (or the lateral DC correction required) in the paper path is sensed by a CCD or full width array sensor located in the downstream paper path. In the closed loop, this information is used to energize a motorized actuator in the upstream paper path to correct for lateral DC errors in the media path. Thus, the paper is delivered to the downstream media path within specifications. | 05-07-2009 |
20100046033 | Method to Improve Image on Paper Registration Measurements - A method of controlling the placement of images on output of a printer, including determining scanner spatial error using an ideal medium having a first two-dimensional array on the ideal medium then determining printer spatial error using a second medium having a second two-dimensional array; and finally, controlling placement of images on the output of the printer based on the scanner spatial error and the printer spatial error. | 02-25-2010 |
20100309526 | REDUCING IOP REGISTRATION ERROR IN A DIGITAL DOCUMENT SYSTEM - What is disclosed is a novel method for reducing errors in IOP registration of a digital document system. In one embodiment, a number of digital pages (10, for example) are received in the image path. For each of a process and lateral direction of a first side of each digital image, a total amount of IOP registration error to be corrected is determined. A portion of the total IOP registration error is estimated that is separable error. Each of the estimated separable errors are subtracted from the total IOP registration error to obtain an amount of non-separable error in each respective direction. The non-separable error values are averaged to obtain an error value for each direction per-side. The error values are compensated for in their respective directions per-side by adjustments to the device in an amount which is equal in magnitude and in an opposite direction to the error. | 12-09-2010 |
20100322688 | IMAGE ALIGNMENT PROCEDURE - This is an alignment system where precise alignment of a reproducible image is obtained with respect to the paper. An imaged paper to be reproduced is placed on a light table having a right angle fitting or marking. The paper is placed on top of the light table and is aligned with this right angle marking. A transparent platen with marked scales is placed over the imaged paper and also aligned with the right angle fitting. The scales are placed over the corners of the image and image corner location readings are taken from the scales. These readings are then entered and fixed into a marking system such as an electrophotographic printer for reproduction of copies from the aligned and fixed original image. | 12-23-2010 |
20110122455 | METHOD AND APPARATUS FOR MEASURING IMAGE ON PAPER REGISTRATION - A method and apparatus for measuring image on paper registration including placing a test sheet of media including a plurality of test pattern marks on a platen of an image sensing device. The platen defines a scan area over which the image sensing device is capable of scanning an image. The image sensing device includes a plurality of calibration marks falling within the scan area. The method further includes operating the scanner to scan the test sheet; determining a scanned position of the calibration marks and a scanned position of the test marks resulting from the scan; comparing the scanned position of the calibration marks with reference position of the calibration marks to determine scanning error; determining an adjusted position of the test marks responsive to the scanning error; and comparing the adjusted test mark positions with predetermined reference positions to measure registration accuracy. An edge guide disposed on the platen assists in aligning the test sheet for scanning. | 05-26-2011 |
20110196718 | SYSTEM AND METHOD FOR FORECASTING IN THE PRESENCE OF MULTIPLE SEASONAL PATTERNS IN PRINT DEMAND - A system for forecasting an inventory level for a consumable in a print production environment may include a computing device and a computer-readable storage medium in communication with the computing device. The computer-readable storage medium may include one or more programming instructions for identifying a demand distribution for a print product resource consumable, identifying a first seasonal period in the demand distribution, creating a seasonally adjusted demand distribution, identifying a second seasonal period in the seasonally adjusted demand distribution, creating an updated seasonally adjusted demand distribution, using a forecasting model to automatically forecast a predicted future demand value for the consumable, updating the predicted future demand value using, determining whether additional inventory is needed based on at least the updated predicted future demand value, and in response to a need for additional inventory, generating an order for the print product resource consumable. | 08-11-2011 |
20140095068 | METHOD AND SYSTEM FOR REDUCING TRAFFIC CONGESTION - A point-based method, system and processor-readable medium for reducing traffic congestion. A license plate number associated with a vehicle can be captured utilizing an image capturing unit and/or a GPS (Global Positioning System) enabled mobile communication device to store/deduct points with respect to a user account on a point storage server. The points can be stored in a user account based on a dynamic policy if a user selects a sub-optimal path (e.g., general-purpose lane or a far-away parking spot) and the level of urgency related to travel is low to reduce congestion. The points can be deducted later if the user decides to take an optimal path (e.g., HOT lane or a near-center parking spot). The points on each path can be dynamically set based on time of day to maintain traffic flow at an optimal level. | 04-03-2014 |
20150363928 | DETECTING FEBRILE SEIZURE WITH A THERMAL VIDEO CAMERA - What is disclosed is a system and method for detecting febrile seizure using a thermal video camera. In one embodiment, a video is received comprising time-sequential thermal images of a subject. The video is acquired of the subject in real-time using a thermal video system. Each thermal image comprises a plurality of pixels with an intensity value of each pixel corresponding to a temperature. The thermal images are processed to determine an occurrence of a febrile seizure. The processing involves identifying a region of interest in the thermal image and determining a temperature for the region of interest based on values of the pixels isolated in that region of interest. Thereafter, a rate of change of temperatures is obtained for the subject in real-time on a per-frame basis. If the rate of change is determined to have exceeded a pre-defined threshold level, then the subject is having a febrile seizure. | 12-17-2015 |
Sudhir Rajaram Kulkarni, Albany, NY US
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20150092343 | ULTRA-CAPACITOR STRUCTURES AND ELECTRONIC SYSTEMS WITH ULTRA-CAPACITOR STRUCTURES - Ultra-capacitor structures and electronic systems and assemblies are provided. In one aspect, the ultra-capacitor structure is configured to selectively power and at least partially house electronic component(s) therein. In one embodiment, the ultra-capacitor structure includes a thermally conductive material facilitating dissipation of heat generated. In another embodiment, the ultra-capacitor structure includes an electrically conductive sheet facilitating electromagnetic shielding. In another aspect, an electronic system includes: an electronic device including electronic component(s); and a support structure physically receiving and electrically coupling to the electronic device, and including an ultra-capacitor structure configured to selectively power the electronic component(s) of the electronic device when electrically coupled to the support structure. In another aspect, an electronic assembly has a first region including electronic component(s), and a second region including an ultra-capacitor structure configured to selectively power the electronic component(s) of the electronic assembly, where the first region is spaced apart from the second region. | 04-02-2015 |
20160087460 | ULTRA-CAPACITOR STRUCTURES WITH MULTIPLE ULTRA-CAPACITOR CELLS AND METHODS THEREOF - Ultra-capacitor structures and methods thereof are presented. In one aspect, a structure includes: an ultra-capacitor structure having multiple ultra-capacitor cells; and a switching mechanism, the switching mechanism being operable to selectively connect different electrical interconnect configurations of the multiple ultra-capacitor cells of the ultra-capacitor structure to provide any one of a plurality of different voltages or currents to at least one electrical load, and to selectively control charging of the multiple ultra-capacitor cells using energy from at least one battery. In another aspect, a method includes: obtaining an ultra-capacitor structure having multiple ultra-capacitor cells; connecting different electrical interconnect configurations of the multiple ultra-capacitor cells of the ultra-capacitor structure to provide any one of a plurality of different voltages or currents to at least one electrical load; and charging the ultra-capacitor structure using energy from at least one battery. | 03-24-2016 |
Sudhir Rajaram Kulkarni, Rensselaer, NY US
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20140287277 | ENERGY STORAGE STRUCTURES AND FABRICATION METHODS THEREOF - Energy storage structures and fabrication methods are provided. The method include: providing first and second conductive sheet portions separated by a permeable separator sheet, and defining, at least in part, outer walls of the energy storage structure, the first and second surface regions of the first and second conductive sheet portions including first and second electrodes facing first and second (opposite) surfaces of the permeable separator sheet; forming an electrolyte receiving chamber, defined, at least in part, by the first and second surface regions, including: bonding the first and second conductive sheet portions, and the permeable separator sheet together with at least one bonding border forming a bordering frame around at least a portion of the first and second electrodes; and providing an electrolyte within the electrolyte receiving chamber, including in contact with the first and second electrodes, with the electrolyte being capable of passing through the permeable separator sheet. | 09-25-2014 |