Patent application number | Description | Published |
20080214138 | Integrated tracking filters for direct conversion and low-IF single conversion broadband filters - A radio frequency (RF) tuner includes a programmable tracking filter bank receiving an RF input and outputting a filtered RF signal. A mixer stage receives the filtered RF signal and outputs a first quadrature component of the filtered RF signal and a second quadrature component of the filtered RF signal. Two variable gain amplifiers receive the first and second quadrature components and output amplitude-controlled I and Q components of the filtered RF signal. In one embodiment, the programmable tracking filter bank includes a plurality of tank circuits each connected to the RF input through an impedance. Each tank circuit include an inductor and a capacitor connected in parallel thereby forming an LC network, and a plurality of switched capacitors in parallel with the LC network and switched in and out of the tank circuit by programmable switches. In another embodiment, the programmable tracking filter bank includes a plurality of peaked low-pass circuits each connected to the RF input through an impedance. Each peaked low-pass circuit includes a capacitor connected to ground, and a plurality of switched capacitors in parallel with the capacitor and switched in and out of the peaked low-pass circuit by programmable switches. | 09-04-2008 |
20080265929 | Process Monitor for Monitoring and Compensating Circuit Performance - A method and system for monitoring and compensating the performance of an operational circuit is provided. The system includes one or more integrated circuit chips and a controller. Each integrated circuit chip includes one or more operational circuits, each operational circuit having at least one controllable circuit parameter. Each integrated circuit chip also includes a process monitor module at least partially constructed thereon. The controller is coupled to each process monitor module and to each operational circuit. The controller includes logic for evaluating the performance of an operational circuit based on data obtained from process monitor module and operational circuit related data stored in a memory. Based on the evaluation, the controller determines whether any deviations from desired or optimal performance of the circuit exist. If deviations exist, the controller generates a control signal to initiate adjustments to the operational circuit to compensate for the deviations. | 10-30-2008 |
20090040393 | Quadrature correction method for analog television reception using direct-conversion tuners - A direct conversion radio frequency (RF) tuner includes a mixer generating I and Q quadrature components. A phase detection circuit generates a phase error measurement between the I quadrature component and the Q quadrature component. A phase correction circuit corrects a phase of the Q component based on the phase error measurement, and outputs a phase-corrected Q quadrature component. An I quadrature component gain control circuit receives the I quadrature component and outputting an amplitude corrected I quadrature component. A Q quadrature component gain control circuit receives the phase corrected Q quadrature component and outputs an amplitude corrected Q quadrature component. | 02-12-2009 |
20090058536 | APPARATUS AND METHOD FOR PHASE LOCK LOOP GAIN CONTROL USING UNIT CURRENT SOURCES - A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for-changing PLL operating conditions, in addition to compensating for variable VCO gain. | 03-05-2009 |
20090085597 | Process Monitor for Monitoring an Integrated Circuit Chip - A system or apparatus for monitoring an Integrated Circuit (IC) chip includes: a sense circuit at least partially constructed on the IC chip and configured to produce one or more sense signals each indicative of a corresponding process-dependent circuit parameter of the IC chip; and a digitizer module configured to produce, responsive to the one or more sense signals, one or more digitized signals each representative of a corresponding one of the sense signals. A controller is configured to determine a value of one or more of the process-dependent circuit parameters based on one or more of the digitized signals. | 04-02-2009 |
20100167683 | Apparatus and Method for Local Oscillator Calibration in Mixer Circuits - An apparatus and method for local oscillator calibration compensates for filter passband variation in a mixer circuit, such as a receiver circuit. The receiver includes at least a mixer circuit and a filter coupled to the output of the mixer. During operation, the mixer mixes an RF input signal with a first local oscillator (LO) signal to frequency translate a selected channel in the RF input signal into the passband of the filter. During a calibration mode, the RF input signal is disabled, and the first LO signal is injected into the filter input by leaking the first LO signal through the mixer circuit. The frequency of the LO signal is then swept over a frequency bandwidth that is sufficiently wide so that the actual passband is detected by measuring the signal amplitude at the output of the bandpass filter, thereby determining any variation in the passband of the filter from the expected passband. Once the actual passband is determined, then the frequency of the first local oscillator signal is adjusted or tuned to compensate for any frequency shift of the actual passband compared to the expected passband. Therefore, the selected channel is up-converted into the center of the actual passband of the bandpass filter and will not fall outside the passband. This enables the passband of the bandpass filter to be narrowed, as compared with conventional receivers that do not utilize this calibration procedure. For example, the bandpass filter can be narrowed to one or two channels wide. | 07-01-2010 |
20100237884 | INTEGRATED SWITCHLESS PROGRAMMABLE ATTENUATOR AND LOW NOISE AMPLIFIER - An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. | 09-23-2010 |
20100261446 | Apparatus and Method for Local Oscillator Calibration in Mixer Circuits - An apparatus and method for local oscillator calibration compensates for filter passband variation in a mixer circuit, such as a receiver circuit. The receiver includes at least a mixer circuit and a filter coupled to the output of the mixer. During operation, the mixer mixes an RF input signal with a first local oscillator (LO) signal to frequency translate a selected channel in the RF input signal into the passband of the filter. During a calibration mode, the RF input signal is disabled, and the first LO signal is injected into the filter input by leaking the first LO signal through the mixer circuit. The frequency of the LO signal is then swept over a frequency bandwidth that is sufficiently wide so that the actual passband is detected by measuring the signal amplitude at the output of the bandpass filter, thereby determining any variation in the passband of the filter from the expected passband. Once the actual passband is determined, then the frequency of the first local oscillator signal is adjusted or tuned to compensate for any frequency shift of the actual passband compared to the expected passband. Therefore, the selected channel is up-converted into the center of the actual passband of the bandpass filter and will not fall outside the passband. This enables the passband of the bandpass filter to be narrowed, as compared with conventional receivers that do not utilize this calibration procedure. For example, the bandpass filter can be narrowed to one or two channels wide. | 10-14-2010 |
20100296573 | Systems and methods for digital upconversion for digital signals - Systems and methods for digital upconversion of digital signals are provided. In one embodiment, the system includes a digital frequency adjustment system and a digital to analog conversion system. In a feature of the embodiment, the digital frequency adjustment system consists of set of digital upconversion and upsample elements that shift upwards the frequency of baseband signals. In a further feature of the embodiment, a tree structure of sets of upsample and upconversion elements is used. In another embodiment, the system includes digital and analog frequency adjustment systems in which the frequencies of the input signals are partially upshifted within both the digital and analog domains. Methods for digital upconversion of digital signals are also provided. | 11-25-2010 |
20110193625 | Amplifier for Cable and Terrestrial Applications with Independent Stage Frequency Tilt - A system comprises a first amplifier stage including a first amplifier, a second amplifier stage including second and third amplifiers, and a fourth amplifier. The first amplifier stage includes an input and an output. The second amplifier stage is coupled between the output of the first amplifier stage and a first output node. The fourth amplifier is coupled between the input of the first amplifier stage and a second output node. | 08-11-2011 |
20110193626 | FREQUENCY RESPONSE COMPENSATION AMPLIFIER ARRANGEMENTS - An embodiment of the present invention provides a system comprising a summing device and first amplifier portion. The summing device is coupled to an output node. The first amplifier portion is coupled between an input node and the summing device. The first amplifier portion includes a first amplifier, a first filter, and first and second switches. The first amplifier is coupled between the input node and the summing device on a first path. The first filter is coupled between the input node and the first amplifier on a second path, the second path being in parallel to the first path. The first switch is coupled between the input node and the first amplifier along the first path. The second switch is coupled between the input node and the first filter along the second path. | 08-11-2011 |
20110284840 | Process Monitor for Monitoring an Integrated Circuit Chip - A system or apparatus for monitoring an Integrated Circuit (IC) chip includes: a sense circuit at least partially constructed on the IC chip and configured to produce one or more sense signals each indicative of a corresponding process-dependent circuit parameter of the IC chip; and a digitizer module configured to produce, responsive to the one or more sense signals, one or more digitized signals each representative of a corresponding one of the sense signals. A controller is configured to determine a value of one or more of the process-dependent circuit parameters based on one or more of the digitized signals. | 11-24-2011 |
20120163290 | INTERNET PROTOCOL LOW NOISE BLOCK FRONT END ARCHITECTURE - Provided is a packet network adapter operable to receive a satellite intermediate frequency (IF) signal and determine whether the satellite IF signal includes DVB content based upon a network client request. When the satellite IF signal includes the requested DVB content, the satellite network adapter produces packetized data for delivery of the digital content to a network client or clients based upon the network client request. | 06-28-2012 |
20120182162 | Rollover operative digital to analog converter (DAC) - Rollover operative digital to analog converter (DAC). With respect to a codeword that is provided to a DAC, a processing module (e.g., a rollover processor) operates to compare the codeword to threshold(s) in accordance with adaptively partitioning the codeword into one or more sub-codewords when the codeword has a magnitude greater than at least one of the thresholds. In instances that the codeword is less than a threshold, the codeword may be provided directly to a DAC for use in generating a first analog signal. However, if the codeword is a larger than a threshold, then that portion of the codeword which is greater than the threshold may be provided to an alternative component such as one or more auxiliary or additional DACs, one or more other circuitry components, etc. in accordance with generating at least one additional analog signal to be combined with the first analog signal. | 07-19-2012 |
20120182165 | Digital to analog converter (DAC) with ternary or tri-state current source - Digital to analog converter (DAC) with ternary or tri-state current source. A DAC including a number of ternary or tri-state devices operates based upon codewords provided thereto. Generally, each respective codeword bit directs operation of one of the respective ternary or tri-state devices within the DAC. Each ternary or tri-state device operates in at least three respective operational states (e.g., based upon the respective values of +1, −1, or 0 being provided thereto). In a current source implementation, each respective current source is implemented to deliver current, draw current, or neither delivered or draw current. In a voltage source implementation, each respective voltage source is implemented to provide a positive voltage, a negative voltage, or provide no voltage. A DAC coding table may be designed based upon characterization of codewords provided to one or more DACs (e.g., based upon a distribution, a probability density function (PDF), etc. of such codewords). | 07-19-2012 |
20120183027 | Dual digital to analog converters (DACs) with codeword parsing - Dual digital to analog converters (DACs) with codeword parsing. With respect to a codeword that is provided to a DAC, a processing module (e.g., a rollover processor) operates to divide, partition, etc. the codeword into different respective sub-codewords as may be provided to two or more DAC's. Adaptation with respect to differently generated sub-codewords with respect to different respective codewords may be made in terms of any one or more of a variety of characteristics, including sub-codeword width (e.g., the number of bits included within a sub-codeword), quantization steps, etc. Moreover, such adaptation may be in consideration of any one or more local and/or remote operating characteristics of one or more devices, communication links, etc. within a communication system or network. Different respective sub-codewords undergo processing by different respective DAC's in generating respective analog signals for combination in generating a final or output analog signal. | 07-19-2012 |
20120183031 | Distortion and aliasing reduction for digital to analog conversion - Distortion and aliasing reduction for digital to analog conversion. Synthesis of one or more distortion terms made based on a digital signal (e.g., one or more digital codewords) is performed in accordance with digital to analog conversion. The one or more distortion terms may correspond to aliased higher-order harmonics, distortion, nonlinearities, clipping, etc. Such distortion terms may be known a priori, such as based upon particular characteristics of a given device, operational history, etc. Alternatively, such distortion terms may be determined based upon operation of a device and/or based upon an analog signal generated from the analog to conversion process. For example, frequency selective measurements made based on an analog signal generated from the digital to analog conversion may be used for determination of and/or adaptation of the one or more distortion terms. One or more DACs may be employed within various architectures operative to perform digital to analog conversion. | 07-19-2012 |
20120183082 | Distortion and aliasing reduction for digital to analog conversion - Distortion and aliasing reduction for digital to analog conversion. Synthesis of one or more distortion terms made based on a digital signal (e.g., one or more digital codewords) is performed in accordance with digital to analog conversion. The one or more distortion terms may correspond to aliased higher-order harmonics, distortion, nonlinearities, clipping, etc. Such distortion terms may be known a priori, such as based upon particular characteristics of a given device, operational history, etc. Alternatively, such distortion terms may be determined based upon operation of a device and/or based upon an analog signal generated from the analog to conversion process. For example, frequency selective measurements made based on an analog signal generated from the digital to analog conversion may be used for determination of and/or adaptation of the one or more distortion terms. One or more DACs may be employed within various architectures operative to perform digital to analog conversion. | 07-19-2012 |
20120183110 | Distortion and aliasing reduction for digital to analog conversion - Distortion and aliasing reduction for digital to analog conversion. Synthesis of one or more distortion terms made based on a digital signal (e.g., one or more digital codewords) is performed in accordance with digital to analog conversion. The one or more distortion terms may correspond to aliased higher-order harmonics, distortion, nonlinearities, clipping, etc. Such distortion terms may be known a priori, such as based upon particular characteristics of a given device, operational history, etc. Alternatively, such distortion terms may be determined based upon operation of a device and/or based upon an analog signal generated from the analog to conversion process. For example, frequency selective measurements made based on an analog signal generated from the digital to analog conversion may be used for determination of and/or adaptation of the one or more distortion terms. One or more DACs may be employed within various architectures operative to perform digital to analog conversion. | 07-19-2012 |
20130222161 | Distortion and aliasing reduction for digital to analog conversion - Distortion and aliasing reduction for digital to analog conversion. Synthesis of one or more distortion terms made based on a digital signal (e.g., one or more digital codewords) is performed in accordance with digital to analog conversion. The one or more distortion terms may correspond to aliased higher-order harmonics, distortion, nonlinearities, clipping, etc. Such distortion terms may be known a priori, such as based upon particular characteristics of a given device, operational history, etc. Alternatively, such distortion terms may be determined based upon operation of a device and/or based upon an analog signal generated from the analog to conversion process. For example, frequency selective measurements made based on an analog signal generated from the digital to analog conversion may be used for determination of and/or adaptation of the one or more distortion terms. One or more DACs may be employed within various architectures operative to perform digital to analog conversion. | 08-29-2013 |
20130230130 | DISTORTION AND ALIASING REDUCTION FOR DIGITAL TO ANALOG CONVERSION - Distortion and aliasing reduction for digital to analog conversion. Synthesis of one or more distortion terms made based on a digital signal (e.g., one or more digital codewords) is performed in accordance with digital to analog conversion. The one or more distortion terms may correspond to aliased higher-order harmonics, distortion, nonlinearities, clipping, etc. Such distortion terms may be known a priori, such as based upon particular characteristics of a given device, operational history, etc. Alternatively, such distortion terms may be determined based upon operation of a device and/or based upon an analog signal generated from the analog to conversion process. For example, frequency selective measurements made based on an analog signal generated from the digital to analog conversion may be used for determination of and/or adaptation of the one or more distortion terms. One or more DACs may be employed within various architectures operative to perform digital to analog conversion. | 09-05-2013 |
20140059632 | Integrated Cable Modem - The present invention is an integrated cable modem tuner. In one embodiment, the upstream path and the downstream path are integrated on a common semiconductor substrate. The down-stream path can include a TV tuner and digital receiver portion that is integrated on a common semiconductor substrate with the power amplifier of the upstream path. In another embodiment, the TV tuner is implemented on a first semiconductor substrate and the digital receiver portion and the power amplifier are configured on a second semiconductor substrate. However, the two substrates are mounted on a common carrier so that the cable modem appears to be a single chip configuration to the user. | 02-27-2014 |
20140086128 | Power savings within communication systems - A communication device is implemented to perform signal processing based on different dynamic ranges at different times. The device can operate with a first, relatively larger dynamic range during normal operations, and with a second, relatively smaller dynamic range during reduced power or sleep mode operations. The relatively smaller dynamic range may have a relatively higher noise floor than the larger dynamic range. Generally, any desired number of different dynamic ranges may be used at different times and based on different operating conditions. The communication device can include functionality associated with two or more transceivers to support communications based on two or more power modes (e.g., a full power mode, a reduced power mode or a sleep mode, etc.). The communication device may alternatively include two or more separate transceivers to support such communications. An unused transceiver or transceiver functionality may be turned off to provide power savings. | 03-27-2014 |