Patent application number | Description | Published |
20090085134 | Wafer-level image sensor module, method of manufacturing the same, and camera module - Provided is a wafer-level image sensor module including a wafer; an image sensor mounted on the wafer; a transparent member installed above the top surface of the wafer so as to seal the image sensor; a plurality of vias formed in the wafer so as to be positioned outside the transparent member; a plurality of upper pads formed on the upper ends of the respective vias; an encapsulation portion formed on the top surface of the wafer so as to be positioned outside the transparent member; and a plurality of external connection members that are electrically connected to the lower ends of the respective vias. | 04-02-2009 |
20100327426 | Semiconductor chip package and method of manufacturing the same - Provided are a semiconductor chip package and a method of manufacturing the same. The semiconductor chip package includes a semiconductor chip including a first face having a chip pad, a second face facing the first face, and a side face connecting the first and second faces, a first lamination layer covering the second face and a portion of the side face, a second lamination layer disposed on a top surface of the first lamination layer and forming a gap having a predetermined distance from the side face, and a redistribution pattern disposed on the first face and electrically connected to the chip pad. The semiconductor package and the method of manufacturing the same achieve a high process yield and reliability. | 12-30-2010 |
20110012220 | Wafer-level image sensor module, method of manufacturing the same and camera module - A wafer-level image sensor module including: a wafer having an image sensor and a plurality of upper pads provided thereon, the wafer having an inclined surface on either side thereof; a transparent member installed above the top surface of the wafer so as to seal the image sensor; a plurality of lead portions having one ends connected to the respective upper pads, the lead portions being formed to extend to the bottom surface of the wafer along the inclined surface of the wafer; an encapsulation portion formed on the top surface of the wafer so as to be positioned outside the transparent member; and a plurality of external connection members that are electrically connected to the other ends of the respective lead portions | 01-20-2011 |
20110045668 | Method of manufacturing wafer level device package - There is provided a method of manufacturing a wafer level device package, the method including: forming a conductive pad on at least one area of a substrate; forming a first insulation layer on the substrate, the first insulation layer having an opening allowing the conductive pad to be exposed; forming a wiring layer connected to the conductive pad on the first insulation layer; forming a conductive diffusion barrier layer on the wiring layer to seal the wiring layer; forming a second insulation layer on the diffusion barrier layer, the second insulation layer having a contact hole allowing a part of diffusion barrier layer to be exposed; and forming a bump pad in the contact hole. This method allows for a reduction in processing time and costs by substituting a simple electroless plating process for a complicated photolithography process in the formation of the bump pad and the diffusion barrier layer. | 02-24-2011 |
20110061911 | Interposer and method for manufacturing the same - An interposer includes: an insulation plate where a via is formed, the insulation plate including a resin or a ceramic; a first upper redistribution layer electrically connected to the via along a circuit pattern designed on the top surface of the insulation plate; a first upper protection layer laminated to expose a portion of the first upper redistribution layer and protecting the first upper redistribution layer; a second upper redistribution layer electrically connected to the first upper redistribution layer and laminated along a designed circuit pattern designed; a second upper protection layer laminated to expose a portion of the second upper redistribution layer and protecting the second upper redistribution layer; and an under bump metallization (UBM) formed at the exposed portion of the second upper redistribution layer. | 03-17-2011 |
20110062533 | Device package substrate and method of manufacturing the same - A device package substrate includes: a substrate having a cavity formed on a top surface thereof, the cavity having a chip mounting region; a first interconnection layer formed to extend to the inside of the cavity; a second interconnection layer formed to be spaced apart from the first interconnection layer; a chip positioned in the chip mounting region so as to be connected to the first and second interconnection layers; an insulating layer formed to cover the first and second interconnection layers and the chip and having a contact hole exposing a part of the second interconnection layer; and a bump pad formed in the contact hole so as to be connected to external elements. | 03-17-2011 |
20110108993 | Semiconductor package and manufacturing method thereof - There is provided a semiconductor package including: a circuit board having a receiving space formed therein; a semiconductor chip inserted into the receiving space of the circuit board; and an electrode pattern portion having a pattern shape on one surface of the semiconductor chip, and directly contacting a via portion of the circuit board so as to be electrically connected thereto. | 05-12-2011 |
20110163437 | Semiconductor package and method of manufacturing the same - There is provided a semiconductor package. A semiconductor package according to an aspect of the invention may include a core part having a semiconductor chip mounted within a receiving space therein; an insulation part provided on one surface of the core part; and a via part provided by filling a hole-processed surface formed simultaneously through the insulation part and a passivation layer for protecting an electrode pattern part on the semiconductor chip. | 07-07-2011 |
20110176285 | Interconnection structure, interposer, semiconductor package, and method of manufacturing interconnection structure - There is provided an interconnection structure. An interconnection structure according to an aspect of the invention may include: a plurality of side portions provided on one surface of a substrate part and a plurality of cavities located between the side portions and located further inward than the side portions; and electrode pattern portions provided on surfaces of the side portions and the cavities. | 07-21-2011 |
20110198749 | Semiconductor chip package and method of manufacturing the same - Provided are a semiconductor chip package and a method of manufacturing the same. The semiconductor chip package includes a semiconductor chip comprising a chip pad, and a rerouting layer disposed on the semiconductor chip and including a metal interconnection electrically connected to the chip pad and a partial oxidation region formed by the oxidation of metal and insulating the metal interconnection. | 08-18-2011 |
20110248408 | Package substrate and fabricating method thereof - There are provided a package substrate and a method fabricating thereof. The package substrate includes: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filled in the through-hole; and at least one electronic device connected to the via. Accordingly, a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing a component mounting density, and a method fabricating thereof may be provided. | 10-13-2011 |
20110269413 | Circuit board and method for manufacturing the same - There are provided a circuit board and a method for manufacturing the same. The circuit board according to the present invention includes: a first wiring pattern that is formed on one surface of the board; a second wiring pattern that is formed on the other surface of the board; an RF transmitter that is formed on one surface of the board and is connected to the first wiring pattern; and an RF receiver that is formed on the other surface of the board to be paired with the RF transmitter and is connected to the second wiring pattern, wherein the first wiring pattern and the second wiring pattern are electrically connected to each other by wireless communication from the RF transmitter to the RF receiver. | 11-03-2011 |
20120261816 | DEVICE PACKAGE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A device package substrate includes: a substrate having a cavity formed on a top surface thereof, the cavity having a chip mounting region; a first interconnection layer formed to extend to the inside of the cavity; a second interconnection layer formed to be spaced apart from the first interconnection layer; a chip positioned in the chip mounting region so as to be connected to the first and second interconnection layers; an insulating layer formed to cover the first and second interconnection layers and the chip and having a contact hole exposing a part of the second interconnection layer; and a bump pad formed in the contact hole so as to be connected to external elements. | 10-18-2012 |
20120295404 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A method of manufacturing a semiconductor package, the method including: forming an insulating layer on a board; forming an electrode pattern portion by redistribution plating in order to make a circuit connection on the insulating layer; manufacturing a semiconductor chip by forming a protecting portion on the electrode pattern portion such that a portion of the electrode pattern portion is exposed; and mounting the semiconductor chip on a receiving space of a circuit board and electrically connecting the semiconductor chip to the circuit board. | 11-22-2012 |
20130029031 | METHOD FOR MANUFACTURING INTERPOSER - A method for manufacturing an interposer includes forming a via hole in an insulation plate including a resin or a ceramic; simultaneously forming resists for a first upper redistribution layer on the top surface of the insulation plate, and a resistor for a lower redistribution layer on the bottom surface of the insulation plate; plating copper to fill the via hole and simultaneously forming the first upper redistribution layer and the lower redistribution layer along a designed circuit pattern; and forming a first upper protection layer and a lower protection layer to expose a portion of the first upper redistribution layer and a portion of the lower redistribution layer. | 01-31-2013 |
20140051212 | METHOD OF FABRICATING A PACKAGE SUBSTRATE - A method of fabricating a package substrate, includes forming a cavity in at least one region of an upper surface of a wafer, the cavity including a chip mounting region, forming a through-hole penetrating through the wafer and a via filling the through-hole, forming a first wiring layer and a second wiring layer spaced apart from the first wiring layer, which are extended into the cavity, and mounting a chip in the cavity to be connected to the first wiring layer and the second wiring layer. | 02-20-2014 |
20140124258 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board includes: a core layer having a first circuit wiring layer formed on one surface or both surfaces thereof; an insulating layer laminated, as at least one layer, on one surface or both surfaces of the core layer; and a second circuit wiring layer formed on one surface of the insulating layer, wherein a conductive core is included in upper and lower insulating layers contacting the second circuit wiring layer requiring an electromagnetic wave shielding, or the conductive core is included in the insulating layer or the core layer contacting the first circuit wiring layer requiring the electromagnetic wave shielding. | 05-08-2014 |
20140174809 | CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a circuit board including: a core layer including a via hole; a metal film covering an inner wall of the via hole; a circuit pattern connected to the metal film on the core layer; and a plug surrounded by the metal film in the via hole and having a thickness thinner than a thickness of the core layer. | 06-26-2014 |
20140176278 | INDUCTOR AND MANUFACTURING METHOD THEREOF - There is provided an inductor, including a circuit board having an input and output terminal formed on a lower surface thereof, a connection pad formed on an upper surface thereof, and a via electrically connecting the input and output terminal and the connection pad, a coil having both ends joined to the connection pad and wound in a circular or a polygonal spiral shape in a longitudinal direction of the circuit board so as to have one or more turns, and a body stacked on the circuit board such that the coil and the connection pad are embedded therein. | 06-26-2014 |
Patent application number | Description | Published |
20090060050 | Method for encoding and decoding video signal - Disclosed is a method for encoding a decoding a video signal. In the procedure of encoding the video signal, when a frame temporarily simultaneous with a frame including a macro block of an enhanced layer which will obtain a prediction video does not exist in a base layer, the macro block is encoded based on difference values of residual data using corresponding residual blocks in a past frame and a future frame of the base layer which are residual data corresponding to image difference values and using a residual block for the macro block of the enhanced layer. In another embodiment, the macro block is encoded based on difference values of residual data using corresponding residual blocks in a past frame and a future frame of the enhanced layer and the residual block for the macro block. Accordingly, a residual prediction mode is applied for a macro block of an enhanced layer even if a frame temporally simultaneous with a frame of the enhanced layer does not exist in a base layer, thereby improve coding efficiency. | 03-05-2009 |
20090190658 | METHOD FOR ENCODING AND DECODING VIDEO SIGNAL - Disclosed is a method for encoding a decoding a video signal. In the procedure of encoding the video signal, when a frame temporarily simultaneous with a frame including a macro block of an enhanced layer which will obtain a prediction video does not exist in a base layer, the macro block is encoded based on difference values of residual data using corresponding residual blocks in a past frame and a future frame of the base layer which are residual data corresponding to image difference values and using a residual block for the macro block of the enhanced layer. In another embodiment, the macro block is encoded based on difference values of residual data using corresponding residual blocks in a past frame and a future frame of the enhanced layer and the residual block for the macro block. Accordingly, a residual prediction mode is applied for a macro block of an enhanced layer even if a frame temporally simultaneous with a frame of the enhanced layer does not exist in a base layer, thereby improve coding efficiency. | 07-30-2009 |
20090190669 | METHOD FOR ENCODING AND DECODING VIDEO SIGNAL - Disclosed is a method for encoding a decoding a video signal. In the procedure of encoding the video signal, when a frame temporarily simultaneous with a frame including a macro block of an enhanced layer which will obtain a prediction video does not exist in a base layer, the macro block is encoded based on difference values of residual data using corresponding residual blocks in a past frame and a future frame of the base layer which are residual data corresponding to image difference values and using a residual block for the macro block of the enhanced layer. In another embodiment, the macro block is encoded based on difference values of residual data using corresponding residual blocks in a past frame and a future frame of the enhanced layer and the residual block for the macro block. Accordingly, a residual prediction mode is applied for a macro block of an enhanced layer even if a frame temporally simultaneous with a frame of the enhanced layer does not exist in a base layer, thereby improve coding efficiency. | 07-30-2009 |
20090190844 | METHOD FOR SCALABLY ENCODING AND DECODING VIDEO SIGNAL - Disclosed is a method for scalably encoding and decoding a video signal. The video signal is encoded through an inter-layer prediction scheme based on a data stream of a base layer encoded with ×¼ resolution. The inter-layer prediction scheme applied between the enhanced layer and the base layer representing ×4 resolution difference includes a motion prediction scheme for predicting motion and dividing a macro block of the enhanced layer based on division information, mode information, and/or mode information of a block of the base layer. Thus, the inter-layer prediction scheme is applied between layers representing ×4 resolution difference, thereby improving a coding efficiency. | 07-30-2009 |
20100208799 | Method for decoding image block - Disclosed is a method for decoding an image block. The method comprises a step of decoding an image block of a first layer based on a corresponding block of a second layer encoded with an intra mode, wherein a first area is formed with pixels, which are adjacent to a corner pixel positioned in the corresponding block in a diagonal direction and extend in vertical and horizontal directions away from the corresponding block, and data are padded in the first area based on the corner pixel and the pixels positioned in the first area and at least one of first and second blocks, which are simultaneously adjacent to the corresponding block and encoded with the intra mode. Accordingly, a reference block required when a macro block is encoded in an intra base mode or when a macro block encoded in the intra base mode is decoded has more precise values, thereby enabling improvement of a coding efficiency. | 08-19-2010 |
20110235714 | Method and device for encoding/decoding video signals using base layer - The present invention relates to encoding and decoding a video signal by motion compensated temporal filtering. In one embodiment, a first sequence of frames are decoded by inverse motion compensated temporal filtering by selectively adding to a first image block in the first sequence image information, the image information being based on at least one of ( | 09-29-2011 |
20150023428 | METHOD AND DEVICE FOR ENCODING/DECODING VIDEO SIGNALS USING BASE LAYER - The present invention relates to encoding and decoding a video signal by motion compensated temporal filtering. In one embodiment, a first sequence of frames are decoded by inverse motion compensated temporal filtering by selectively adding to a first image block in the first sequence image information, the image information being based on at least one of (1) a second image block from the first sequence and (2) a third image block from an auxiliary sequence of frames. | 01-22-2015 |
Patent application number | Description | Published |
20090085204 | Wafer-level package and method of manufacturing the same - Provided is a wafer-level package including a wafer-level semiconductor chip having a plurality of integrated circuits (ICs) and pads formed on the top surface thereof; a molding material of which the outer portion is supported by the top surface of the semiconductor chip such that a cavity is provided on the semiconductor chip; and a conducive member filled in a plurality of vias which are formed in arbitrary positions of the molding material so as to pass through the molding material, the conductive member being connected to the pads. | 04-02-2009 |
20090087951 | Method of manufacturing wafer level package - A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased. | 04-02-2009 |
20090253259 | Solder ball attachment jig and method for manufacturing semiconductor device using the same - Disclosed are a solder attachment jig and a method of manufacturing a semiconductor device using the same. The solder ball attachment jig, which arranges a solder ball to be aligned with a conductive post of a semiconductor wafer, can include a body and a receiving hole, which is formed on the body to hold the solder ball. Internal walls of the receiving hole that face each other are symmetrically inclined. Using the solder ball attachment jig in accordance with an embodiment of the present invention, the alignment of the solder ball can be improved while reducing the cost and simplifying the processes. | 10-08-2009 |
20100117218 | Stacked wafer level package and method of manufacturing the same - The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost. | 05-13-2010 |
20100144152 | Method of manufacturing semiconductor package - The present invention relates to a method of manufacturing a semiconductor package capable of simplifying a process and remarkably reducing a production cost by including the steps of: preparing a different bonded panel including at least one metal layer; forming a pad unit electrically connected to the metal layer; mounting a semiconductor chip over the different bonded panel to be electrically connected to the pad unit; sealing the semiconductor chip; forming a rearrangement wiring layer by etching the metal layer; and forming an external connection unit electrically connected to the rearrangement wiring layer. | 06-10-2010 |
20100149770 | Semiconductor stack package - The present invention relates to a semiconductor stack package including: a printed circuit board; a first semiconductor chip mounted on the printed circuit board; a second semiconductor chip mounted on the printed circuit board in parallel with the first semiconductor chip; a first rearrangement wiring layer positioned on the first semiconductor chip; a second rearrangement wiring layer which constitutes one circuit together with the first rearrangement wiring layer and is positioned on the second semiconductor chip; and a third semiconductor chip which is electrically connected to the first and second rearrangement wiring layers and of which both ends are separately positioned on the first and second semiconductor chips. | 06-17-2010 |
20120073861 | PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - A printed circuit board and a manufacturing method of the printed circuit board are disclosed. The printed circuit board includes: a first insulation layer having a first pattern formed thereon; a first trench caved in one surface of the first insulation layer along at least a portion of the first pattern; and a second insulation layer stacked on one surface of the first insulation layer so as to cover the first pattern. The first trench is filled by the second insulation layer. | 03-29-2012 |
20140345916 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board according to a preferred embodiment of the present invention includes a base substrate; a through via formed to penetrate through the base substrate; and circuit patterns formed on one side and the other side of the base substrate and formed to be thinner than an inner wall of the through via. | 11-27-2014 |
20150028686 | COIL TYPE UNIT FOR WIRELESS POWER TRANSMISSION, WIRELESS POWER TRANSMISSION DEVICE, ELECTRONIC DEVICE AND MANUFACTURING METHOD OF COIL TYPE UNIT FOR WIRELESS POWER TRANSMISSION - The present invention relates to a coil type unit for wireless power transmission, a wireless power transmission device, an electronic device, and a manufacturing method of a coil type unit for wireless power transmission. A coil type unit for wireless power transmission according to the present invention includes a coil pattern in the form of a wiring pattern; a magnetic portion having the coil pattern attached to one surface thereof; and an adhesive portion interposed between the magnetic portion and the coil pattern to bond the magnetic portion and the coil pattern, wherein the magnetic portion is formed by laminating one or more conductive sheets with one or more magnetic sheets and integrally firing the laminated sheets, and the magnetic portion has conductive holes in the position, where both ends of the coil pattern are disposed, to electrically connect the both ends of the coil pattern and the conductive sheet. | 01-29-2015 |
20150061400 | COIL TYPE UNIT FOR WIRELESS POWER TRANSMISSION, WIRELESS POWER TRANSMISSION DEVICE, ELECTRONIC DEVICE AND MANUFACTURING METHOD OF COIL TYPE UNIT FOR WIRELESS POWER TRANSMISSION - The present invention relates to a coil type unit for wireless power transmission, a wireless power transmission device, an electronic device, and a manufacturing method of a coil type unit for wireless power transmission. A coil type unit for wireless power transmission of the present invention includes a coil portion having a coil pattern on a substrate; a magnetic portion having the coil portion attached to one surface thereof and a conductive pattern formed thereon; an adhesive portion interposed between the magnetic portion and the coil portion to mutually bond the magnetic portion and the coil portion; and a conductive hole for electrically connecting the coil pattern and the conductive pattern, wherein the adhesive portion is formed on one surface of the magnetic portion having the conductive pattern thereon while being formed in an area other than the area in which the conductive pattern is formed. | 03-05-2015 |
20150076919 | COIL TYPE UNIT FOR WIRELESS POWER TRANSMISSION, WIRELESS POWER TRANSMISSION DEVICE, ELECTRONIC DEVICE AND MANUFACTURING METHOD OF COIL TYPE UNIT FOR WIRELESS POWER TRANSMISSION - The present invention relates to a coil type unit for wireless power transmission, a wireless power transmission device, an electronic device, and a manufacturing method of a coil type unit for wireless power transmission. | 03-19-2015 |
20150083480 | INTERPOSER BOARD AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are an interposer board and a method of manufacturing the same. According to a preferred embodiment of the present invention, the interposer substrate may include: a base substrate; a circuit pattern formed on the base substrate; and a through via formed to penetrate through the base substrate and have a height lower than that of the circuit pattern. | 03-26-2015 |
Patent application number | Description | Published |
20100102426 | Dual face package and method of manufacturing the same - Disclosed herein is a dual face package and a method of manufacturing the same. The dual face package includes a semiconductor substrate including a through-electrode connected to a die pad disposed on one side of the semiconductor substrate, and a lower redistribution layer disposed on another side thereof and connected to the through-electrode, an insulating layer including a post electrode connected to the through-electrode, and an upper redistribution layer disposed on one side thereof and connected to the post electrode, and an adhesive layer disposed on the one side of the semiconductor substrate so as to attach the insulating layer to the semiconductor substrate such that the through-electrode is connected to the post electrode. The dual face package is produced by a simple process and is applicable to a large diameter wafer level package. | 04-29-2010 |
20110129994 | Method of manufacturing a dual face package - A method of manufacturing a dual face package, including: preparing an upper substrate composed of an insulating layer including a post via-hole; forming a filled electrode in a semiconductor substrate, the filled electrode being connected to a die pad; applying an adhesive layer on one side of the semiconductor substrate including the filled electrode, and attaching the upper substrate to the semiconductor substrate; cutting another side of the semiconductor substrate in a thickness direction, thus making the filled electrode into a through-electrode; and forming a post electrode in the post via-hole, forming an upper redistribution layer connected to the post electrode of the semiconductor substrate, and forming a lower redistribution layer connected to the through-electrode on the other side of the semiconductor substrate. | 06-02-2011 |
20110156241 | PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME - Disclosed herein are a package substrate and a method of fabricating the same. The package substrate includes a base part that includes a chip, a mold part surrounding the chip, and a connection unit formed inside the mold part to connect the chip to a terminal part formed on the outer surface of the mold part, and a buildup layer that is formed on one surface of the base part on which the terminal part is formed, including the side surfaces of the base part, but includes a circuit layer connected to the terminal part, thereby making it possible to minimize stress applied to chips during a buildup process and easily replace malfunctioning chips. | 06-30-2011 |
20120012378 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - Disclosed is a printed circuit board, including a base member, an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened, a circuit layer formed on the insulating layer, and a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member. A method of manufacturing the printed circuit board is also provided. | 01-19-2012 |
20120018897 | SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor module, including: a substrate including wiring patterns formed on both sides thereof; a first device mounted on the substrate; a first molding layer made of a molding material, surrounding the first device and including via holes formed therein to interconnect with the wiring pattern formed on one side of the substrate; and a second device mounted on the first molding layer and electrically connected with the wiring pattern formed on one side of the substrate through the via holes formed in the first molding layer. | 01-26-2012 |
20120073870 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - Disclosed is a printed circuit board, including a base member, an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened, a circuit layer formed on the insulating layer, and a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member. A method of manufacturing the printed circuit board is also provided. | 03-29-2012 |
20120084977 | METHOD OF MANUFACTURING BLOCK MODULE - Disclosed herein is a method of manufacturing a block module including: mounting an electronic part on a base substrate on which a ground terminal is formed; forming a lead frame to extend to the outside of the base substrate from the ground terminal; connecting a flexible printed circuit to a circuit layer on the base substrate; forming a mold to surround the base substrate; cutting the lead frame and exposing the cut surface of the lead frame to the outside of the mold; and forming a metal coating layer connected to the lead frame on the mold, whereby the metal coating layer is formed to surround the mold to interrupt the electromagnetic waves and the metal coating layer is connected to the ground terminal by the lead frame to make the process simple. | 04-12-2012 |
20130199833 | CIRCUIT BOARD - Disclosed herein is a circuit board including: a base substrate including a via for power and a via pad for power connected to the via for power; and an insulating layer formed on the base substrate and including a dummy pattern formed in a region facing the via pad for power. | 08-08-2013 |
20140003770 | OPTICAL CONNECTOR AND OPTICAL MODULE HAVING THE SAME | 01-02-2014 |
Patent application number | Description | Published |
20090166859 | Semiconductor device and method of manufacturing the same - Provided is a semiconductor device including a wafer having an electrode pad; an insulating layer that is formed on the wafer and has an exposure hole formed in one side thereof, the exposure layer exposing the electrode pad, and a support post formed in the other side, the support post having a buffer groove; a redistribution layer that is formed on the top surface of the insulating layer and has one end connected to the electrode pad and the other end extending to the support post; an encapsulation layer that is formed on the redistribution layer and the insulating layer and exposes the redistribution layer formed on the support post; and a solder bump that is provided on the exposed portion of the redistribution layer. | 07-02-2009 |
20110309501 | SEMICONDUCTOR PACKAGE MODULE AND ELECTRIC CIRCUIT ASSEMBLY WITH THE SAME - Disclosed herein is a semiconductor package module. The semiconductor package module includes a circuit substrate having an external connection pattern; electronic components mounted on the circuit substrate; a molding structure having a structure surrounding the circuit substrate so as to seal the electronic components from the external environment; and an external connection structure of which one portion is connected to the external connection pattern and the other portion is exposed to the outside of the molding structure. | 12-22-2011 |
20130075144 | PACKAGE SUBSTRATE WITH MESH PATTERN AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a package substrate and a method for manufacturing the same. According to an exemplary embodiment, there is provided a package substrate with a mesh pattern, including: a plurality of bonding pads forming sections connected with the outside; an insulating layer formed below the plurality of bonding pads; and a metallic layer placed below the insulating layer and having the mesh pattern in at least a partial area thereof and capacitance is provided by a combination of the mesh pattern and the insulating layer that infiltrates into a space for the mesh pattern. Further, there is provided a method for manufacturing the package substrate with the mesh pattern. | 03-28-2013 |
20130320561 | PLUG VIA STACKED STRUCTURE, STACKED SUBSTRATE HAVING VIA STACKED STRUCTURE AND MANUFACTURING METHOD THEREOF - Disclosed herein is a plug via stacked structure including: a through hole plating layer plated on a through hole inner wall and around top and bottom of a through hole at thickness t; a via plug filled in an inner space of the through hole plating layer; a circuit pattern formed over the top and bottom of the through hole plating layer and the via plug and making a thickness t′ formed on the through hole plating layer thicker than a thickness t; and a stacked conductive via filled in a via hole formed on the top of the through hole and formed at thickness α from a top of the circuit pattern, wherein T≦t″+α is satisfied, T represents a sum of the thicknesses t and t′ and t″ is a thickness of a portion of the circuit pattern formed on the via plug. | 12-05-2013 |
20140251657 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - Embodiments of the invention provide a printed circuit board, including a base member, an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened, a circuit layer formed on the insulating layer, and a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member. A method of manufacturing the printed circuit board is also provided. | 09-11-2014 |
20150048985 | ANTENNA MODULE FOR NEAR FIELD COMMUNICATION - Embodiments of the invention provide an antenna module for NFC. According to at least one embodiment, the antenna module includes an antenna sheet patterned with a loop coil of a conductive metal material, a magnetic shielding sheet comprising a metal sheet, which is embedded in a magnetic sheet, and an adhesive film interposed between the antenna sheet and the magnetic shielding sheet. | 02-19-2015 |