Patent application number | Description | Published |
20080265305 | INTEGRATED CIRCUITS WITH SUBSTRATE PROTRUSIONS, INCLUDING (BUT NOT LIMITED TO) FLOATING GATE MEMORIES - A floating gate memory cell's channel region ( | 10-30-2008 |
20080266949 | INTEGRATED CIRCUITS WITH SUBSTRATE PROTRUSIONS, INCLUDING (BUT NOT LIMITED TO) FLOATING GATE MEMORIES - A floating gate memory cell's channel region ( | 10-30-2008 |
20080291723 | SOURCE BIASING OF NOR-TYPE FLASH ARRAY WITH DYNAMICALLY VARIABLE SOURCE RESISTANCE - A dynamically variable source resistance is provided for each sector of a NOR-type Flash memory device. The variable source resistance of a given sector is set to a relatively low value (i.e., close to zero) during read operations. The variable source resistance is set to a relatively high impedance value (i.e., close to being an open circuit) during flash erase operations. The variable source resistance is set to a first intermediate resistance value at least during soft-programming where the first intermediate resistance value is one that raises V | 11-27-2008 |
20090085069 | NAND-type Flash Array with Reduced Inter-cell Coupling Resistance - In a NAND-type nonvolatile reprogrammable memory array, inter-cell coupling resistance between adjoining memory cells is reducing by forming metal silicide insets embedded in the diffusion zone of the inter-cell coupling region. The diffusion zone includes a shallow implant region and a deep implant region. In one embodiment, the shallow implant region defines shallow source/drain regions for floating gate transistors of the memory cells. The size of the metal silicide insets are controlled to not compromise isolation PN junctions defined by the shallow and deep implant region. In one embodiment, the metal silicide insets include nickel. | 04-02-2009 |
20090096013 | NON-VOLATILE MEMORY DEVICES WITH CHARGE STORAGE REGIONS - A memory device includes a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, and a control gate. Applying a positive bias to the control gate, the select gate and the source of the device injects negative charges from a channel region of a substrate by hot electron injection through the tunneling dielectric layer at a location near a gap between the select gate and the control gate into the charge storage layer to store negative charges in the charge storage layer. Applying a negative bias is to the control gates directly tunnels positive charges from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to store positive charges in the charge storage layer. | 04-16-2009 |
20090101961 | MEMORY DEVICES WITH SPLIT GATE AND BLOCKING LAYER - The present disclosure provides a memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, a tantalum-nitride layer, and a control gate layer. When a positive bias is applied to the control gate and the select gate, negative charges are injected from a channel region of a substrate through the tunneling dielectric layer and into the charge storage layer to thereby store the negative charges in the charge storage layer. When a negative bias is applied to the control gate, negative charges are tunneled from the charge storage layer to the channel region of the substrate through the tunneling dielectric layer. | 04-23-2009 |
20090159957 | NONVOLATILE MEMORIES WITH LATERALLY RECESSED CHARGE-TRAPPING DIELECTRIC - Charge-trapping dielectric ( | 06-25-2009 |
20090184359 | Split-gate non-volatile memory devices having nitride tunneling layers - A memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a first trap-free-nitride layer formed on a channel region of a substrate, a second nitride layer formed on the first nitride layer, an oxide layer formed on the second nitride layer, a control gate formed on the high-K oxide layer, and a poly spacer as the select gate formed adjacent to the control gate. | 07-23-2009 |
20090251972 | NONVOLATILE MEMORY ARRAYS WITH CHARGE TRAPPING DIELECTRIC AND WITH NON-DIELECTRIC NANODOTS - Charge-trapping dielectric ( | 10-08-2009 |
20090256221 | METHOD FOR MAKING VERY SMALL ISOLATED DOTS ON SUBSTRATES - A method for forming very small isolated dots of a target material, e.g., a ferromagnetic material or phase change material, on a substrate includes providing a substrate having a layer of the target material disposed on a surface thereof, etching the layer of target material so as to form a plurality of lines of the material on the surface of the substrate, and etching the lines of the target material so as to form a rectangular matrix of substantially similar, very small isolated dots of the target material on the substrate. By the successive formation of orthogonally intersecting linear patterns on the substrate, including the formation and use of “hard” etch masks, spacer approach and selective etching techniques, the method enables very small (<65 nm) isolated dots of the target material to be formed on the substrate reliably and with the use of conventional 193 nm wavelength photolithographic methods and apparatus. | 10-15-2009 |
20090321806 | NONVOLATILE MEMORY WITH FLOATING GATES WITH UPWARD PROTRUSIONS - Substrate isolation regions ( | 12-31-2009 |
20100323511 | NONVOLATILE MEMORIES WITH LATERALLY RECESSED CHARGE-TRAPPING DIELECTRIC - Charge-trapping dielectric ( | 12-23-2010 |
20110309421 | ONE-TIME PROGRAMMABLE MEMORY AND METHOD FOR MAKING THE SAME - A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate. | 12-22-2011 |
20130161761 | ONE-TIME PROGRAMMABLE MEMORY AND METHOD FOR MAKING THE SAME - A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate. | 06-27-2013 |
20140001429 | HETEROJUNCTION OXIDE MEMORY DEVICE WITH BARRIER LAYER | 01-02-2014 |