Wu, Yunlin County
Cheng-Han Wu, Yunlin County TW
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20120029888 | TOPOGRAPHY SHAPING APPARATUS FOR FORMING SURFACES OF LOW FRICTION COEFFICIENT - The topography shaping apparatus for forming surfaces of low friction coefficient includes a data-input element, a computing element, and a shaping element. The data-input element is adapted to receive an action length, a fractal dimension value, and a fractal roughness parameter of a desired surface. The computing element connects with the data-input element to obtain a surface topography function from the data received by the data-input element. The shaping element connects with the computing element for processing a target surface to have a sectional outline matching the surface topography function to become the desired surface. | 02-02-2012 |
Chien-Cheng Wu, Yunlin County TW
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20100138217 | METHOD FOR CONSTRUCTING CHINESE DICTIONARY AND APPARATUS AND STORAGE MEDIA USING THE SAME - A method for constructing a Chinese dictionary is disclosed, including determining a probability for nominalization of a Chinese term with a given collocation term according to a determination rule and the correlation between the Chinese term and its corresponding collocations, wherein the Chinese term is determined to be a verb part-of-speech. The method further includes modifying the verb part-of-speech of the Chinese term with the given collocation term to an appropriate part-of-speech when the probability for nominalization of the Chinese term with the given collocation term is higher than a predetermined value, and storing the correlation between the Chinese term, the given collocation term and the appropriate part-of-speech in a storage device. | 06-03-2010 |
Chih-Pin Wu, Yunlin County TW
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20150039923 | METHOD OF CONTROLLING SDIO DEVICE AND RELATED SDIO SYSTEM AND SDIO DEVICE - Described in embodiments herein are techniques for placing a secure digital input output (SDIO) device in a sleep mode and waking up the SDIO device from the sleep mode. In accordance with an embodiment, a method of controlling the SDIO device comprising: writing a control value into a register of the SDIO device; allowing the SDIO device to switch to a first operation mode based on the control value written into the register; sending a first signal to the SDIO device through a first data terminal of the SDIO device; and allowing the SDIO device to switch to a second operation mode based on the first signal. | 02-05-2015 |
Chun-I Wu, Yunlin County TW
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20100263370 | MULTI-STAGE TURBOCHARGER REGULATION APPARATUS - A multi-stage turbocharger regulation apparatus includes a casing which has a housing chamber, a driving membrane and at least one floating membrane. The housing chamber has at least one blocking portion. The linkage bar runs through the bottom surface of the casing into the housing chamber to couple with a spring. The driving membrane pushes the linkage bar and also pushes the spring between the driving membrane and the bottom surface of the casing. The floating membrane has at least one opening. The driving membrane is pushed by the elastic force of the spring to block the opening. The floating membrane is compressed by a control gas to drive the driving membrane to push the spring and the linkage bar, or force the driving membrane to separate from the floating membrane to push the linkage bar and the spring. Thereby the wastegate can be opened or closed. | 10-21-2010 |
20100263371 | TURBINE INTAKE PRESSURE RELEASE STRUCTURE - A turbine intake pressure release structure to control pressure release between a throttle and a first turbine boosted pressure outlet includes a pressure release valve which has a first pressure orifice, a second pressure orifice and a housing chamber, at least one controller which has a pressure detection end and a driven portion and a switch duct which has a first end opening, a second end opening and a third end opening. The first end opening is connected to a third turbine boosted pressure outlet. The second end opening leads to the atmosphere. The third end opening is connected to the second pressure orifice. The driven portion runs through the switch duct to close the second end opening through the driven portion drive a membrane to a first position or closes the first end opening through the driven portion to drive the membrane to a second position. | 10-21-2010 |
Chun-Yuan Wu, Yunlin County TW
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20110180113 | METHOD OF WAFER CLEANING AND APPARATUS OF WAFER CLEANING - A method of cleaning wafer cleaning includes: first a wafer stage for holding and rotating a wafer is provided. The wafer has a surface to be washed. A nozzle is positioned on the wafer for spraying a cleaning solution. The nozzle moves in non-uniform motion from a first given point to a second given point so as to make the time which the first given point is exposed to the cleaning solution equal to the time which the second given point is exposed to the cleaning solution. Furthermore, the nozzle moves faster when passing the center of the wafer and moves slower when passing the edge of the wafer. | 07-28-2011 |
20120021583 | SEMICONDUCTOR PROCESS - A semiconductor process is disclosed. The semiconductor process includes the steps of: providing a substrate having a specific area defined thereon; and performing an etch process by using an etchant comprising H | 01-26-2012 |
20120070948 | ADJUSTING METHOD OF CHANNEL STRESS - An adjusting method of channel stress includes the following steps. A substrate is provided. A metal-oxide-semiconductor field-effect transistor is formed on the substrate. The MOSFET includes a source/drain region, a channel, a gate, a gate dielectric layer and a spacer. A dielectric layer is formed on the substrate and covers the metal-oxide-semiconductor field-effect transistor. A flattening process is applied onto the dielectric layer. The remaining dielectric layer is removed to expose the source/drain region. A non-conformal high stress dielectric layer is formed on the substrate having the exposed source/drain region. | 03-22-2012 |
20120074468 | SEMICONDUCTOR STRUCTURE - A semiconductor structure comprises a substrate, a gate structure, at least a source/drain region, a recess and an epitaxial layer. The substrate includes an up surface. A gate structure is located on the upper surface. The source/drain region is located within the substrate beside the gate structure. The recess is located within the source/drain region. The epitaxial layer fills the recess, and the cross-sectional profile of the epitaxial layer is an octagon. | 03-29-2012 |
20120086054 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor structure is disclosed. The semiconductor structure includes a gate structure disposed on a substrate, a source and a drain respectively disposed in the substrate at two sides of the gate structure, a source contact plug disposed above the source and electrically connected to the source and a drain contact plug disposed above the drain and electrically connected to the drain. The source contact plug and the drain contact plug have relatively asymmetric element properties. | 04-12-2012 |
20120115284 | METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE - A method for manufacturing a multi-gate transistor device includes providing a semiconductor substrate having a first patterned semiconductor layer formed thereon, sequentially forming a gate dielectric layer and a gate layer covering a portion of the first patterned semiconductor layer on the semiconductor substrate, removing a portion of the first patterned semiconductor layer to form a second patterned semiconductor layer, and performing a selective epitaxial growth process to form an epitaxial layer on a surface of the second patterned semiconductor layer. | 05-10-2012 |
20120196410 | METHOD FOR FABRICATING FIN FIELD EFFECT TRANSISTOR - A method for fabricating a fin-FET, wherein the method comprises several steps as follows: A substrate is first provided, and a silicon fin is then formed in the substrate. Next a dielectric layer is formed on the silicon fin and the substrate. A poly silicon layer is subsequently formed on the dielectric layer, and the poly silicon layer is then planarized. Subsequently, a poly silicon gate is formed and a portion of the silicon fin is exposed by patterning the planarized poly silicon layer. A source and a drain are separately formed on two opposite sides of the exposed silicon fin adjacent to the poly silicon gate. | 08-02-2012 |
20120223397 | METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ. | 09-06-2012 |
20120241863 | FIN FIELD-EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING PROCESS THEREOF - A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced. | 09-27-2012 |
20120244669 | Method of Manufacturing Semiconductor Device Having Metal Gates - The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench. | 09-27-2012 |
20120244675 | METHOD FOR FORMING METAL GATE - A method for forming a metal gate is provided. First, a dummy material is formed to completely cover a substrate. Second, a dopant is selectively implanted into the dummy material. Then, some of the dummy material is removed to expose part of the substrate and to form a dummy gate including a dopant region disposed between a first region and a second region. Later an interlayer dielectric layer is formed to surround the dummy gate. Next, a selective etching step is carried out to remove the first region to form a recess without substantially removing the dopant region. Afterwards, the recess is filled with a material set to form a metal gate. | 09-27-2012 |
20120248507 | METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a metal gate structure includes providing a substrate having at least a first metal oxide layer formed thereon, and transferring the surface of the first metal oxide layer into a second metal oxide layer. The first metal oxide layer includes a metal oxide (M | 10-04-2012 |
20120248511 | SEMICONDUCTOR STRUCTURE AND METHOD FOR SLIMMING SPACER - A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer. | 10-04-2012 |
20120264306 | Method of Forming Opening on Semiconductor Substrate - The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer. | 10-18-2012 |
20120270377 | METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE - A method of fabricating a semiconductor structure, in which after an etching process is performed to form at least one recess within a semiconductor beside a gate structure, a thermal treatment is performed on the recess in a gas atmosphere including an inert gas before a silicon-containing epitaxial layer is formed in the recess through an epitaxy growth process. | 10-25-2012 |
20120319198 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench. | 12-20-2012 |
20120322260 | THROUGH-SILICON VIA FORMING METHOD - A through-silicon via forming method includes the following steps. Firstly, a semiconductor substrate is provided. Then, a through-silicon via conductor is formed in the semiconductor substrate, and a topside of the through-silicon via conductor is allowed to be at the same level as a surface of the semiconductor substrate. Afterwards, a portion of the through-silicon via conductor is removed, and the topside of the through-silicon via conductor is allowed to be at a level lower than the surface of the semiconductor substrate, so that a recess is formed over the through-silicon via conductor. | 12-20-2012 |
20130001707 | FABRICATING METHOD OF MOS TRANSISTOR, FIN FIELD-EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF - A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided. | 01-03-2013 |
20130078778 | SEMICONDUCTOR PROCESS - A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed. | 03-28-2013 |
20130087810 | FIN FIELD-EFFECT TRANSISTOR STRUCTURE - A fin field-effect transistor structure comprises a substrate, a fin channel, a source/drain region, a high-k metal gate and a plurality of slot contact structures. The fin channel is formed on the substrate. The source/drain region is formed in the fin channel. The high-k metal gate formed on the substrate and the fin channel comprises a high-k dielectric layer and a metal gate layer, wherein the high-k dielectric layer is arranged between the metal gate layer and the fin channel. The slot contact structures are disposed at both sides of the metal gate. | 04-11-2013 |
20130089957 | FIN FIELD-EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING PROCESS THEREOF - A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced. | 04-11-2013 |
20130207122 | METHOD FOR FABRICATING FINFETS AND SEMICONDUCTOR STRUCTURE FABRICATED USING THE METHOD - A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method. | 08-15-2013 |
20130288446 | SEMICONDUCTOR STRUCTURE AND METHOD FOR SLIMMING SPACER - A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer. | 10-31-2013 |
20130330919 | MANUFACTURING PROCESS OF GATE STACK STRUCTURE WITH ETCH STOP LAYER - A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench. | 12-12-2013 |
20140106568 | METHOD OF FORMING OPENING ON SEMICONDUCTOR SUBSTRATE - The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer. | 04-17-2014 |
20140332824 | SEMICONDUCTOR STRUCTURE WITH DIFFERENT FINS OF FINFETS - A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the FinFETs are defined from the substrate. The even fins of the FinFETs are different from the odd fins of the FinFETs in at least one of the width and the material, and may be further different from the odd fins of the FinFETs in the height. | 11-13-2014 |
20140370701 | METHOD OF FABRICATING SEMICONDUCTOR PATTERNS - A method of fabricating semiconductor patterns includes steps as follows: Firstly, a substrate is provided and has at least a first semiconductor pattern and at least a second semiconductor pattern, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern. Then, a barrier pattern is formed over a surface of the first semiconductor pattern, and the second semiconductor pattern is exposed. Then, a surface portion of the second semiconductor pattern is reacted to form a sacrificial structure layer. Then, the barrier pattern and the sacrificial structure layer are removed, and the line width of the second semiconductor pattern is shrunken to be less than the line width of the first semiconductor pattern. A third semiconductor pattern having a line width can be further provided. | 12-18-2014 |
20150064896 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF | 03-05-2015 |
20150255307 | MANUFACTURING PROCESS OF GATE STACK STRUCTURE WITH ETCH STOP LAYER - A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench. | 09-10-2015 |
20150380512 | METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ. | 12-31-2015 |
E-In Wu, Yunlin County TW
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20120135836 | HYBRID VEHICLE AND HYBRID POWER SYSTEM - An operation method of a hybrid vehicle having an automatic manual transmission system adapted to use at least two energy sources is provided with the following steps. Engaging an engine with a starter generator motor such that the engine and the starter generator motor rotate synchronously. Performing a speed changing by using a control unit assembly through controlling rotation speed of the traction motor and a rotation speed of the starter generator motor to a desired rotation speed for the speed changing according to a running state of the vehicle, such that the engine and the traction motor nearly rotate synchronously with the automatic manual transmission system to perform a gear ratio shifting process thereby to perform the speed changing. Controlling an automatic-switching clutch to engage or disengage the engine and the traction motor to achieve a plurality of driving mode for the vehicle. | 05-31-2012 |
Fa-Chen Wu, Yunlin County TW
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20110157528 | DISPLAY PANEL - A display panel includes a first substrate, a conductive light-shielding pattern, color filter patterns, a second substrate, scan lines, data lines, pixel structures, third pads and fourth pads. The conductive light-shielding pattern disposed on the first substrate defines conductive matrix pattern, first pads, and second pads. Each first pad is electrically connected to one corresponding second pad through the conductive matrix pattern and insulated with other second pads. The color filter patterns are disposed on the first substrate and a portion of each color filter pattern overlaps the conductive light-shielding pattern. The third pads are one-to-one electrically to the first pads while the fourth pads are one-to-one electrically connected to the second pads. Each fourth pad is electrically connected to one of the scan lines and one of the data lines. | 06-30-2011 |
20110266565 | DISPLAY PANEL - A display panel having a display area and a non-display area outside the display area is provided. The display panel includes a first substrate, a conductive light-shielding pattern, color filter patterns, first spacers, transparent pads, a second substrate, scan lines, data lines, pixel structures, third pads and fourth pads. The conductive light-shielding pattern defines a conductive matrix pattern, a plurality of first pads and second pads. Each first pad is electrically connected with one of the corresponding second pads through the conductive matrix pattern. The color filter patterns include a plurality of first filter patterns and second filter patterns. The second filter patterns are located within the non-display area and disposed on the second pads. The first spacers are disposed on the second filter patterns, and the transparent pads cover the first spacers and contact the second pads. | 11-03-2011 |
Guan-Ming Wu, Yunlin County TW
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20110050336 | MULTI-CHIP STACK STRUCTURE AND SIGNAL TRANSMISSION METHOD THEREOF - A multi-chip stack structure and a signal transmission method are disclosed in specification and drawing, where the multi-chip stack structure includes first and second chips. The first chip includes a first inductance coil with a first series capacitor, and the second chip includes a second inductance coil with a second series capacitor. The first and second inductance coils are magnetically coupled to each other. The magnetically coupled inductance coils and the capacitors constitute a coupling filter. | 03-03-2011 |
I Wei Wu, Yunlin County TW
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20090167841 | SYSTEM AND METHOD FOR MULTI-PARTICIPANT VIDEO CONFERENCE WITHOUT MULTIPOINT CONFERENCING UNIT - The method for multi-participant video conference without a multipoint conferencing unit includes the following steps: generating a multicast forest; adjusting the video resolution to lower the streaming rate; and limiting the audio multicast numbers of the members. The multicast forest includes a plurality of multicast trees and the ways of connections of the nodes in trees are all different from each other. | 07-02-2009 |
Jian-Cheng Wu, Yunlin County TW
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20140324898 | SYSTEM AND METHOD FOR SEARCHING ALIASES ASSOCIATED WITH AN ENTITY - A search system for collecting aliases associated with an entity name, includes a storage module configured to store at least one first lexical pattern, a search module coupled to the storage module and configured to obtain a plurality of first snippets from a database according to the entity name, and an alias extracting module coupled to the storage module and the search module separately and configured to, according to the entity name and the first lexical pattern, determine whether any first alias exists in the first snippets. If a first alias exists, the alias extracting module extracts it out and stores it in the storage module. | 10-30-2014 |
Jian-Lin Wu, Yunlin County TW
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20120012246 | ENCAPSULATION METHOD OF ENVIRONMENTALLY SENSITIVE ELECTRONIC ELEMENT - An encapsulation method of an environmentally sensitive electronic element is provided. A first substrate is provided, wherein at least one first alignment mark and a plurality of environmentally sensitive electronic elements are formed on the first substrate. A second substrate is provided, wherein at least one second alignment mark and a plurality of limiting cavities are formed on the second substrate. A plurality of cover lids is respectively disposed in the limiting cavities. An adhesive is formed on the cover lids. The first substrate and the second substrate are laminated together with the first alignment mark and the second alignment mark as reference, so that the environmentally sensitive electronic elements are sealed in the adhesive and located between the first substrate and the second substrate. The second substrate and the cover lids are separated from each other. | 01-19-2012 |
20130126932 | PACKAGE OF ENVIRONMENTAL SENSITIVE ELECTRONIC ELEMENT - A package of an environmental sensitive electronic element including a first substrate, a second substrate, an environmental sensitive electronic element, a flexible structure layer and a filler layer is provided. The environmental sensitive electronic element is disposed on the first substrate and located between the first substrate and the second substrate. The environmental sensitive electronic element includes an anode layer, a hole injecting layer, a hole transporting layer, an organic light emitting layer, a cathode layer and an electron injection layer. The flexible structure layer is disposed on the environmental sensitive electronic element and includes a soft layer, a trapping layer and a protective layer. The material of the trapping layer is the same as the material of the electron injection layer. The filler layer is disposed between the first substrate and the second substrate and encapsulates the environmental sensitive electronic element and the flexible structure layer. | 05-23-2013 |
Jian-Shu Wu, Yunlin County TW
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20080257399 | BIFACIAL THIN FILM SOLAR CELL AND METHOD FOR MAKING THE SAME - A bifacial thin film solar cell and method for fabricating the same are provided. The solar cell has a first and a second transparent substrates, a first and a second solar cell modules, and an insulating layer. The first solar cell module is formed on the first transparent substrate, and has a metal layer as one of the electrodes of the first solar cell module and as a light reflection layer. The insulating layer is formed on the metal layer of the first solar cell module. The second solar cell module is formed between the insulating layer and the second transparent substrate. | 10-23-2008 |
20110240092 | THIN FILM SOLAR CELL MODULE OF SEE-THROUGH TYPE - A thin film solar cell module of see-through type having cells connected in series and disposed on an opaque substrate with holes is provided. The thin film solar cell module includes a first electrode, a second electrode, and a photoelectric conversion layer disposed between the first electrode and the second electrode. The first electrode is disposed on the opaque substrate and is composed of a first comb electrode and block-like first electrodes. The second electrode is disposed above the first electrode and is composed of a second comb electrode and block-like second electrodes. A portion of the block-like first electrodes, a portion of the opaque substrate, and the holes are exposed between the second comb electrode and the block-like second electrodes. The second comb electrode and the first comb electrode are disposed symmetrically, and the block-like first electrodes and the block-like second electrodes are disposed by parallel displacement. | 10-06-2011 |
Jing-Mei Wu, Yunlin County TW
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20120245108 | METHOD OF MODULATING COMPLEMENT FACTOR B (CFB) EXPRESSION IN CELLS - The present invention relates to a method of modulating complement factor B (CFB) expression in cells, comprising administering an effective amount of tannic acid to the cells. This method can be applied in treating or prophylaxis of the disease, disorder or medical condition associated to complement factor B (CFB) expression. | 09-27-2012 |
Jin Neng Wu, Yunlin County TW
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20090132737 | REMOTE INTERFACE APPARATUS, CONTROL SYSTEM, AND THE METHOD THEREOF - A remote interface apparatus comprises a network interface, a peripheral device interface, an interface-providing mechanism and a network address setting mechanism. The network interface is configured to communicate with a remote host. The peripheral device interface is configured to connect to a peripheral device. The interface-providing mechanism cooperates with the network interface to transfer the peripheral device interface into a remote peripheral device connection port of the host. The network address setting mechanism is configured to automatically obtain a network address upon a connection to the network, and to broadcast information of the peripheral device interface. | 05-21-2009 |
Kuan-Wei Wu, Yunlin County TW
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20110187982 | COLOR CHOLESTERIC LIQUID CRYSTAL DISPLAY DEVICES AND FABRICATION METHODS THEREOF - Color cholesteric liquid crystal display devices and fabrication methods thereof are provided. The color cholesteric liquid crystal display device includes a first substrate, a second substrate and a gap interposed therebetween. A patterned enclosed structure, formed by adhering a first patterned enclosed structure on the first substrate and a second patterned enclosed structure on the second substrate, is interposed between the first substrate and the second substrate, dividing a plurality of color sub-pixel channels. A plurality of the color cholesteric liquid crystals are respectively filled into each of the color sub-pixel channel, wherein the first patterned enclosed structure is tightly adhered to the second patterned enclosed structure so as to prevent mixing of the color cholesteric liquid crystals between adjacent color sub-pixel channels. | 08-04-2011 |
Lin-Yi Wu, Yunlin County TW
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20130109036 | PROTEIN SUBSTRATE AND ITS MANUFACTURING METHOD | 05-02-2013 |
Ming-Tzung Wu, Yunlin County TW
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20090085016 | HIGH OPTICAL CONTRAST PIGMENT AND COLORFUL PHOTOSENSITIVE COMPOSITION EMPLOYING THE SAME AND FABRICATION METHOD THEREOF - A high optical contrast pigment and colorful photosensitive composition employing the same are disclosed. The composition comprises a solvent, an alkali-soluble resin, reactive monomer, and a modified pigment which has low crystallization. The low crystallization degree means that the grain size variation R is not more 80%, wherein the grain size variation R is represented by a formula R=G1/G0×100%, G0 is the original grain size, and G1 is the grain size after modification. | 04-02-2009 |
20100079720 | RETARDATION FILM AND METHOD FOR MANUFACTURING THE SAME - A retardation film and formula thereof, and method for manufacturing the same are provided. Furthermore, the retardation film is applied to compensate TFT-LCD viewing angle. Referring to the formula of the invention, the positive A film-embedded negative C optically anisotropic coating of the retardation film can be formed by single step coating, and the retardation film with net negative C symmetry in whole is easily manufactured. | 04-01-2010 |
20110088592 | REACTIVE SILICON DIOXIDE COMPOUND AND OPTICAL PROTECTIVE FILM CONTAINING THE SAME - A reactive silicon dioxide compound, wherein the formula of the reactive silicon dioxide compound is shown as Formula (I): | 04-21-2011 |
20110111333 | HEAT-RESISTANT FLEXIBLE COLOR FILTER - The invention provides a heat-resistant flexible color filter, including: a flexible transparent substrate, wherein the forming material thereof includes nano silica and polyimide, and the nano silica is present in an amount of about 20-70 wt %, based on 100 wt % of the forming material; and a heat-stable color photoresist material coated on the flexible transparent substrate, wherein the heat stable color photoresist material includes: a base soluble resin system about 30-90 wt %; a photosensitive system about 5-60 wt %; and a pigment coated with an inorganic alkoxide about 10-50 wt %. | 05-12-2011 |
Pei-Shan Wu, Yunlin County TW
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20150200118 | BONDING APPARATUS AND METHOD - A bonding apparatus includes a wafer stage, a first chip stage, a first transporting device, a second stage and a second transporting device. The wafer stage is used for holding a wafer. The first chip stage is used for holding at least one first chip. The first transporting device is used for transporting the first chip from the first chip stage onto the wafer. The second chip stage is used for holding at least one second chip. The second transporting device is used for transporting the second chip from the second chip stage onto the wafer. | 07-16-2015 |
Rong-Wha Wu, Yunlin County TW
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20090021525 | Display apparatus, display system and method for setting color scheme - A display apparatus, a display system and a method for setting color scheme are provided. The display system comprises a host and a display apparatus. The host comprises a first storage unit and a processing unit. The display apparatus used for displaying a graphical user interface (GUI) comprises a second storage unit and a display control unit. An application program and a color scheme service program are stored in the first storage unit. The processing unit executes the application program for generating a GUI, and executes the color scheme service program for outputting a coordinate parameter according to the GUI. A color scheme selector program is stored in the second storage unit. The display control unit executes the color scheme selector program for setting a color scheme of the GUI according to the coordinate parameter and a color scheme parameter. | 01-22-2009 |
20090115773 | COMPENSATION DEVICE, METHOD, AND ELECTRONIC SYSTEM UTILIZING THE SAME - A compensation device receiving an input signal, generating a compensated signal to a display panel, and including a memory unit and a control unit. The memory unit stores a first overdrive look-up table and a second overdrive look-up table. The control unit is connected to the memory unit and selects a compensation data from the first or the second overdrive look-up table according to a frame rate of the input signal. The control unit compensates the input signal by the compensation data to generate the compensated signal. | 05-07-2009 |
Shang-Jie Wu, Yunlin County TW
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20160140915 | PIXEL STRUCTURE - A pixel structure is provided. The pixel structure includes a scan line and a data line, an active device, a pixel electrode, and a common electrode. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The common electrode is disposed to overlap with the pixel electrode. The common electrode is coupled to the pixel electrode to form a first storage capacitor and a second storage capacitor. The first storage capacitor and the second storage capacitor commonly use the pixel electrode as an upper electrode. | 05-19-2016 |
Shang-Teh Wu, Yunlin County TW
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20140265678 | ENERGY CONVERTING DEVICE HAVING AN ECCENTRIC ROTOR - An energy converting device having an eccentric rotor includes a fixed portion and an eccentric rotor. This fixed portion has a central axis, an outer frame, and several fixed coil portions. The eccentric rotor has a bearing, a rotatory shaft, an eccentric arm, an eccentric shaft portion, a supporting plate, an inner annular magnetic portion, and an outer annular magnetic portion. The inner magnetic portion and the outer magnetic portion are concentric and aligned with the eccentric shaft portion. The eccentric shaft portion is offset from the rotary shaft. When the rotary shaft of the eccentric rotor rotates, these fixed coil portions cut through the inner magnetic portion and the outer magnetic portion repeatedly, so magnetic flux passing through the coils alternates accordingly to generate electromotive force. Conversely, it can be used as an electric motor. In addition, it can be integrated with a cycloidal speed reducer to form a motor with speed reduction and torque augmentation capability. The integrated cycloidal motor is compact, does not need a shaft coupler to transmit power from a motor to the reducer, and therefore may operate more smoothly. | 09-18-2014 |
Te-Ho Wu, Yunlin County TW
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20130009633 | Method of Measuring Dimensionless Coupling Constant of Magnetic Structure - In A method for measuring a dimensionless coupling constant of a magnetic structure includes the following steps. A step of applying an external vertical magnetic field is performed for enabling magnetic moments of a RE-TM (Rare Earth-Transition metal) alloy magnetic layer of the magnetic structure to be vertical and saturated. A step of measuring a compensation temperature is performed when the sum of the magnetization of the RE-TM alloy magnetic layer is zero. A step of applying an external parallel magnetic field to the RE-TM alloy magnetic layer is performed. A step of adjusting the temperature of the magnetic structure to the compensation temperature and measuring a hysteresis loop of the magnetic structure under the external parallel magnetic field is performed, wherein the inverse of the slope of hysteresis loop is a dimensionless coupling constant. | 01-10-2013 |
20150023092 | RING-SHAPED MAGNETORESISTIVE MEMORY DEVICE AND WRITING METHOD THEREOF - A ring-shaped magnetoresistive memory device includes a ring-shaped magnetoresistive memory cell, a first conductor, and a second conductor. The first conductor is positioned on a first surface of the ring-shaped magnetoresistive memory cell for generating a first magnetic field pulse. The second conductor is positioned on a second surface of the ring-shaped magnetoresistive memory cell for generating a second magnetic field pulse. The first surface is opposite to the second surface. An extension direction of the first conductor is perpendicular to an extension direction of the second conductor. A time delay is between the first magnetic field pulse and the second magnetic field pulse. | 01-22-2015 |
Tien-Jung Wu, Yunlin County TW
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20140015741 | PROGRAMMABLE GAMMA CIRCUIT FOR LCD DISPLAY DEVICE AND RELATED METHOD AND DRIVER CIRCUIT - A programmable Gamma circuit of a LCD display device includes a control signal generator for generating multiple control signals; one or more voltage-reducing circuits for generating multiple voltage-reduced signals corresponding to a common voltage feedback signal outputted from a LC array of the LCD display device; and multiple amplifying circuits for respectively amplifying the multiple coupled signals to generate multiple Gamma calibration signals. The multiple voltage-reduced signals are respectively coupled with the multiple control signals to generate multiple coupled signals. | 01-16-2014 |
Tsong-Hsueh Wu, Yunlin County TW
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20110132456 | SOLAR CELL INTEGRATING MONOCRYSTALLINE SILICON AND SILICON-GERMANIUM FILM - The present invention discloses a solar cell integrating monocrystalline silicon and a SiGe film, which comprises an N-type amorphous silicon-germanium (SiGe) film formed on a P-type monocrystalline silicon substrate. The P-type monocrystalline silicon substrate has a roughened surface to capture sunlight. A transparent conductive layer is stacked on the N-type amorphous SiGe film. Metal electrodes are formed on the transparent conductive layer and penetrate the transparent conductive layer to contact the N-type amorphous SiGe film. A P-type polycrystalline SiGe film is formed on the backside of the P-type monocrystalline silicon substrate. A back surface field is arranged below the P-type polycrystalline SiGe film to prevent from the recombination of major carriers. A backside metal electrode layer is arranged below the back surface field to function as a backside electrode and decrease the contact resistance. Thereby, the present invention can effectively promote the absorption rate of solar energy. | 06-09-2011 |
Ya-Na Wu, Yunlin County TW
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20130236507 | Method for treating cancer by using Fe-containing alloy particles - A method for treating a cancer is disclosed, which comprises: administering an effective amount of Fe-containing alloy particles to a subject in need, wherein a material of each Fe-containing alloy particle is an alloy comprising a first metal of Fe and a second metal. | 09-12-2013 |
20130236548 | Method for treating cancer by using Fe-based particles - A method for treating a cancer is disclosed, which comprises: administering an effective amount of Fe-based particles to a subject in need, wherein the Fe-based particles have core-shell structures. Herein, each Fe-based particle of the present invention comprises: an Fe elemental core with zero valent irons; and a covering layer formed on partial or whole surface of the Fe elemental core, wherein a material of the covering layer is a metal, a metal doped with dopants, a metal alloy, a polymer, carbon, a metal oxide or a nonmetal oxide, and the shape of the Fe-based particles is a rod, a sphere, a cubic or a dumbbell, with the proviso that the metal is not Au. | 09-12-2013 |
Yi-Cang Wu, Yunlin County TW
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20120268192 | HIGH-LINEARITY TESTING STIMULUS SIGNAL GENERATOR - A high-linearity testing stimulus signal generator comprises a signal collection unit receiving an input current signal, a waveform conversion unit connecting with the signal collection unit, a first voltage-to-current conversion unit connecting with the waveform conversion unit, a delay unit connecting with the waveform conversion unit, a second voltage-to-current conversion unit connecting with the delay unit, a current comparison unit connecting respectively with the first voltage-to-current conversion unit and the second voltage-to-current conversion unit, an error calculation unit connecting with the current comparison unit, and a compensation unit connecting with the error calculation unit. The above-mentioned structure forms a feedback mechanism to perform compensation adjustment to promote the linearity of the output signals. Thus, the present invention can generate high-accuracy testing stimulus signals. | 10-25-2012 |
Yin-Cyuan Wu, Yunlin County TW
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20150226899 | BACK LIGHT MODULE - A back light module comprising a light-emitting module, a light transparent refraction plate and a light guide plate is disclosed. The light-emitting module comprises a substrate and several light-emitting components disposed on the substrate. Each light-emitting component has a light-emitting surface. The light transparent refraction plate is disposed on the substrate and has several apertures. Each aperture exposes a corresponding light-emitting surface, and has a sidewall higher than the light-emitting surface. The light guide plate has a lateral light incident surface facing the light-emitting surface and pressing the light transparent refraction plate. The refractive index of the light transparent refraction plate is larger than that of the light guide plate, such that the light emitted by each light-emitting component will enter the light guide plate after passing through the light transparent refraction plate. | 08-13-2015 |
Yue-Jin Wu, Yunlin County TW
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20140031531 | METHOD OF PROTEIN PURIFICATION - A method for producing a target protein is provided, which includes steps described below. A crude extract including a fusion protein is provided. The fusion protein includes a tag, a target protein and a linker inserted between the tag and the target protein. The fusion protein and magnetic particles are then bound to form a magnetic particle-binding fusion protein. Finally, the linker of the magnetic particle-binding fusion protein undergoes autocleavage by using a cleavage buffer solution to release the target protein. A one-pot process for producing a purified target protein is also provided. | 01-30-2014 |