Patent application number | Description | Published |
20080269753 | DYNAMIC CERVICAL PLATE - A cervical plate assembly having a body, with at least two wings, and a tensioning mechanism for applying a force to the wings. The tensioning mechanism includes a shape memory band and an adjuster for shortening or lengthening the band. | 10-30-2008 |
20090171392 | Guide wire mounting collar for spinal fixation using minimally invasive surgical techniques - An improved guide wire having a collar member for affixation to a pedicle screw, the guide wire assembly used in a system, set of instrumentation and method comprising the combination and use of plural pedicle screws, a rod for connecting pedicle screws in a relatively rigid manner, and instrumentation means to optimize insertion of the rod into the pedicle screws, such means comprising a guide wire and instrumentation to position the guide wire in the pedicle screws, whereby the guide wire is mounted to a pedicle screw, all the screws are implanted into the vertebrae, and the rod subsequently guided into the pedicle screws along the guide wire, all using minimally invasive surgical incisions. | 07-02-2009 |
20100063590 | LAMINOPLASTY IMPLANT - A hollow non-load-bearing spinal implant having a hollow body and an attachment device for attaching the implant. A method of inserting a non-load-bearing spinal implant by inserting the laminoplasty implant into a prepared space in a spine, positioning the implant within the prepared space and affixing the implant to the spine. | 03-11-2010 |
20110144652 | System, instrumentation and method for spinal fixation using minimally invasive surgical techiques - A pedicle screw tower having a guide chute, open at both ends, affixed to the exterior of the main body of the tower. The guide chute extends the length of the tower and is curved inwardly at its bottom such that the exit direction is at approximately 90 degrees to and facing the central axis of tower. A guide cable is passed into and through the guide chute such that it is directed across the tower to an adjacent tower. | 06-16-2011 |
20110184473 | Method and apparatus for spinal fixation using minimally invasive surgical techniques - An improved method and guide wire assembly used in a system, set of instrumentation and method comprising the combination and use of plural pedicle screws, a rod for connecting pedicle screws in a relatively rigid manner, and instrumentation to optimize insertion of the rod into the pedicle screws, the assembly having a guide wire and instrumentation to grasp a medial portion of the guide wire to pull the medial portion through all the pedicle screws and connecting the loop to the end of a fixation rod, whereby one end of the guide wire is mounted to a pedicle screw, all the screws are implanted into the vertebrae, and the rod subsequently guided into the pedicle screws by pulling the guide wire loop back through the pedicle screws, all using minimally invasive surgical incisions. | 07-28-2011 |
20110184475 | System, instrumentation and method for spinal fixation using minimally invasive surgical techiques - A cable threader device for passing a guide cable between pedicle screws during minimally invasive spinal surgery, the device comprising a handle with a trigger mechanism, the handle mounted onto an elongated shaft having a curved free end with a detachable curved lead member retained in telescoping manner on the end of the body. The guide cable is affixed to the lead member, the instrument is inserted into a first screw tower, the trigger mechanism is activated to advance the lead member into the adjacent tower, and the lead member and guide cable are retrieved through the second tower. Alternatively, the lead member is a hollow sleeve and the guide cable is pushed through the lead member. | 07-28-2011 |
20120215259 | POSTERIOR CERVICAL FUSION SYSTEM AND TECHNIQUES - A posterior cervical fusion surgery assembly and method. The assembly includes a sled adapted to be positioned in a facet joint and two receivers slidably mounted on the sled. The receivers are adapted to support surgical instruments such as a drill, a tap, and a screw. The sled assists in orienting the instruments at a desired angle with respect to the spine. | 08-23-2012 |
20140018868 | Instrumentation for Spinal Fixation Using Minimally Invasive Surgical Techniques - A cable threader device for passing a guide cable between pedicle screws during minimally invasive spinal surgery, the device comprising a handle with a trigger mechanism, the handle mounted onto an elongated shaft having a curved free end with a detachable curved lead member retained in telescoping manner on the end of the body. The guide cable is affixed to the lead member, the instrument is inserted into a first screw tower, the trigger mechanism is activated to advance the lead member into the adjacent tower, and the lead member and guide cable are retrieved through the second tower. | 01-16-2014 |
20150230834 | System and Method for Posterior Cervical Fusion - This application describes surgical instruments and implants for building a posterior fixation construct across one or more segments of the cervical spinal column. The construct includes a sled adapted for positioning in a facet joint and two receivers slideably mounted on the sled. The receivers are adapted to support surgical instruments such as a drill, a tap, and a screw. The sled assists in orienting the instruments at a desired angle with respect to the spine. | 08-20-2015 |
Patent application number | Description | Published |
20110310775 | DE-MULTIPLEXING A RADIO FREQUENCY INPUT SIGNAL USING OUTPUT TRANSFORMER CIRCUITRY - The present disclosure relates to de-multiplexing at least one RF input signal feeding RF power amplifier circuitry to create multiple de-multiplexed RF output signals, which may be used to provide RF transmit signals in an RF communications system. Output transformer circuitry is coupled to outputs from the RF power amplifier circuitry to provide the de-multiplexed RF output signals, which may support multiple modes, multiple frequency bands, or both. The de-multiplexed RF output signals may be used in place of RF switching elements in certain embodiments. As a result, RF front-end switching circuitry in the RF communications system may be simplified, thereby reducing insertion losses, reducing costs, reducing size, or any combination thereof. Additionally, the output transformer circuitry may provide load line transformation, output transistor biasing, or both to the RF power amplifier circuitry. | 12-22-2011 |
20130024142 | QUASI ISO-GAIN SUPPLY VOLTAGE FUNCTION FOR ENVELOPE TRACKING SYSTEMS - A method of defining a quasi iso-gain supply voltage function for an envelope tracking system is disclosed. The method includes a step of capturing iso-gain supply voltage values versus power values for a device under test (DUT). Other steps involve locating a minimum iso-gain supply voltage value, and then replacing the iso-gain supply voltage values with the minimum iso-gain supply voltage value for corresponding output power values that are less than an output power value corresponding to the minimum iso-gain supply voltage value. The method further includes a step of generating a look-up table (LUT) of iso-gain supply voltage values as a function of input power for the DUT after the step of replacing the iso-gain supply voltage values with the minimum iso-gain supply voltage value for corresponding output power values that are less than an output power value corresponding to the minimum iso-gain supply voltage value. | 01-24-2013 |
20130154729 | DYNAMIC LOADLINE POWER AMPLIFIER WITH BASEBAND LINEARIZATION - Radio frequency (RF) amplification devices and methods of amplifying RF signals are disclosed. In one embodiment, an RF amplification device includes a control circuit and a Doherty amplifier configured to amplify an RF signal. The Doherty amplifier includes a main RF amplification circuit and a peaking RF amplification circuit. The control circuit is configured to activate the peaking RF amplification circuit in response to the RF signal reaching a threshold level. In this manner, the activation of the peaking RF amplification circuit can be precisely controlled. | 06-20-2013 |
20130169245 | NOISE REDUCTION FOR ENVELOPE TRACKING - A direct current (DC)-DC converter, which includes a parallel amplifier, a radio frequency (RF) trap, and a switching supply, is disclosed. The switching supply includes switching circuitry and a first inductive element. The parallel amplifier has a feedback input and a parallel amplifier output. The switching circuitry has a switching circuitry output. The first inductive element is coupled between the switching circuitry output and the feedback input. The RF trap is coupled between the parallel amplifier output and a ground. | 07-04-2013 |
20130176075 | DUAL PARALLEL AMPLIFIER BASED DC-DC CONVERTER - A direct current (DC)-DC converter, which includes switching circuitry, a first parallel amplifier, and a second parallel amplifier, is disclosed. The switching circuitry has a switching circuitry output. The first parallel amplifier has a first feedback input and a first parallel amplifier output. The second parallel amplifier has a second feedback input and a second parallel amplifier output. A first inductive element is coupled between the switching circuitry output and the first feedback input. A second inductive element is coupled between the first feedback input and the second feedback input. | 07-11-2013 |
20130181730 | PULSED BEHAVIOR MODELING WITH STEADY STATE AVERAGE CONDITIONS - A method for pulsed behavior modeling of a device under test (DUT) using steady state conditions is disclosed. The method includes providing an automated test system (ATS) programmed to capture at least one behavior of the DUT. The ATS then generates a DUT input power pulse that transitions from a predetermined steady state level to a predetermined pulse level and back to the predetermined steady state level. At least one behavior of the DUT is then captured by the ATS while the input power is at the predetermined pulse level. The ATS then steps the predetermined pulse level to a different predetermined pulse level, and the above steps are repeated until a range of predetermined pulse levels is swept. The ATS then steps the predetermined steady state level to a different steady state level, and the above steps are repeated until a range of predetermined steady state levels is swept. | 07-18-2013 |
20130181774 | ENVELOPE TRACKING WITH VARIABLE COMPRESSION - Radio frequency (RF) transmitter circuitry, which includes an envelope tracking power supply and an RF power amplifier (PA), is disclosed. The RF PA operates in either a first operating mode or a second operating mode, such that selection of the operating mode is based on compression tolerance criteria. During the first operating mode, the RF PA receives and amplifies an RF input signal using a first compression level. During the second operating mode, the RF PA receives and amplifies the RF input signal using a second compression level, which is greater than the first compression level. The envelope tracking power supply provides an envelope power supply signal to the RF PA. The envelope power supply signal provides power for amplification. | 07-18-2013 |
20140016517 | DE-MULTIPLEXING A RADIO FREQUENCY INPUT SIGNAL USING OUTPUT TRANSFORMER CIRCUITRY - The present disclosure relates to de-multiplexing at least one RF input signal feeding RF power amplifier circuitry to create multiple de-multiplexed RF output signals, which may be used to provide RF transmit signals in an RF communications system. Output transformer circuitry is coupled to outputs from the RF power amplifier circuitry to provide the de-multiplexed RF output signals, which may support multiple modes, multiple frequency bands, or both. The de-multiplexed RF output signals may be used in place of RF switching elements in certain embodiments. As a result, RF front-end switching circuitry in the RF communications system may be simplified, thereby reducing insertion losses, reducing costs, reducing size, or any combination thereof. Additionally, the output transformer circuitry may provide load line transformation, output transistor biasing, or both to the RF power amplifier circuitry. | 01-16-2014 |
20140253244 | POWER AMPLIFIER SPURIOUS CANCELLATION - This disclosure relates generally to power amplification devices and methods of operating the same. The power amplification devices are capable of reducing (and possibly cancelling) modulation of a ripple variation of a supply voltage level of a supply voltage onto a radio frequency (RF) signal. In one embodiment, a power amplification device includes a power amplification circuit configured to amplify an RF signal with a supply voltage such that a ripple variation in a supply voltage level of the supply voltage is modulated onto the RF signal in accordance with a conversion gain. However, the power amplification device also includes a plurality of ripple rejection circuits. The plurality of ripple rejection circuits is configured to produce phase shifts and one or more amplitude shifts in the RF signal so as to reduce the conversion gain of the power amplification circuit. | 09-11-2014 |
20150139359 | FREQUENCY SELECTIVE PREDISTORTION - A baseband PA predistortion module, which includes a baseband combiner, a baseband PA correction circuit, and a baseband filter, is disclosed. The baseband PA correction circuit replicates behavior of an RF PA by processing a modulation data signal to provide a predistortion data signal. The behavior of the RF PA includes distortion. The modulation data signal is representative of an RF input signal to an RF PA and the predistortion data signal is representative of a correction needed at an output of the RF PA. The baseband filter receives and filters the predistortion data signal to provide a reduced predistortion data signal, such that a low frequency content of the reduced predistortion data signal is less than a low frequency content of the predistortion data signal. The baseband combiner receives and combines the modulation data signal and the reduced predistortion data signal to provide a baseband transmit signal. | 05-21-2015 |
Patent application number | Description | Published |
20090083518 | Attaching and virtualizing reconfigurable logic units to a processor - In one embodiment, the present invention includes a pipeline to execute instructions out-of-order, where the pipeline has front-end stages, execution units, and back-end stages, and the execution units are coupled between dispatch ports of the front-end stages and writeback ports of the back-end stages. Further, a reconfigurable logic is coupled between one of the dispatch ports and one of the writeback ports. Other embodiments are described and claimed. | 03-26-2009 |
20100250792 | OPPORTUNISTIC IMPROVEMENT OF MMIO REQUEST HANDLING BASED ON TARGET REPORTING OF SPACE REQUIREMENTS - Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space requirements) are described. In one embodiment, logic in a processor may detect one or more bits in a message that is to be transmitted from an input/output (I/O) device. The one or more bits may indicate memory mapped I/O (MMIO) information corresponding to one or more attributes of the I/O device. Other embodiments are also disclosed. | 09-30-2010 |
20110078389 | MANAGING AND IMPLEMENTING METADATA IN CENTRAL PROCESSING UNIT USING REGISTER EXTENSIONS - A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers. | 03-31-2011 |
20110258419 | Attaching And Virtualizing Reconfigurable Logic Units To A Processor - In one embodiment, the present invention includes a pipeline to execute instructions out-of-order, where the pipeline has front-end stages, execution units, and back-end stages, and the execution units are coupled between dispatch ports of the front-end stages and writeback ports of the back-end stages. Further, a reconfigurable logic is coupled between one of the dispatch ports and one of the writeback ports. Other embodiments are described and claimed. | 10-20-2011 |
20130022201 | Encrypted memory - A memory device is operable to perform channel encryption wherein for communication between devices, each includes cryptographic logic and performs cryptographic operations. In an illustrative embodiment, the memory device can comprise memory operable to store data communicated via a communication channel from a processor, and logic operable to perform channel encryption operations on the communication channel that communicates information between the processor and the memory. | 01-24-2013 |
20130024676 | Control flow integrity - In at least some embodiments, a processor in accordance with the present disclosure is operable to enforce control flow integrity. For examiner, a processor may comprise logic operable to execute a control flow integrity instruction specified to verify changes in control flow and respond to verification failure by at least one of a trap or an exception. | 01-24-2013 |
20130024867 | Resource allocation using a library with entitlement - An entitlement vector may be used when selecting a thread for execution in a multi-threading environment in terms of aspects such as priority. An embodiment or embodiments of an information handling apparatus can comprise a library comprising a plurality of functions and components operable to handle a plurality of objects. The information handling apparatus can further comprise an entitlement vector operable to assign entitlement to at least one of a plurality of resources to selected ones of the plurality of functions and components. | 01-24-2013 |
20130024937 | Intrusion detection using taint accumulation - A method operable in a computing device adapted for handling security risk can use taint accumulation to detect intrusion. The method can comprise receiving a plurality of taint indicators indicative of potential security risk from a plurality of distinct sources at distinct times, and accumulating the plurality of taint indicators independently using a corresponding plurality of distinct accumulation functions. Security risk can be assessed according to a risk assessment function that is cumulative of the plurality of taint indicators. | 01-24-2013 |
20130024939 | Conditional security response using taint vector monitoring - An embodiment or embodiments of a computing system can conditionally trap based on a taint vector. A computing system can comprise at least one taint vector operable to list at least one of a plurality of taints indicative of potential security risk originating from at least one of a plurality of resources, and response logic operable to monitor the at least one taint vector and respond to a predetermined taint condition. | 01-24-2013 |
20130031364 | Fine-grained security in federated data sets - A data processing system, a server such as a federated server, a computer system, and like devices, and associated operating methods can be configured to support fine-grained security including resource allocation and resource scheduling. A data processing system can comprise a federated server operable to access data distributed among a plurality of remote data sources upon request from a plurality of client users and applications; and logic executable on the federated server. The logic can be operable to enforce fine-grained security operations on a plurality of federated shared data sets distributed among the plurality of remote data sources. | 01-31-2013 |
20130036314 | Security perimeter - Embodiments of memory devices, computer systems, security apparatus, data handling systems, and the like, and associated methods facilitate security in a system incorporating the concept of a security perimeter which combines cryptographic and physical security. The memory device can comprise a memory operable to store information communicated with a processor, and a logic operable to create at least one cryptographic security perimeter enclosing at least one selected region of the memory and operable to manage information communication between the processor and the at least one selected region of the memory. | 02-07-2013 |
20130036464 | Processor operable to ensure code integrity - A processor can be used to ensure that program code can only be used for a designed purpose and not exploited by malware. Embodiments of an illustrative processor can comprise logic operable to execute a program instruction and to distinguish whether the program instruction is a legitimate branch instruction or a non-legitimate branch instruction. | 02-07-2013 |
20130081039 | Resource allocation using entitlements - A data handling apparatus are adapted to facilitate resource allocation, allocating resources upon which objects execute. A data handling apparatus can comprise resource allocation logic and a scheduler. The resource allocation logic can be operable to dynamically set entitlement value for a plurality of resources comprising physical/logical resources and operational resources. The entitlement value are specified as predetermined rights wherein a process of a plurality of processes is entitled to a predetermined percentage of operational resources. The scheduler can be operable to monitor the entitlement value and schedule the processes based on priority of the entitlement values. | 03-28-2013 |
20130081043 | Resource allocation using entitlement hints - An embodiment of an information handling apparatus can comprise an entitlement vector operable to specify resources used by at least one object of a plurality of a plurality of objects, and logic operable to issue a hint instruction based on the entitlement vector for usage in scheduling the resources. | 03-28-2013 |
20130081134 | Instruction set adapted for security risk monitoring - A processor is adapted to manage security risk by updating and monitoring a taint storage element in response to receipt of taint indicators, and responding to predetermined taint conditions detecting by the monitoring. The processor can be operable to execute instructions of a defined instruction set architecture and comprises an instruction of the instruction set architecture operable to access data from a source and operable to receive a taint indicator indicative of potential security risk associated with the data. The processor can further comprise a taint storage element operable for updating in response to receipt of the taint indicator and logic. The logic can be operable to update the taint storage element, process the taint storage element, determine a security risk condition based on the processing of the taint storage element, and respond to the security risk condition. | 03-28-2013 |
20130111489 | Entitlement vector for managing resource allocation | 05-02-2013 |
20130111491 | Entitlement vector with resource and/or capabilities fields | 05-02-2013 |
20130139262 | Taint injection and tracking - An embodiment or embodiments of an electronic device can comprise an input interface and a hardware component coupled to the input interface. The input interface can be operable to receive a plurality of taint indicators corresponding to at least one of a plurality of taints indicative of potential security risk which are injected from at least one of a plurality of resources. The hardware component can be operable to track the plurality of taints. | 05-30-2013 |
20140223141 | SHARING TLB MAPPINGS BETWEEN CONTEXTS - In some implementations, a processor may include a data structure, such as a translation lookaside buffer, that includes an entry containing first mapping information having a virtual address and a first context associated with a first thread. Control logic may receive a request for second mapping information having the virtual address and a second context associated with a second thread. The control logic may determine whether the second mapping information associated with the second context is equivalent to the first mapping information in the entry of the data structure. If the second mapping information is equivalent to the first mapping information, the control logic may associate the second thread with the first mapping information contained in the entry of the data structure to share the entry between the first thread and the second thread. | 08-07-2014 |
20150128262 | Taint vector locations and granularity - An embodiment or embodiments of a computing system can be adapted to manage security risk by accumulating and monitoring taint indications, and can respond to predetermined taint conditions detecting by the monitoring. An illustrative computing system can comprise a plurality of resources operationally coupled into the computing system, and at least one taint vector operable to list a plurality of taints indicative of potential security risk associated with a selected location and granularity of selected ones of the plurality of resources. | 05-07-2015 |
Patent application number | Description | Published |
20090027056 | Battery performance monitor - Improvements both in the methods whereby existing techniques for determining the condition of a battery are communicated to a user (for example, to the owner of a private vehicle, or to the service manager of a fleet of vehicles), or the vehicle's operating system, and in the methods for evaluating the condition of the battery are disclosed. It has been discovered by the inventors that the difference in internal resistance of a fully charged battery as measured during charging and as measured after charging is greater for a battery in poor condition than for a new battery. The invention relates in part to instruments and corresponding methods for evaluating the condition of a battery utilizing this discovery. | 01-29-2009 |
20140107976 | Tester for equipment, apparatus, or component with distributed processing function - A tester for equipment, apparatuses, or components with distributed measurement and analytical functions comprises a simplified test circuit for obtaining key data representative of the operational characteristics of said equipment, apparatus, or component and transmitting these to a sophisticated device capable of other uses, such as a smart phone or tablet computer. The latter analyzes the raw data with reference to values for nominal characteristics or operation of the equipment, apparatus, or component and provides a result indicative of the condition thereof. | 04-17-2014 |
20140374475 | Tester for equipment, apparatus or component with distributed processing function - A system and method for testing equipment, apparatuses, or components with distributed measurement and analytical functions. The system comprises a simplified test circuit for obtaining key data representative of the operational characteristics of said equipment, apparatus, or component and transmitting these to a sophisticated device capable of other uses, such as a smart phone or tablet computer. The latter analyzes the raw data with reference to values for nominal characteristics or operation of the equipment, apparatus, or component and provides a result indicative of the condition thereof, or may transmit the data over the Internet to a remote computer for performing the analysis. | 12-25-2014 |