Patent application number | Description | Published |
20090080270 | MEMORY DEVICE HAVING TERMINALS FOR TRANSFERRING MULTIPLE TYPES OF DATA - A memory device includes terminals for transferring input data and output data to and from a memory array. The memory device also includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information associated with the output data. The input and output auxiliary information include inverting codes, parity codes, temperature information and time delay information. The input and output auxiliary information are transferred to and from the memory device on the same terminals that the input data and the output data are transferred. | 03-26-2009 |
20090097340 | READ COMMAND TRIGGERED SYNCHRONIZATION CIRCUITRY - A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off. | 04-16-2009 |
20090231936 | MEMORY DEVICE HAVING STROBE TERMINALS WITH MULTIPLE FUNCTIONS - A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device and transfer output data from the memory device. The write strobe transceivers transfer timing information of the input data. The read strobe transceivers transfer timing information of the output data. The memory device also has an auxiliary circuit for generating auxiliary information. The auxiliary information includes information different from the timing information of the input data and the output data. The auxiliary circuit uses the write and read transceivers to transfer the auxiliary information to and from the memory device. | 09-17-2009 |
20090248970 | DUAL EDGE COMMAND - A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device. | 10-01-2009 |
20100027368 | READ COMMAND TRIGGERED SYNCHRONIZATION CIRCUITRY - A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off. | 02-04-2010 |
20100265777 | MEMORY DEVICE HAVING STROBE TERMINALS WITH MULTIPLE FUNCTIONS - A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device and transfer output data from the memory device. The write strobe transceivers transfer timing information of the input data. The read strobe transceivers transfer timing information of the output data. The memory device also has an auxiliary circuit for generating auxiliary information. The auxiliary information includes information different from the timing information of the input data and the output data. The auxiliary circuit uses the write and read transceivers to transfer the auxiliary information to and from the memory device. | 10-21-2010 |
20110255362 | READ COMMAND TRIGGERED SYNCHRONIZATION CIRCUITRY - A system having a processor, a memory controller coupled to said processor, a plurality of dynamic random access memory (DRAM) chips coupled to said memory controller and at least one of said DRAM chips comprising a clock synchronization circuit to receive a reference clock signal and to output a synchronized clock output signal. The system has a plurality of signal buses coupling the processor to the memory controller and the memory controller to said DRAM chips. The signal line conveys signals from said memory controller to said clock synchronization circuit to turn on and off the clock synchronization circuit according to control logic. A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off. | 10-20-2011 |