Patent application number | Description | Published |
20080239806 | NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING - Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number of program states. The method includes determining whether the Vt of each of the cells has reached a pre-verify voltage (PVFY) associated with the program state, selectively biasing bit lines coupled to those cells whose Vt has reached the PVFY, adjusting the PVFY to a different level, and selectively biasing bit lines coupled to cells whose Vt has reached the adjusted PVFY, wherein the PVFY and the adjusted PVFY are less than the VFY. | 10-02-2008 |
20080266953 | SINGLE LATCH DATA CIRCUIT IN A MULTIPLE LEVEL CELL NON-VOLATILE MEMORY DEVICE - A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on. | 10-30-2008 |
20090135650 | COMPENSATION OF BACK PATTERN EFFECT IN A MEMORY DEVICE - In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation. | 05-28-2009 |
20100085807 | SINGLE LATCH DATA CIRCUIT IN A MULTIPLE LEVEL CELL NON-VOLATILE MEMORY DEVICE - A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on. | 04-08-2010 |
20100091582 | ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING - Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line. | 04-15-2010 |
20110063920 | SENSING FOR ALL BIT LINE ARCHITECTURE IN A MEMORY DEVICE - Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells of the first selected word line is complete, the precharge voltage is maintained on the bit lines while a second word line is selected. | 03-17-2011 |
20110134701 | MEMORY KINK COMPENSATION - This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude. | 06-09-2011 |
20110194350 | COMPENSATION OF BACK PATTERN EFFECT IN A MEMORY DEVICE - In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation. | 08-11-2011 |
20120176843 | MEMORIES AND METHODS OF PROGRAMMING MEMORIES - Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper limit is determined after a single programming pulse for lower page programming, and upper page programming start voltages are adjusted based on the determined upper limit of the threshold voltage distribution. | 07-12-2012 |
20120206974 | SENSING FOR ALL BIT LINE ARCHITECTURE IN A MEMORY DEVICE - Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells of the first selected word line is complete, the precharge voltage is maintained on the bit lines while a second word line is selected. | 08-16-2012 |
20120262993 | SENSING SCHEME IN A MEMORY DEVICE - Methods of operating memory devices, generating reference currents in memory devices, and sensing data states of memory cells in a memory device are disclosed. One such method includes generating reference currents utilized in sense amplifier circuitry to manage leakage currents while performing a sense operation within a memory device. Another such method activates one of two serially coupled transistors along with activating and deactivating the second transistor serially coupled with the first transistor thereby regulating a current through both serially coupled transistors and establishing a particular reference current. | 10-18-2012 |
20120269011 | VOLTAGE SWITCHING IN A MEMORY DEVICE - Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage. | 10-25-2012 |
20120287726 | ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING - Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line. | 11-15-2012 |
20130039129 | MEMORY DEVICES AND CONFIGURATION METHODS FOR A MEMORY DEVICE - Memory devices and methods of operating memory devices are disclosed. In one such method, different blocks of memory cells have different configurations of user data space and overhead data space. In at least one method, overhead data is distributed within more than one block of memory cells. In another method, blocks are reconfigurable responsive to particular operating modes and/or desired levels of reliability of user data stored in a memory device. | 02-14-2013 |
20130051141 | THRESHOLD VOLTAGE COMPENSATION IN A MULTILEVEL MEMORY - Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. | 02-28-2013 |
20130058164 | MEMORY APPARATUS, SYSTEMS, AND METHODS - Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided. | 03-07-2013 |
20130188427 | COMPENSATION OF BACK PATTERN EFFECT IN A MEMORY DEVICE - In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation. | 07-25-2013 |
20130215688 | VOLTAGE SWITCHING IN A MEMORY DEVICE - Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage. | 08-22-2013 |
20130227203 | DYNAMIC SLC/MLC BLOCKS ALLOCATIONS FOR NON-VOLATILE MEMORY - Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode. | 08-29-2013 |
20130272071 | DETERMINING SOFT DATA FOR COMBINATIONS OF MEMORY CELLS - The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and a second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells. | 10-17-2013 |
20140133224 | ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING - Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line. | 05-15-2014 |
20140133226 | ERASING PHYSICAL MEMORY BLOCKS OF NON-VOLATILE MEMORY - Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode. | 05-15-2014 |
20140321207 | DETERMINING SOFT DATA FOR COMBINATIONS OF MEMORY CELLS - The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells, wherein the array includes a first memory cell and a second memory cell, wherein the first and second memory cells are each programmable to one of a number of program states, and wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states. A number of embodiments also include a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and determine soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program state of the first memory cell and the soft data associated with the program state of the second memory cell. | 10-30-2014 |
20150033096 | MEMORY DEVICES AND CONFIGURATION METHODS FOR A MEMORY DEVICE - A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells in a first configuration comprising one or more groups of overhead data memory cells, and to configure a second block of memory cells in a second configuration comprising one or more groups of user data memory cells and at least one group of overhead data memory cells. The first configuration is different than the second configuration. At least one group of overhead data memory cells of the second block of memory cells comprises a different storage capacity than at least one group of overhead data memory cells of the first block of memory cells. | 01-29-2015 |
20150063031 | DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE - A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programing operation performed on the memory device is performed and before a subsequent portion of the particular programing operation performed on the memory device is performed. The controller is configured to determine the program window responsive to an amount of program disturb experienced by a particular state of a memory cell. The controller is configured to perform the subsequent portion of the particular programing operation performed on the memory device using the determined program window. | 03-05-2015 |
20150220344 | Memory Systems and Memory Control Methods - Memory systems and memory control methods are described. According to one aspect, a memory system includes a plurality of memory cells individually configured to store data, program memory configured to store a plurality of first executable instructions which are ordered according to a first instruction sequence and a plurality of second executable instructions which are ordered according to a second instruction sequence, substitution circuitry configured to replace one of the first executable instructions with a substitute executable instruction, and a control unit configured to execute the first and second executable instructions to control reading and writing of the data with respect to the memory, wherein the control unit is configured to execute the first executable instructions according to the first instruction sequence, to execute the substitute executable instruction after the execution of the first executable instructions, and to execute the second executable instructions according to the second instruction sequence as a result of execution of the substitute executable instruction. | 08-06-2015 |
20150243351 | THRESHOLD VOLTAGE COMPENSATION IN A MEMORY - Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. | 08-27-2015 |
Patent application number | Description | Published |
20090080253 | DEVICE, SYSTEM, AND METHOD OF BIT LINE SELECTION OF A FLASH MEMORY - Device, system, and method of bit line selection of a flash memory. In some demonstrative embodiments, the method may include connecting to ground at least one location along at least one bit line of a flash memory when the bit line is at an unselected state, wherein the bit line is connected to a multiplexer, and wherein at least one memory sector is coupled to the bit line between the multiplexer and the location; and connecting the location to a precharge path when the bit line is at a selected state. Other embodiments are described and claimed. | 03-26-2009 |
20100122016 | DYNAMIC SLC/MLC BLOCKS ALLOCATIONS FOR NON-VOLATILE MEMORY - Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode. | 05-13-2010 |
20100165739 | NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING - Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number of program states. The method includes determining whether the Vt of each of the cells has reached a pre-verify voltage (PVFY) associated with the program state, selectively biasing bit lines coupled to those cells whose Vt has reached the PVFY, adjusting the PVFY to a different level, and selectively biasing bit lines coupled to cells whose Vt has reached the adjusted PVFY, wherein the PVFY and the adjusted PVFY are less than the VFY. | 07-01-2010 |
20120307564 | METHOD FOR KINK COMPENSATION IN A MEMORY - This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude. | 12-06-2012 |
20140043912 | METHOD FOR KINK COMPENSATION IN A MEMORY - This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude. | 02-13-2014 |