Patent application number | Description | Published |
20090124192 | Hiding structure of a vent pipe for a mobile air conditioner - A hiding structure of a vent pipe for a mobile air conditioner is composed of a housing, a cold air outlet for blowing the cold air into a room, and a hot air outlet for expelling the hot air out of the room. The hot air outlet is disposed with an extractable vent pipe which is collected in the housing of the mobile air conditioner, the housing is disposed with a connector opening from which the vent pipe can be extended, and the connector opening is disposed with a vent pipe cap. As the extractable vent pipe is used by the present invention, a volume of the mobile air conditioner is decreased, and convenience in moving is increased. | 05-14-2009 |
20100230078 | EXHAUST PIPE OF AN AIR CONDITIONER - The present invention discloses an exhaust pipe of an air conditioner. The air conditioner includes a condenser, a first pipe, an air duct and a second pipe. The condenser is located in the air conditioner, an end of the first pipe is close to the condenser, the other end is penetrated out of a side of the condenser, and an interior of the first pipe is provided with the second pipe. An end of the second pipe is connected with the air duct (the air duct is located in the air conditioner), and the other end is penetrated out of the first pipe. Therefore, when the air conditioner is running, hot air is sucked into the condenser through the first pipe and then the circulated hot air is sent out of a room from the second pipe through the air duct, such that indoor temperature can be reduced effectively. | 09-16-2010 |
20110094260 | ROLLER EVAPORATOR FOR A SNOW MACHINE - A roller evaporator for a snow machine includes an inner layer and an outer layer. The inner layer is fixed on a high pressure tube and a low pressure tube, and the outer layer corresponds to and rotates relatively with respect to the inner layer. A roller of the roller evaporator is divided into two layers, with the inner layer being installed and sealed on the high pressure tube. Therefore, an extremely good sealing effect is provided and refrigerant does leak out easily while making ice. | 04-28-2011 |
Patent application number | Description | Published |
20120119375 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - In a manufacturing method of a semiconductor structure, a substrate having a front surface and a back surface is provided. The front surface has a device layer thereon and conductive plugs electrically connected to the device layer. A thinning process is performed on the back surface of the substrate, such that the back surface of the substrate and surfaces of the conductive plugs have a distance therebetween. Holes are formed in the substrate from the back surface to the conductive plugs, so as to form a porous film. An oxidization process is performed, such that the porous film correspondingly is reacted to form an oxide material layer. A polishing process is performed on the oxide material layer to expose the surfaces of the conductive plugs. | 05-17-2012 |
20120127625 | TRENCH CAPACITOR STRUCTURES AND METHOD OF MANUFACTURING THE SAME - A trench capacitor structure is provided. The trench capacitor structure includes a substrate, a trench formed in the substrate, a plurality of scallops formed in the sidewalls of the trench, and at least one capacitor formed within at least one of the scallops. The disclosure also provides a method of manufacturing the trench capacitor structure. | 05-24-2012 |
20120133030 | TSV SUBSTRATE STRUCTURE AND THE STACKED ASSEMBLY THEREOF - The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively. | 05-31-2012 |
20120139105 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor structure includes providing a substrate having an upper surface and a bottom surface. First openings are formed in the substrate. An oxidization process is performed to oxidize the substrate having the first openings therein to form an oxide-containing material layer, and the oxide-containing material layer has second openings therein. A conductive material is filled into the second openings to form conductive plugs. A first device layer is formed a first surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. A second device layer is formed on a second surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. | 06-07-2012 |
20120142184 | MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE - A manufacturing method of a semiconductor structure includes providing a substrate having an upper surface and a bottom surface. First openings are formed in the substrate. An oxidization process is performed to oxidize the substrate having the first openings therein to form an oxide-containing material layer, and the oxide-containing material layer has second openings therein. A conductive material is filled into the second openings to form conductive plugs. A first device layer is formed a first surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. A second device layer is formed on a second surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. | 06-07-2012 |
20120322249 | MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE - In a manufacturing method of a semiconductor structure, a substrate having a front surface and a back surface is provided. The front surface has a device layer thereon and conductive plugs electrically connected to the device layer. A thinning process is performed on the back surface of the substrate, such that the back surface of the substrate and surfaces of the conductive plugs have a distance therebetween. Holes are formed in the substrate from the back surface to the conductive plugs, so as to form a porous film. An oxidization process is performed, such that the porous film correspondingly is reacted to form an oxide material layer. A polishing process is performed on the oxide material layer to expose the surfaces of the conductive plugs. | 12-20-2012 |
20130161825 | THROUGH SUBSTRATE VIA STRUCTURE AND METHOD FOR FABRICATING THE SAME - A through substrate via (TSV) structure is provided, including: a substrate; an opening formed in a portion of the semiconductor substrate; a dielectric layer formed on the sidewall of the opening; a conductive pillar formed inside the opening; and at least a portion of the dielectric layer is removed to form void. Also provided is a method for fabricating a through substrate via (TSV) structure. | 06-27-2013 |
20130214390 | TSV SUBSTRATE STRUCTURE AND THE STACKED ASSEMBLY THEREOF - The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively. | 08-22-2013 |
20130270713 | DUAL DAMASCENE STRUCTURE HAVING THROUGH SILICON VIA AND MANUFACTURING METHOD THEREOF - A dual damascene structure having a through silicon via and a manufacturing method thereof are provided. The method includes forming a first, a second, and a third dielectric layers a on a substrate having a conductive structure. A trench is formed in the third dielectric layer. A hard mask layer is formed on the third dielectric layer and a surface of the trench. A first opening having a tapered sidewall is formed in the hard mask layer. A second opening is formed in the second and the third dielectric layers. The substrate exposed by the second opening and the first opening is etched to form a through hole so as to form a dual damascene opening. A liner layer is formed on a surface of the dual damascene opening and the conductive structure is exposed. The dual damascene opening is filled with a conductive material. | 10-17-2013 |
20140008652 | THROUGH-SUBSTRATE VIA STRUCTURE - A through-substrate via structure including a substrate, a conductive layer, and a parasitic capacitance modulation layer is provided. The substrate has at least one opening. The opening is filled with the conductive layer. The parasitic capacitance modulation layer is disposed between the conductive layer and the substrate. The parasitic capacitance modulation layer is placed around the through-substrate via to reduce the depletion capacitance and further reduce the parasitic capacitance of the through-substrate via. Therefore, during transmission of signals with high frequency, the parasitic capacitance around the through-substrate via is rather small and thereby the operation speed of devices is increased. | 01-09-2014 |
20140008800 | METHOD FOR MANUFACTURING THROUGH SUBSTRATE VIA (TSV), STRUCTURE AND CONTROL METHOD OF TSV CAPACITANCE - A method for manufacturing a through substrate via (TSV) structure, a TSV structure, and a control method of a TSV capacitance are provided. The method for manufacturing the TSV structure includes: providing a substrate having a first surface and a second surface; forming a trench in the first surface of the substrate; filling a low resistance material into the trench; forming an insulating layer on the first surface of the substrate; forming at least one opening in the first surface of the substrate, wherein the opening is located differently the trench; forming an oxide liner layer, a barrier layer and a conductive seed layer on a sidewall and a bottom of the opening and on the insulating layer of the first surface; and filling a conductive material into the opening, wherein the opening is used to form at least one via. | 01-09-2014 |
20140175614 | WAFER STACKING STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A wafer stacking structure includes a first wafer and a second wafer. The first wafer includes a first through silicon via (TSV) opening and a first TSV filling portion formed in the first TSV opening and including a concave structure. The second wafer includes a second TSV opening and a second TSV filling portion formed in the second TSV opening and including a convex structure. A front surface of the first wafer faces a front surface of the second wafer, and the convex structure of the second TSV filling portion is inserted into the concave structure of the first TSV filling portion. | 06-26-2014 |
20140175655 | CHIP BONDING STRUCTURE AND MANUFACTURING METHOD THEREOF - A chip bonding structure at least includes a first substrate, a second substrate opposite to the first substrate, and a copper bonding structure sandwiched in between the first and the second substrates. A Cu—Cu bonding interface is within the copper bonding structure and is characterized with combinations of protrusions and recesses, and the copper crystallization orientation at one side of the Cu—Cu bonding interface is different from that at another side. | 06-26-2014 |
20140238725 | METHOD OF FLATTENING SURFACE OF CONDUCTIVE STRUCTURE AND CONDUCTIVE STRUCTURE WITH FLATTENED SURFACE - A method of flattening surface of conductive structure including a substrate, a dielectric layer on the substrate, and a conductive line formed in the dielectric layer is provided. A surface of the conductive line has a recess. A cover layer is formed on the substrate. A mechanical polishing process is performed to remove a portion of the cover layer. A remaining cover layer fills and levels the recess. | 08-28-2014 |
20140346666 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes following steps. A mould is provided. The mould has a chamber and a plurality of protrusions in the chamber. A thermosetting material is injected into the chamber. The thermosetting material is cured. A parting step is performed to separate the cured thermosetting material from the mould, so as to form an interposer substrate. A plurality of blind holes corresponding to the protrusions is formed on the interposer substrate. A conductive material is filled into the blind holes to form a plurality of conductive pillars. A conductive pattern layer is formed on a surface of the interposer substrate. The conductive pattern layer is electrically connected with the conductive pillars. | 11-27-2014 |
20150155204 | TSV SUBSTRATE STRUCTURE AND THE STACKED ASSEMBLY THEREOF - The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively. | 06-04-2015 |
20150294953 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device is provided. First, a mould is provided. The mould has a chamber, patterns in the chamber, and protrusions in the chamber. A carrier substrate having at least one die located thereon is disposed in the chamber, and the protrusions surround the die. A thermosetting material is injected into the chamber and is cured. The cured thermosetting material is separated from the mould, so as to form an interposer substrate. A plurality of through holes corresponding to the protrusions and a plurality of grooves corresponding to the patterns are formed on the interposer substrate. A conductive material is filled into the through holes and the grooves to form a plurality of conductive pillars and a first conductive pattern layer on a first surface of the interposer substrate. The first conductive pattern layer is electrically connected with the conductive pillars. | 10-15-2015 |
Patent application number | Description | Published |
20080233486 | System and Method for Providing Phase Shift Mask Passivation Layer - System and method for providing a passivation layer for a phase shift mask (“PSM”) are described. In one embodiment, a PSM comprises a transparent substrate; a phase shift pattern disposed on the transparent substrate; and a passivation layer disposed to substantially cover exposed surfaces of at least a portion of the phase shift pattern. | 09-25-2008 |
20090206057 | Method To Improve Mask Critical Dimension Uniformity (CDU) - A method and system for fabricating a substrate is disclosed. First, a plurality of process chambers are provided, at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate and at least one of the plurality of process chambers containing a plasma filtering plate library. A plasma filtering plate is selected and removed from the plasma filtering plate library. Then, the plasma filtering plate is inserted into at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate. Subsequently, an etching process is performed in the substrate. | 08-20-2009 |
20090222785 | METHOD FOR SHAPE AND TIMING EQUIVALENT DIMENSION EXTRACTION - An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout. | 09-03-2009 |
20090258159 | NOVEL TREATMENT FOR MASK SURFACE CHEMICAL REDUCTION - A method includes forming an absorption material layer on a mask; applying a plasma treatment to the mask to reduce chemical contaminants after the forming of the absorption material layer; performing a chemical cleaning process of the mask; and performing a gas injection to the mask. | 10-15-2009 |
20100095253 | TABLE-BASED DFM FOR ACCURATE POST-LAYOUT ANALYSIS - Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data. | 04-15-2010 |
20100293514 | DESIGN-DRIVEN METAL CRITICAL DIMENSION (CD) BIASING - A method of designing an integrated circuit (“IC”) is provided that includes placing an IC design, where the IC design includes a first element, a second element, and a path coupling the first and second elements, and routing the IC design. Further, the method includes obtaining at least one of resistivity data and capacitance data related to the path, and obtaining timing data related to the path. The method also includes using at least one of the resistivity data, the capacitance data, and the timing data to determine a critical dimension (“CD”) bias to be applied to the path, and modifying the IC design, where modifying includes applying the CD bias to the path. | 11-18-2010 |
20110217630 | INTENSITY SELECTIVE EXPOSURE PHOTOMASK - An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material. | 09-08-2011 |
20110289466 | Table-Based DFM for Accurate Post-Layout Analysis - Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data. | 11-24-2011 |
20120040278 | INTENSITY SELECTIVE EXPOSURE PHOTOMASK - An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. | 02-16-2012 |
20120146159 | STRUCTURE AND METHOD FOR OVERLAY MARKS - The overlay mark and method for making the same are described. In one embodiment, a semiconductor overlay structure includes gate stack structures formed on the semiconductor substrate and configured as an overlay mark, and a doped semiconductor substrate disposed on both sides of the gate stack structure that includes at least as much dopant as the semiconductor substrate adjacent to the gate stack structure in a device region. The doped semiconductor substrate is formed by at least three ion implantation steps. | 06-14-2012 |
20140170537 | METHOD OF DEFINING AN INTENSITY SELECTIVE EXPOSURE PHOTOMASK - An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern. | 06-19-2014 |
20150056724 | INTEGRATED CIRCUIT LAYOUT AND METHOD WITH DOUBLE PATTERNING - The present disclosure provides one embodiment of a method for an integrated circuit (IC). The method includes forming a mandrel pattern on a substrate by a first lithography process; forming a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; forming a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the substrate using the second spacer pattern as an etch mask. | 02-26-2015 |
Patent application number | Description | Published |
20090030631 | METHOD FOR ENHANCING THE MEASUREMENT CAPABILITY OF MULTI-PARAMETER INSPECTION SYSTEMS - A method for improving the measurement capability of multi-parameter inspection systems includes performing a measuring procedure to acquire a measured signature of a sample, calculating weighting factors representing a correlation between structural parameters of the sample by using a weighting algorithm, transforming the weighting factors into a sampling function by using a transforming rule, updating the measured signature to form an updated measured signature and generating a plurality of updated nominal signatures according to the sampling function, and comparing the updated measured signature and the updated nominal signatures to determine the structural parameters of the sample. | 01-29-2009 |
20090079969 | Method and apparatus for scatterfield microscopical measurement - A method and an apparatus are disclosed for scatterfield microscopical measurement. The method integrates a scatterometer and a bright-field microscope for enabling the measurement precision to be better than the optical diffraction limit. With the aforesaid method and apparatus, a detection beam is generated by performing a process on a uniform light using an LCoS (liquid crystal on silicon) or a DMD (digital micro-mirror device) which is to directed to image on the back focal plane of an object to be measured, and then scattered beams resulting from the detection beam on the object's surface are focused on a plane to form an optical signal which is to be detected by an array-type detection device. The detection beam can be oriented by the modulation device to illuminate on the object at a number of different angles, by which zero order or higher order diffraction intensities at different positions of the plane at different incident angles can be collected. | 03-26-2009 |
20090116035 | Structure and method for overlay measurement - A structure for overlay measurement is provided in the present invention, using the diffraction characteristics on the boundary portion between two microstructures formed on each of two material layers. The optical intensity distribution on the boundary portion between microstructures formed on the two overlaid material layers respectively are measured by an optical microscope to obtain the overlay error between the two overlaid material layers. In addition, the present invention also provides a method for overlay measurement using the structure for overlay measurement, wherein a merit relation based on the optical intensity distribution on the boundary portion between different microstructures is determined. The merit relation can be used to analyze the overlay error to improve the efficiency and accuracy of on-line error measurement. | 05-07-2009 |
20090313589 | METHOD FOR DESIGNING OVERLAY TARGETS AND METHOD AND SYSTEM FOR MEASURING OVERLAY ERROR USING THE SAME - A method for designing an overlay target comprises selecting a plurality of overlay target pairs having different overlay errors or offsets, calculating a deviation of the simulated diffraction spectrum for each overlay target pair, selecting a plurality of sensitive overlay target pairs by taking the deviation of the simulated diffraction spectrum into consideration, selecting an objective overlay target pair from the sensitive overlay target pairs by taking the influence of the structural parameters to the simulated diffraction spectrum into consideration, and designing the overlay target pair based on the structural parameter of the objective overlay target pair. | 12-17-2009 |
20100007881 | SCATTERFIELD MICROSCOPICAL MEASURING METHOD AND APPARATUS - The present invention provides a scatterfield microscopical measuring method and apparatus, which combine scatterfield detecting technology into microscopical device so that the microscopical device is capable of measuring the sample whose dimension is under the limit of optical diffraction. The scatterfield microscopical measuring apparatus is capable of being controlled to focus uniform and collimated light beam on back focal plane of an objective lens disposed above the sample. By changing the position of the focus position on the back focal plane, it is capable of being adjusted to change the incident angle with respect to the sample. | 01-14-2010 |
20100053627 | REFLECTIVE SCATTEROMETER - A reflective scatterometer capable of measuring a sample is provided. The reflective scatterometer includes a paraboloid mirror, a light source, a first reflector, a second reflector and a detector. The paraboloid mirror has an optical axis and a parabolic surface, wherein the sample is disposed on the focal point of the parabolic surface and the normal direction of the sample is parallel with the optical axis. A collimated beam generated from the light source is reflected by the first reflector to the parabolic surface and then is reflected by the parabolic surface to the sample to form a first diffracted beam. The first diffracted beam is reflected by the parabolic surface to the second reflector and is then reflected by the second reflector to the detector. | 03-04-2010 |
20110131538 | METHOD FOR DESIGNING TWO-DIMENSIONAL ARRAY OVERLAY TARGETS AND METHOD AND SYSTEM FOR MEASURING OVERLAY ERRORS USING THE SAME - A method for designing a two-dimensional array overlay target comprises the steps of: selecting a plurality of two dimensional array overlay targets having different overlay errors; calculating a deviation of a simulated diffraction spectrum for each two-dimensional array overlay target; selecting an error-independent overlay target by taking the deviations of the simulated diffraction spectra into consideration; and designing a two dimensional array overlay target based on structural parameters of the error-independent overlay target. | 06-02-2011 |
20110154272 | METHOD FOR DESIGNING TWO-DIMENSIONAL ARRAY OVERLAY TARGET SETS AND METHOD AND SYSTEM FOR MEASURING OVERLAY ERRORS USING THE SAME - A method for designing a two-dimensional array overlay target set comprises the steps of: selecting a plurality of two-dimensional array overlay target sets having different overlay errors; calculating a deviation of a simulated diffraction spectra for each two-dimensional array overlay target set; selecting a sensitive overlay target set by taking the deviations of the simulated diffraction spectra into consideration; and designing a two-dimensional array overlay target set based on the structural parameters of the sensitive overlay target set. | 06-23-2011 |
20110172974 | SYSTEM AND METHOD FOR VIA STRUCTURE MEASUREMENT - A system for via structure measurement is disclosed. The system comprises a reflectometer, a simulation unit and a comparing unit. The reflectometer is configured to collect a measured diffraction spectrum of at least a via. The simulation unit is configured to provide simulated diffraction spectrums of the at least a via. The comparing unit is configured to determine at least a depth and at least a bottom profile of the at least a via by comparing the collected diffraction spectrum and the simulated diffraction spectrums. | 07-14-2011 |
20110320986 | METHOD FOR DESIGNING OVERLAY TARGETS AND METHOD AND SYSTEM FOR MEASURING OVERLAY ERROR USING THE SAME - A method for designing an overlay target comprises selecting a plurality of overlay target pairs having different overlay errors or offsets, calculating a deviation of the simulated diffraction spectrum for each overlay target pair, selecting a plurality of sensitive overlay target pairs by taking the deviation of the simulated diffraction spectrum into consideration, selecting an objective overlay target pair from the sensitive overlay target pairs by taking the influence of the structural parameters to the simulated diffraction spectrum into consideration, and designing the overlay target pair based on the structural parameter of the objective overlay target pair. | 12-29-2011 |
20120147171 | METHOD FOR MEASURING VIA BOTTOM PROFILE - A method for measuring a via bottom profile is disclosed for obtaining a profile of a bottom of a via in a front side of a substrate. In this method, an infrared (IR) light source is transmitted from the back of the substrate to the bottom of the via through an objective by using an IR-microscope, and lights scattered from the bottom of the via are acquired by an image capturing device to generate an image, where the image displays a diameter ( | 06-14-2012 |
20120197592 | SYSTEM, METHOD AND COMPUTER READABLE MEDIUM FOR THROUGH SILICON VIA STRUCTURE MEASUREMENT - A system for through silicon via (TSV) structure measurement comprises a reflectometer, and a computing unit. The reflectometer emits a broadband light beam to at least a TSV structure and receives a reflection spectrum of at least a TSV structure. The computing unit is coupled with the reflectometer and determines the depth of the TSV structure in accordance with the reflection spectrum. | 08-02-2012 |
20120290239 | THIN METAL FILM MEASUREMENT METHOD - A thin metal film measurement method is disclosed. The method includes the following steps. A respective capacitance is measured before and after a thin metal film is formed. The thickness of the thin metal film is calculated according to the variation of the capacitance. In an embodiment, the capacitance is measured respectively by a capacitance measuring module before and after the thin metal film is formed so as to calculate the thickness of the thin metal film. In another embodiment, a pair of capacitance measuring modules opposite at up and down sides is applied to measure the capacitance before and after the thin metal film is formed so as to calculate the thickness of the thin metal film. | 11-15-2012 |
20140085640 | MEASUREMENT SYSTEMS AND MEASUREMENT METHODS - A measurement system is provided to measure a hole of a target, including a light source generation unit, a capturing unit and a processing unit. The light source generation unit generates a light source and focuses the light source on a plurality of different height planes. The capturing unit captures a plurality of images scattered from the plurality of different height planes. The processing unit obtains boundaries of the hole on the plurality of different height planes according to the plurality of images, samples image intensities of different azimuth angles on the boundaries of the hole on each of the plurality of different height planes to generate a plurality of sampling values, and develops a sidewall image of the hole according to the plurality of sampling values, the plurality of different height planes and the different azimuth angles. | 03-27-2014 |
20140333936 | THICKNESS MEASURING SYSTEM AND METHOD FOR A BONDING LAYER - In a thickness measuring system for a bonding layer according to an exemplary embodiment, an optical element changes the wavelength of a first light source to enable at least one second light source propagating through a bonding layer to be incident to an object, wherein the bonding layer has an upper interface and a lower interface that are attached to the object; and an optical image capturing and analysis unit receives a plurality of reflected lights from the upper and the lower interfaces to capture a plurality of interference images of different wavelengths, and analyzes the intensity of the plurality of interference images to compute the thickness information of the bonding layer. | 11-13-2014 |