Patent application number | Description | Published |
20090078940 | Location-controlled crystal seeding - A structure with location-controlled crystallization of an active semiconductor film using a crystal seed has been provided, along with an associated fabrication method. The method forms a first semiconductor film overlying a substrate having a crystallographic orientation. Typically, the structure is polycrystalline or single-crystal. The first semiconductor film is selectively etched, forming a seed region. An insulator is formed with an opening, exposing the seed region. An amorphous second semiconductor film is formed over the insulator layer. The second semiconductor film is laser annealed, partially melting the seed region. Crystal grains are laterally grown in the second semiconductor film having the same crystallographic orientation as the seed region. In TFT fabrication an etching is typically performed to remove the second semiconductor film overlying the seed region, and a transistor active region is formed in the remaining second semiconductor film. | 03-26-2009 |
20090250700 | Crystalline Semiconductor Stripe Transistor - A transistor with crystalline semiconductor stripes and an associated fabrication process are provided. The method provides a substrate, and deposits a semiconductor layer overlying the substrate. The semiconductor layer is irradiated using a scanning step-and-repeat laser annealing process, which agglomerates portions of the semiconductor layer. In response to cooling agglomerated semiconductor material, a transistor active semiconductor region is formed including a plurality of crystalline semiconductor stripes oriented along parallel axes. In one aspect, a channel region is formed from the plurality of oriented crystalline semiconductor stripes, and the method forms a gate dielectric overlying the channel region, with a gate electrode overlying the gate dielectric. In another aspect, forming the transistor active semiconductor region includes forming source, drain, and channel regions from the plurality of oriented crystalline semiconductor stripes. | 10-08-2009 |
20090250791 | Crystalline Semiconductor Stripes - Crystalline semiconductor stripes and an associated fabrication process are provided. The method provides an insulator substrate, and deposits a semiconductor layer overlying the insulator substrate. The semiconductor layer is irradiated using a scanning step-and-repeat laser annealing process, which agglomerates portions of the semiconductor layer. In response to cooling agglomerated semiconductor material, oriented crystalline semiconductor stripes are formed on the insulator substrate. The crystalline semiconductor stripes are aligned approximately with a straight line stripe axis overlying a top surface of the insulating substrate. Each crystalline semiconductor stripe includes a plurality of consecutive ring segments aligned with the stripe axis. The rings segments have a width about equal to the laser annealing process step distance. The crystalline semiconductor stripes typically have a top surface shape of a truncated cylinder or a parabolic cross section. | 10-08-2009 |
20100102323 | Directionally Annealed Silicon Film Having a (100)-Normal Crystallographical Orientation - A method is provided for forming a directionally crystallized (100)-normal crystallographic orientation silicon (Si) film. The method provides a substrate including Si. An amorphous Si (a-Si) layer is formed overlying the substrate, and a silicon oxide cap layer is formed overlying the a-Si layer. In response to scanning a laser in a first direction along a top surface of the silicon oxide cap layer, the a-Si layer is transformed into a crystalline Si film having a (100)-normal crystallographic orientation, with crystal grains elongated in the first direction. That is, the crystalline Si film has grain boundaries between crystal grains, aligned in parallel with the first direction. | 04-29-2010 |
20110068342 | Laser Process for Minimizing Variations in Transistor Threshold Voltages - A laser method is provided for minimizing variations in transistor threshold voltages. The method supplies a wafer with a laser-crystallized active semiconductor film having a top surface with a first surface roughness. The method laser anneals the active semiconductor film, and in response to the laser annealing, melts the top surface of the active semiconductor film. The result is a top surface with a second roughness, less than the first roughness. More explicitly, the wafer active semiconductor film is crystallized using a laser with a first fluence, and then laser annealed with a second fluence, less than the first fluence. As compared with complementary metal-oxide-semiconductor field-effect (CMOSFET) thin-film transistor (TFT) structures formed in unprocessed regions of the active semiconductor film, the TFT threshold voltage standard deviation for TFTs in laser annealed portions of the active film are 60% less for n-channel and 30% less for p-channel TFTs. | 03-24-2011 |
Patent application number | Description | Published |
20090173948 | UNIFORM LARGE-GRAINED AND GRAIN BOUNDARY LOCATION MANIPULATED POLYCRYSTALLINE THIN FILM SEMICONDUCTORS FORMED USING SEQUENTIAL LATERAL SOLIDIFICATION AND DEVICES FORMED THEREON - Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed. In one preferred arrangement, a method includes the steps of generating a sequence of excimer laser pulses, controllably modulating each excimer laser pulse in the sequence to a predetermined fluence, homoginizing each modulated laser pulse in the sequence in a predetermined plane, masking portions of each homoginized fluence controlled laser pulse in the sequence with a two dimensional pattern of slits to generate a sequence of fluence controlled pulses of line patterned beamlets, each slit in the pattern of slits being sufficiently narrow to prevent inducement of significant nucleation in region of a silicon thin film sample irradiated by a beamlet corresponding to the slit, irradiating an amorphous silicon thin film sample with the sequence of fluence controlled slit patterned beamlets to effect melting of portions thereof corresponding to each fluence controlled patterned beamlet pulse in the sequence of pulses of patterned beamlets, and controllably sequentially translating a relative position of the sample with respect to each of the fluence controlled pulse of slit patterned beamlets to thereby process the amorphous silicon thin film sample into a single or polycrystalline silicon thin film. | 07-09-2009 |
20090189164 | UNIFORM LARGE-GRAINED AND GRAIN BOUNDARY LOCATION MANIPULATED POLYCRYSTALLINE THIN FILM SEMICONDUCTORS FORMED USING SEQUENTIAL LATERAL SOLIDIFICATION AND DEVICES FORMED THEREON - Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed. In one preferred arrangement, a method includes the steps of generating a sequence of excimer laser pulses, controllably modulating each excimer laser pulse in the sequence to a predetermined fluence, homoginizing each modulated laser pulse in the sequence in a predetermined plane, masking portions of each homoginized fluence controlled laser pulse in the sequence with a two dimensional pattern of slits to generate a sequence of fluence controlled pulses of line patterned beamlets, each slit in the pattern of slits being sufficiently narrow to prevent inducement of significant nucleation in region of a silicon thin film sample irradiated by a beamlet corresponding to the slit, irradiating an amorphous silicon thin film sample with the sequence of fluence controlled slit patterned beamlets to effect melting of portions thereof corresponding to each fluence controlled patterned beamlet pulse in the sequence of pulses of patterned beamlets, and controllably sequentially translating a relative position of the sample with respect to each of the fluence controlled pulse of slit patterned beamlets to thereby process the amorphous silicon thin film sample into a single or polycrystalline silicon thin film. | 07-30-2009 |
20100032586 | Uniform Large-Grained And Grain Boundary Location Manipulated Polycrystalline Thin Film Semiconductors Formed Using Sequential Lateral Solidification And Devices Formed Thereon - Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed. In one preferred arrangement, a method includes the steps of generating a sequence of excimer laser pulses, controllably modulating each excimer laser pulse in the sequence to a predetermined fluence, homogenizing each modulated laser pulse in the sequence in a predetermined plane, masking portions of each homogenized fluence controlled laser pulse in the sequence with a two dimensional pattern of slits to generate a sequence of fluence controlled pulses of line patterned beamlets, each slit in the pattern of slits being sufficiently narrow to prevent inducement of significant nucleation in region of a silicon thin film sample irradiated by a beamlet corresponding to the slit, irradiating an amorphous silicon thin film sample with the sequence of fluence controlled slit patterned beamlets to effect melting of portions thereof corresponding to each fluence controlled patterned beamlet pulse in the sequence of pulses of patterned beamlets, and controllably sequentially translating a relative position of the sample with respect to each of the fluence controlled pulse of slit patterned beamlets to thereby process the amorphous silicon thin film sample into a single or polycrystalline silicon thin film. | 02-11-2010 |
20130009074 | UNIFORM LARGE-GRAINED AND GRAIN BOUNDARY LOCATION MANIPULATED POLYCRYSTALLINE THIN FILM SEMICONDUCTORS FORMED USING SEQUENTIAL LATERAL SOLIDIFICATION AND DEVICES FORMED THEREON - Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed. One method includes generating a sequence of excimer laser pulses, controllably modulating each pulse to a predetermined fluence, homoginizing each modulated pulse in a predetermined plane, masking portions of each homoginized pulse with a pattern of slits to generate a sequence of fluence controlled pulses of line patterned beamlets, each slit in the pattern of slits being sufficiently narrow to prevent inducement of significant nucleation in region of a silicon thin film sample irradiated by a beamlet corresponding to the slit, irradiating an amorphous silicon thin film sample with the sequence of fluence controlled slit patterned beamlets to effect melting of portions corresponding to each fluence controlled patterned beamlet pulse, and controllably sequentially translating a relative position of the sample with respect to each of the fluence controlled pulse of slit patterned beamlets. | 01-10-2013 |