Patent application number | Description | Published |
20080280441 | Method of Forming Isolation Layer of Flash Memory Device - An embodiment of the invention relates to a method of forming an isolation layer of a flash memory device. An isolation layer is formed using a PSZ-based material and a nitride film of liner form is deposited on a trench before the PSZ film is deposited. An oxide film can be prevented from remaining on a top of the sidewalls of a conductive film for a floating gate through an etch process employing the etch rate. The thickness of a dielectric film can be prevented from increasing when a dielectric film is deposited. Accordingly, the contact area of the floating gate and the dielectric film can be increased and the coupling ratio between the floating gate and the control gate can be improved. | 11-13-2008 |
20090170282 | Method of Forming Isolation Layer in Semiconductor Device - A method of forming isolation layer in a semiconductor device, comprising forming a trench on an isolation region of a semiconductor substrate by etching utilizing an isolation mask; forming a first insulating layer on a lower portion of the trench; forming a second insulating layer on the semiconductor substrate including the first insulating layer; etching the second insulating layer to increase an aspect ratio on the isolation region; and forming a third insulating layer on a peripheral region of the second insulating layer to fill moats formed on the second insulating layer with the third insulating layer. | 07-02-2009 |
20090212339 | Flash Memory Device and Method of Fabricating the Same - The present invention relates to flash memory devices and a method of fabricating the same. In an aspect of the present invention, the flash memory device includes trenches formed in a semiconductor substrate and having a step at their lower portion, a tunnel insulating layer formed in an active region of the semiconductor substrate, first conductive layers formed on the tunnel insulating layer, an isolation layer gap-filling between the trenches and the first conductive layers, and a second conductive layer formed on the first conductive layer and having one side partially overlapping with the isolation layers. | 08-27-2009 |
20100025752 | CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer formed over sidewalls of the charge trap layer and provided to isolate the charge trap layer. | 02-04-2010 |
20100304549 | METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE - A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer. | 12-02-2010 |
20110059594 | FLASH MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - The present invention relates to flash memory devices and a method of fabricating the same. In an aspect of the present invention, the flash memory device includes trenches formed in a semiconductor substrate and having a step at their lower portion, a tunnel insulating layer formed in an active region of the semiconductor substrate, first conductive layers formed on the tunnel insulating layer, an isolation layer gap-filling between the trenches and the first conductive layers, and a second conductive layer formed on the first conductive layer and having one side partially overlapping with the isolation layers. | 03-10-2011 |
20120202329 | CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer formed over sidewalls of the charge trap layer and provided to isolate the charge trap layer. | 08-09-2012 |
20130078794 | CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer formed over sidewalls of the charge trap layer and provided to isolate the charge trap layer. | 03-28-2013 |
20150032960 | ELECTRONIC DEVICES HAVING SEMICONDUCTOR MEMORY UNITS AND METHOD OF FABRICATING THE SAME - Electronic devices have a semiconductor memory unit including a magnetization compensation layer in a contact plug. One implementation of the semiconductor memory unit includes a variable resistance element having a stacked structure of a first magnetic layer, a tunnel barrier layer, and a second magnetic layer, and a contact plug arranged in at least one side of the variable resistance element and comprising a magnetization compensation layer. Another implementation includes a variable resistance element having a stacked structure of a first magnetic layer having a variable magnetization, a tunnel barrier layer, and a second magnetic layer having a pinned magnetization; and a contact plug arranged at one side of and separated from the variable resistance element to include a magnetization compensation layer that produces a magnetic field to reduce an influence of a magnetic field of the second magnetic layer on the first magnetic layer. | 01-29-2015 |
20150052302 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - The disclosed technology provides an electronic device and a fabrication method thereof, in which an etching margin in formation of a variable resistance element is secured and process difficulty is reduced. An electronic device according to an implementation includes a semiconductor memory, the semiconductor memory including: a variable resistance element including a stack of a first magnetic layer, a tunnel barrier layer and a second magnetic layer; a contact plug coupling a top of the variable resistance element and including a magnetism correcting layer; and a conductive line coupled to the variable resistance element through the contact plug including the magnetism correcting layer. | 02-19-2015 |
20150092480 | ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME - An electronic device includes a semiconductor memory, wherein the semiconductor memory includes: a seed layer including conductive hafnium silicate; a first magnetic layer formed over the seed layer; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer. | 04-02-2015 |
20150092481 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device includes a semiconductor memory, wherein the semiconductor memory includes: a variable resistance element having a stacked structure of a first magnetic layer, a tunnel barrier layer, and a second magnetic layer; and a protection layer including a pillar-shaped magnetic compensation layer and a non-magnetic layer, which are formed on the sidewall of the variable resistance element. | 04-02-2015 |
Patent application number | Description | Published |
20110269304 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a multilayer, forming a plurality of patterns by etching the multilayer and a portion of the substrate, forming a supporter to support the plurality of patterns, and removing residues formed during the etching. | 11-03-2011 |
20110284942 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an active region having a sidewall, which has a sidewall step, a junction formed under a surface of the sidewall step, and a buried bit line configured to contact the junction. | 11-24-2011 |
20120292684 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a first storage layer making contact with a sidewall of an active region in an isolation trench and a second charge storage layer making contact with an opposite sidewall of the active region in the isolation trench, first and second tunnel insulation layers interposed between the first charge storage layer and the active region and between the second charge storage layer and the active region, a first charge blocking layer disposed over the first and second charge storage layers, and a control gate disposed over the first charge blocking layer. | 11-22-2012 |
20130264623 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINES - A semiconductor device includes an active region having a sidewall, which has a sidewall step, a junction formed under a surface of the sidewall step, and a buried bit line configured to contact the junction. | 10-10-2013 |
20150255708 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device that includes a first structure including a first magnetic layer, a second magnetic layer, and a tunnel barrier layer which is interposed between the first magnetic layer and the second magnetic layer; and a second structure disposed over the first structure, and including a magnetic correction layer for correcting a magnetic field of the first structure, wherein a width of a bottom surface of the second structure is larger than a width of a top surface of the first structure. | 09-10-2015 |
Patent application number | Description | Published |
20110056487 | FULL TIME REGENERATIVE TYPE SINGLE RADIANT TUBE BURNER - The present invention relates to a full time regenerative type single radiant tube burner. The full time regenerative type single radiant tube burner includes a radiant tube type burner; a regenerating unit that regenerates exhaust gas heat generated from the burner and is used for preheating the intake combustion air; and an intake and exhaust switching device that passes the intake air and the exhaust gas to the regenerating unit and heat-exchanges them and simultaneously progresses the intake and exhaust processes of the burner to perform the full time combustion. | 03-10-2011 |
20120125052 | LOW-CARBON-TYPE IN-FLIGHT MELTING FURNACE UTILIZING COMBINATION OF PLASMA HEATING AND GAS COMBUSTION, MELTING METHOD UTILIZING THE SAME AND MELTING SYSTEM UTILIZING THE SAME - A low-carbon-type in-flight melting furnace for melting granular raw material for glass production in in-flight state using plasma heating and gas combustion, a melting method using the same and a melting system utilizing the same are provided. The low-carbon-type in-flight melting furnace includes a melting furnace body unit; a melting tank in the melting furnace body unit; a melting unit provided above the melting tank and serving to melt raw material; a raw material feeding unit provided outside the melting unit; a plasma/gas melting device provided around the melting unit and serving to spray high-temperature flames produced by plasma and gas; an exhaust tube provided at one side of the melting tank and serving to discharge exhaust gas; and a tap hole for tapping the melt, formed in the melting unit, through the melting tank, in the form of a slag. | 05-24-2012 |
20130164179 | FLAMELESS STEAM REFORMER - A flameless steam reformer is provided, which includes a main housing, a catalyst housing which is inserted to the main housing and in which a combustion catalyst and a reforming catalyst are provided such that they are partitioned from each other, and a passage housing which is disposed between the main housing and the catalyst housing and includes a passage through which a reforming fuel supplied to the catalyst housing moves. | 06-27-2013 |
20140093805 | SOLID OXIDE FUEL CELL STACK WITH UNIFORM FLOW DISTRIBUTION STRUCTURE AND METAL SEALING MEMBER - A solid oxide fuel cell stack with a uniform flow distribution structure and a metal sealing member is provided, in which fuel and air introduced into the solid oxide fuel cell stack are preheated to a predetermined temperature by heat exchangers provided therein and uniformly distributed over the entire anode and cathode reaction surfaces of unit cells to improve the use efficiency of a fuel cell and in which the sealing of the fuel cell stack is effectively maintained even under high temperature and high pressure conditions to ensure the safety of the fuel cell and increase its durability. | 04-03-2014 |
20150318564 | BOP SYSTEM OF SOLID OXIDE FUEL CELL, SOLID OXIDE FUEL CELL STACK MODULE, AND METHOD FOR OPERATING THE SOLID OXIDE FUEL CELL - The present invention relates to a balance of plant (BOP) system of solid oxide fuel cells including a burner, a reformer, a steam generator, and heat exchangers, wherein the burner, the reformer and the steam generator are laid sequentially on top of each other to transmit the flames and burned gas generated from the burner directly to the reformer and the steam generator disposed sequentially on top of the burner, and the heat exchangers introduce the flue gas discharged from the steam generator thereinto and preheat the process air to be supplied to cathodes of stacks. | 11-05-2015 |
Patent application number | Description | Published |
20090298831 | PHENYL PIPERAZINE COMPOUNDS, PHARMACEUTICAL COMPOSITION INCLUDING THE SAME AND USE THEREOF - The present invention relates to novel piperazine derivatives or pharmaceutically acceptable salts thereof, a process for preparing the same, and in particular, a high binding for Serotonin 1A(5-hydroxytryptamine; 5-HT1A) receptor, a pharmaceutical composition for treatment and/or prevention of depression and anxiety including an effective amount of the piperazine compound, and a method of treating depression, anxiety and other conditions related to 5-HT1A receptor in a mammal. | 12-03-2009 |
20090298851 | PHENYL PIPERAZINE COMPOUNDS, PHARMACEUTICAL COMPOSITION COMPRISING THE SAME AND USE THEREOF - The present invention relates to a novel piperazine derivative or pharmaceutically acceptable salt thereof, a process for preparing the same, a pharmaceutical composition for treating central nervous system diseases comprising an effective amount of the piperazine compound and a method of treating central nervous system (CNS) disorder such as psychosis in a mammal. | 12-03-2009 |
20110118264 | PHENYL PIPERAZINE COMPOUNDS, PHARMACEUTICAL COMPOSITION INCLUDING THE SAME AND USE THEREOF - The present invention relates to novel piperazine derivatives or pharmaceutically acceptable salts thereof, a process for preparing the same, and in particular, a high binding for Serotonin 1A(5-hydroxytryptamine; 5-HT1A) receptor, a pharmaceutical composition for treatment and/or prevention of depression and anxiety including an effective amount of the piperazine compound, and a method of treating depression, anxiety and other conditions related to 5-HT1A receptor in a mammal | 05-19-2011 |
Patent application number | Description | Published |
20080213509 | Composition for LC alignment film using diamine having dendron side chain - Disclosed herein is an LC aligning agent using diamine having dendron side chains. In detail, the present invention relates to a composition for an LC alignment film which employs diamine having dendron side chains to produce polyamic acid, followed by imidization. When the LC alignment film is applied to a liquid crystal display device, high heat resistance, high penetration in a visible ray range, excellent alignment, and a high voltage holding ratio are assured. Even though it contains a small amount of functional diamine, a high pretilt angle can be assured. Thus, the pretilt angle is easily controlled and a vertical aligning force is improved. | 09-04-2008 |
20100168374 | Diamine compound having dendron side chain and liquid crystal aligning agent using same - Disclosed herein is a novel functional diamine compound having a dendron structure, polyamic acid which is produced using functional diamine, aromatic cyclic diamine, aliphatic cyclic acid dianhydride, and aromatic cyclic acid dianhydride, polyimide which is produced by imidizing polyamic acid, and an LC alignment film produced using polyimide. Even if the diamine compound is used in a small amount, it is possible to realize a high pretilt angle, thus the pretilt angle is easily controlled. Therefore, it can be used to produce an LC alignment film using a twisted nematic (TN) mode, in which the pretilt angle of liquid crystal is low, and a vertically aligned (VA) mode, which requires a high pretilt angle of about 90°. | 07-01-2010 |
Patent application number | Description | Published |
20100136264 | Liquid Crystal Alignment Agent, and Liquid Crystal Alignment Film and Liquid Crystal Display Including Same - Disclosed are a liquid crystal alignment agent, and a liquid crystal alignment film and a liquid crystal display (LCD) including the same. The liquid crystal alignment agent includes a polymer of polyamic acid, a polyimide, or a combination thereof, and an epoxy compound represented by the following Chemical Formula 1. | 06-03-2010 |
20120116045 | Liquid Crystal Alignment Agent, Liquid Crystal Alignment Film Manufactured Using the Same, and Liquid Crystal Display Device Including the Liquid Crystal Alignment Film - Disclosed is a liquid crystal alignment agent including a polymer including polyamic acid including a repeating unit represented by Chemical Formula 1, polyimide including a repeating unit represented by Chemical Formula 2, or a combination thereof. | 05-10-2012 |
20120172541 | Liquid Crystal Alignment Agent, Liquid Crystal Alignment Film Manufactured Using the Same, and Liquid Crystal Display Device Including the Liquid Crystal Alignment Film - A liquid crystal alignment agent includes a first polymer including polyamic acid including a repeating unit represented by the following Chemical Formula 1, polyimide including a repeating unit represented by the following Chemical Formula 2, or a combination thereof. A liquid crystal alignment film manufactured using the liquid crystal alignment agent, and a liquid crystal display including the liquid crystal alignment film are also provided. | 07-05-2012 |
20130123438 | Liquid Crystal Alignment Agent, Liquid Crystal Alignment Film Manufactured Using the Same, and Liquid Crystal Display Device Including the Liquid Crystal Alignment Film - Disclosed is a liquid crystal alignment agent that includes a polymer including a polyamic acid including a repeating unit represented by the following Chemical Formula 1, polyimide including a repeating unit represented by the following Chemical Formula 2, or a combination thereof, wherein in Chemical Formulas 1 and 2, X | 05-16-2013 |