Patent application number | Description | Published |
20160071551 | VOLTAGE COMPARATOR CIRCUIT AND USAGE THEREOF - A circuit comprising a first power supply having a first voltage and a second power supplying having a second voltage, wherein said first and second voltages are different at least in some cycles of said circuit, a memory element, wherein said first and second power supplies are driven into said memory element, a voltage comparator having connected thereto said first and second power supplies, wherein said voltage comparator is an analog to digital converter configured to provide digital output indicting of a voltage difference over a predetermined threshold between said first and second power supplies, and a supply selector element, wherein said supply selector element is configured to disconnect said second power supply from said memory element in response to the digital output of said voltage comparator. | 03-10-2016 |
20160071617 | VOLTAGE COMPARATOR CIRCUIT AND USAGE THEREOF - A method for testing a circuit comprising a memory element, a voltage comparator and a supply selector, the circuit is configured to be connected to two power supplies, the voltage comparator is configured to provide an output indicative of a voltage difference between the two power supplies above a predetermined threshold, the supply selector is configured to select a power supply to feed power to the memory element in response to the output from the voltage comparator. The method comprises connecting the two power supplies to the circuit, wherein said connecting comprises causing the two power supplies to drive power to the memory element and to another element of the circuit, wherein the voltage different between the two power supplies is above the predetermined threshold. The method further comprises that in response to said connecting, the supply selector of the circuit is invoked and disconnects one power supply from the memory element; whereby stress testing the circuit, the stress testing tests the memory element without a voltage difference condition, the stress testing tests the another element with the voltage difference condition. | 03-10-2016 |
Patent application number | Description | Published |
20100194439 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the n-type transistor network is connected to the second dedicated logic terminal, and the first network gate connection of the n-type transistor network is connected to the second logic input. The inner diffusion connections of the p-type network and of the n-type network are connected together to form a common diffusion logic terminal. | 08-05-2010 |
20120126853 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for implementing a predetermined logic function, and having an outer diffusion connection connected to the first dedicated logic terminal, a first network gate connection connected to the first logic input, and an inner diffusion connection; and an n-type transistor network comprising multiple n-type transistors, for implementing a logic function complementary to the predetermined logic function, and having an outer diffusion connection connected to the second dedicated logic terminal, a first network gate connection connected to the second logic input, and an inner diffusion connection; the inner diffusion connections of the p-type transistor network and of the n-type transistor network being connected to form a common diffusion logic terminal. | 05-24-2012 |
Patent application number | Description | Published |
20080270502 | System, Method and Device of Generating a Random Value - Some demonstrative embodiments of the invention include a method, apparatus and system of generating a random number. A random number generator may include, for example, a plurality of different random-number-generation modules adapted to generate random bits at a plurality of bit paths; and a combiner adapted to combine the bits of the plurality of paths. Other embodiments are described and claimed. | 10-30-2008 |
20100289563 | Method and Mechanism to Reduce Current Variation in a Current Reference Branch Circuit - A novel and useful system and method of providing a feedback mechanism to reduce current variation observed in a current reference branch circuit by using body voltage control to compensate process, temperature and supply voltage variations. The current reference output voltage, which is proportional to the reference current, is sampled into a feedback loop, which controls the field effect transistor body voltage. The method and mechanism of the present invention uses Corner Robust Current Reference in order to keep the design simple and diminish variation between Process Voltage Temperature (PVT) corners. This method exhibits superior robustness with smaller variation in the reference current magnitude. | 11-18-2010 |
20120044024 | LATCHED RING OSCILLATOR DEVICE FOR ON-CHIP MEASUREMENT OF CLOCK TO OUTPUT DELAY IN A LATCH - A novel and useful apparatus and related method for on-chip measurement of the clock to output delay of a latch within an integrated circuit. The delay measurement mechanism enables measuring the time delay from the transition of the clock input to the data output of a latch. The output delay of the on-chip latch is measured by making the latch delay part of a ring oscillator and measuring its frequency of oscillation. A latch based delay stage is used to construct the ring oscillator in which a delayed short pulse derived from the input edge is used as the trigger for the latch. The latched ring oscillator mechanism of the invention can be used to measure the clock to output (C2Q) delay of on-chip latch devices. | 02-23-2012 |
Patent application number | Description | Published |
20090196487 | METHOD AND SYSTEM FOR EVALUATING A VARIATION IN A PARAMETER OF A PATTERN - A method and system are presented for evaluating a variation of a parameter of a pattern, the method includes: processing data indicative of an aerial intensity image of at least a portion of a patterned article, and determining values of a certain functional of the aerial image intensity for predetermined regions within said at least portion of the patterned article, said values of the aerial image intensity functional being indicative of a variation of at least one parameter of the pattern within said at least portion of the patterned article or of a variation of at least one parameter of a pattern manufactured by utilizing the patterned article. | 08-06-2009 |
20140199791 | Method and System for Universal Target Based Inspection and Metrology - Universal target based inspection drive metrology includes designing a plurality of universal metrology targets measurable with an inspection tool and measurable with a metrology tool, identifying a plurality of inspectable features within at least one die of a wafer using design data, disposing the plurality of universal targets within the at least one die of the wafer, each universal target being disposed at least proximate to one of the identified inspectable features, inspecting a region containing one or more of the universal targets with an inspection tool, identifying one or more anomalistic universal targets in the inspected region with an inspection tool and, responsive to the identification of one or more anomalistic universal targets in the inspected region, performing one or more metrology processes on the one or more anomalistic universal metrology targets with the metrology tool. | 07-17-2014 |
20150054940 | QUALIFYING PATTERNS FOR MICROLITHOGRAPHY - Disclosed are methods and apparatus for qualifying a photolithographic reticle. A reticle inspection tool is used to acquire at least two images at different imaging configurations from each pattern area of the reticle. A reticle pattern is reconstructed based on each at least two images from each pattern area of the reticle. For each reconstructed reticle pattern, a lithographic process with two or more different process conditions is modeled on such reconstructed reticle pattern to generate two or more corresponding modeled test wafer patterns. Each two or more modelled test wafer patterns is analyzed to identify hot spot patterns of the reticle patterns that are susceptible to the different process conditions altering wafer patterns formed with such hot spot patterns. | 02-26-2015 |
Patent application number | Description | Published |
20100037753 | INTERVENTIVE-DIAGNOSTIC DEVICE - Apparatus for improving health of a user is provided, including a first sensor, adapted to measure a first physiological variable, which is indicative of a voluntary action of the user. A second sensor is adapted to measure a second physiological variable, which is substantially governed by an autonomic nervous system of the user. Circuitry is adapted to receive respective first and second sensor signals from the first and second sensors, and, responsive thereto, to generate an output signal which directs the user to modify a parameter of the voluntary action. | 02-18-2010 |
20120225412 | INTERVENTIVE DIAGNOSTIC DEVICE - Apparatus and methods are described for facilitating improving health of a user. In accordance with some applications, a first physiological variable, which is indicative of a voluntary action of the user, is received. A second physiological variable, which is not entirely under the direct voluntary control of the user, is received. Responsive to the first and second variables, the second physiological variable is changed in a desired manner, by using circuitry to direct the user to modify a parameter of the voluntary action, by generating an output signal. Other applications are also described. | 09-06-2012 |
20140141395 | INTERVENTIVE-DIAGNOSTIC DEVICE - Apparatus for improving health of a user is provided, including a first sensor, adapted to measure a first physiological variable, which is indicative of a voluntary action of the user. A second sensor is adapted to measure a second physiological variable, which is substantially governed by an autonomic nervous system of the user. Circuitry is adapted to receive respective first and second sensor signals from the first and second sensors, and, responsive thereto, to generate an output signal which directs the user to modify a parameter of the voluntary action. | 05-22-2014 |
Patent application number | Description | Published |
20080218585 | APPEARANCE MATCHING FOR VIDEOCONFERENCING - Methods and systems for presenting video images generated by multiple endpoints in a videoconference such that the displayed images have consistent appearance, for example consistent brightness levels are disclosed. Sampling methods and algorithms are used to calculate an appropriate amount of correction for each video image and the images are adjusted accordingly. Brightness correction may implement one or more brightness sampling and analyzing logical modules (BSAM) and one or more transforming logical module (TLM). The brightness matching methods may be implemented in centralized architecture, for example, as part of a multipoint control unit (MCU). Alternatively, the methods may be implemented using a distributed architecture. | 09-11-2008 |
20080291265 | SMART CROPPING OF VIDEO IMAGES IN A VIDEOCONFERENCING SESSION - Systems and methods are disclosed for controlling cropping areas of video images to match the allocated area associated with the image in a video conferencing layout. The disclosed methods can protect regions of interest from being cropped. A region of interest within a video image is identified to adjust the cropping in such a way that the region of interest is preserved within the cropped image. The region of interest may be identified based on motion detection or flesh tone detection, for example. | 11-27-2008 |
20100103245 | Dynamic Adaption of a Continuous Presence Videoconferencing Layout Based on Video Content - Dynamically adapting a continuous presence (CP) layout in a videoconference enhances a videoconferencing experience by providing optimum visibility to regions of interest within the CP layout and ignoring regions of no interest. Based on the CP layout, a CP video image can be built, in which a conferee at a receiving endpoint can observe, simultaneously, several other participants' sites in the conference. For example, more screen space within the CP layout is devoted to presenting the participants in the conference and little or no screen space is used to present an empty seat, an empty room, or an unused portion of a room. Aspect ratios of segments of the CP layout (e.g., landscape vs. portrait) can be adjusted to optimally present the regions of interest. The CP layout can be adjusted as regions of interest change depending on the dynamics of the video conference. | 04-29-2010 |
20120147130 | Appearance Matching for Videoconferencing - Methods and systems for presenting video images generated by multiple endpoints in a videoconference such that the displayed images have consistent appearance, for example consistent brightness levels are disclosed. Sampling methods and algorithms are used to calculate an appropriate amount of correction for each video image and the images are adjusted accordingly. Brightness correction may implement one or more brightness sampling and analyzing logical modules (BSAM) and one or more transforming logical module (TLM). The brightness matching methods may be implemented in centralized architecture, for example, as part of a multipoint control unit (MCU). Alternatively, the methods may be implemented using a distributed architecture. | 06-14-2012 |
20130222529 | DYNAMIC ADAPTION OF A CONTINUOUS PRESENCE VIDEOCONFERENCING LAYOUT BASED ON VIDEO CONTENT - Dynamically adapting a continuous presence (CP) layout in a videoconference enhances a videoconferencing experience by providing optimum visibility to regions of interest within the CP layout and ignoring regions of no interest. Based on the CP layout, a CP video image can be built, in which a conferee at a receiving endpoint can observe, simultaneously, several other participants' sites in the conference. For example, more screen space within the CP layout is devoted to presenting the participants in the conference and little or no screen space is used to present an empty seat, an empty room, or an unused portion of a room. Aspect ratios of segments of the CP layout (e.g., landscape vs. portrait) can be adjusted to optimally present the regions of interest. The CP layout can be adjusted as regions of interest change depending on the dynamics of the video conference. | 08-29-2013 |
20140002585 | METHOD AND SYSTEM FOR ADAPTING A CP LAYOUT ACCORDING TO INTERACTION BETWEEN CONFEREES | 01-02-2014 |