Patent application number | Description | Published |
20080218178 | TESTING APPARATUS, FIXTURE BOARD AND PIN ELECTRONICS CARD - There is provided a test apparatus for testing a device under test including a pre-emphasis circuit. The pre-emphasis circuit emphasizes a predetermined component of an output signal of the device under test and outputs the resulting output signal. Here, the test apparatus includes a filter that eliminates an emphasized component that is generated by the pre-emphasis circuit, from the output signal output from the device under test, and a testing section that measures the output signal output from the filter, and judges whether the device under test is acceptable based on a result of the measurement. The test apparatus can accurately test the pre-emphasis function of the device under test including the pre-emphasis circuit. | 09-11-2008 |
20080315130 | FOCUSED ION BEAM PROCESSING SYSTEM AND METHOD - A focused ion beam (FIB) processing system includes a FIB irradiation unit that irradiates a FIB onto a pattern formed in a wafer, to form a section of the pattern, an imaging unit that images the section of the pattern, a calculation unit that calculates a pattern size based on the image of the section, a judgment unit that judges whether or not a differential of the pattern size with respect to time is equal to or below a threshold; and a control unit that stops the FIB irradiation unit if the judgment unit judges that the differential of the pattern size is equal to or below the threshold. | 12-25-2008 |
20090012729 | LIGHT RECEIVING APPARATUS, TESTING APPARATUS, LIGHT RECEIVING METHOD, TESTING METHOD, TEST MODULE AND SEMICONDUCTOR CHIP - An optical receiving apparatus that receives an optical signal and outputs a data value of digital data transmitted by the optical signal is provided, including a light receiving element that receives the optical signal and outputs a photocurrent according to a strength of the optical signal, a present cycle integrator that integrates the photocurrent corresponding to a present cycle of the digital data over a prescribed period within the cycle, a previous cycle integrator that integrates the photocurrent corresponding to a cycle prior to the present cycle over a period that is substantially equal to the prescribed period in the cycle, and a data value identifying circuit that outputs a data value of the present cycle of the digital data based on a difference between a charge amount obtained through integration by the present cycle integrator and a charge amount obtained through integration by the previous cycle integrator. | 01-08-2009 |
20090074420 | MEASURING APPARATUS, TRANSFER CIRCUIT, AND MEASURING METHOD - There is provided a measuring apparatus that measures a characteristic of a transfer circuit transmitting a signal. The transfer circuit includes an electrical signal sending section that transmits a sending signal, a current to light converting section that converts the sending signal into an optical signal, an optical signal transmitting section that transmits the optical signal, a photo-electric converting circuit that converts the optical signal into an electrical signal, a level measuring section that compares the intensity of the electrical signal output from the photo-electric converting circuit and a predetermined reference level to detect a data value of the electrical signal, an electrical signal receiving section that detects a data value of the electrical signal, and a timing controlling section that controls latch timing at which the electrical signal receiving section detects the data value of the electrical signal. The measuring apparatus includes a comparing section that compares the data value of the electrical signal received by the electrical signal receiving section with a predetermined expected value, a setting controlling section that sequentially changes the reference level and the latch timing, and a result storing section that stores a comparison result by the comparing section for each the reference level and the latch timing. | 03-19-2009 |
20090103869 | CONNECTING DEVICE, CONNECTING SYSTEM, OPTICAL WAVEGUIDE AND CONNECTING METHOD - There is provided a connecting system including a connecting apparatus that includes (i) a signal transfer path that transfers one of an electrical signal and an optical signal and (ii) a connecting device that connects the signal transfer path to a connection target component in such a manner that a signal is capable of being transferred therebetween, and a connected apparatus that includes the connection target component to be connected to the signal transfer path. Here, the connecting device includes a moving portion that has therein a sealed space. The moving portion moves an end portion of the signal transfer path closer to the connection target component so that the end portion of the signal transfer path is connected to the connection target component in response to an increase in a pressure within the moving portion, and moves the end portion away from the connection target component in response to a decrease in the pressure within the moving portion. | 04-23-2009 |
20090132884 | TIMING GENERATOR AND SEMICONDUCTOR TESTING APPARATUS - A timing generator that needs no analog circuit for adding jitters and allows the circuit scale and power consumption to be reduced. There are included a counter for performing a counting operation synchronized with a reference clock signal: a timing memory for outputting respective data corresponding to the quotient and remainder resulting from dividing the time from the front of a basic period until a generation of a timing edge by the period of the reference clock signal: a coincidence detecting circuit for outputting a signal that exhibits a high level when the count value of the counter coincides with the quotient: a jitter generating circuit for outputting as a jitter amplitude value: adders for adding a time corresponding to the remainder and a time represented by the jitter amplitude value outputted from the jitter generating circuit: and a variable delay circuit for delaying the output signal from the coincidence detecting circuit by the time represented by the addition result of the adders and outputting the delayed output signal. | 05-21-2009 |
20090184741 | Delay lock loop circuit, phase lock loop circuit, timing generator, semiconductor tester and semiconductor integrated circuit - A delay lock loop circuit and a phase lock loop circuit are designed to reduce a lock-up time, extend a lock range without increasing the number of bits of a counter, and quickly return to a lock target upon deviation from the lock target. There are provided with a plurality of phase comparators | 07-23-2009 |
20090295417 | TEST SYSTEM, ELECTRONIC DEVICE, AND TEST APPARATUS - Provided is a test system that tests a device under test, including a plurality of internal test circuits that are provided inside the device under test and that are used for testing an operation circuit of the device under test; a device control section that is electrically connected to the plurality of internal test circuits via a common bus and that controls the plurality of internal test circuits by supplying the common bus with an intra-device control signal corresponding to a received external signal; and a test apparatus that supplies the device control section with the external signal. | 12-03-2009 |
20100007366 | TEST EQUIPMENT AND SEMICONDUCTOR DEVICE - An interface circuit is connected to an ATE via a test control bus BUS | 01-14-2010 |
20100049453 | TEST APPARATUS AND MANUFACTURING METHOD - Provided is a test apparatus that tests a device under test, comprising a test signal generating section that generates a test signal to be applied to the device under test; a first driver that is electrically connected to a terminal of the device under test and that supplies the test signal to the terminal of the device under test; a correction signal generating section that generates a correction signal for correcting attenuation of the test signal occurring until the test signal reaches the terminal of the device under test; and a second driver that is electrically connected to the terminal of the device under test and that supplies the correction signal to the terminal of the device under test. | 02-25-2010 |
20100052736 | SIGNAL GENERATING APPARATUS, TEST APPARATUS AND CIRCUIT DEVICE - There is provided a signal generating apparatus for generating an output signal corresponding to pattern data supplied thereto. The signal generating apparatus includes a timing generating section that generates a periodic signal, a shift register section including a plurality of flip-flops in a cascade arrangement through which each piece of data of the pattern data is propagated sequentially in response to the periodic signal, a waveform generating section that generates the output signal whose value varies in accordance with a cycle of the periodic signal, based on data values output from the plurality of flip-flops, and an analog circuit that enhances a predetermined frequency component in a waveform of the output signal generated by the waveform generating section. | 03-04-2010 |
20100090737 | CLOCK DATA RECOVERY CIRCUIT AND METHOD - A change-point detection circuit | 04-15-2010 |
20100128538 | DATA RECEIVING CIRCUIT - A variable delay circuit provides an adjustable delay to a strobe signal. An input latch circuit latches each bit data included in internal serial data by a strobe signal delayed by the variable delay circuit. A delay set unit adjusts a delay amount provided to the strobe signal by the variable delay circuit. While a calibration operation is being executed in which a known calibration pattern is inputted as serial data, the delay set unit statistically acquires output latch data of the input latch circuit, and adjusts the delay amount such that probabilities of occurrence of 1 and 0 becomes a predetermined ratio. | 05-27-2010 |
20100164584 | Timing Generator - A delay setting data generator generates delay setting data based on rate data. A variable delay circuit delays the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay. First rate data designates the period of the test pattern data with a precision determined by the unit amount of delay. Second rate data designates the period of the test pattern data with a precision higher than that determined by the unit amount of delay. The delay setting data generator outputs a first value and a second value in a time division manner at a ratio determined by the second rate data, the first and second values being determined by the first rate data. | 07-01-2010 |
20100321127 | TEST APPARATUS FOR DIGITAL MODULATED SIGNAL - A test apparatus includes digital modulators provided in increments of multiple channels. A baseband signal generator performs retiming of data input as a modulation signal for the in-phase (quadrature) component, using a timing signal the timing of which can be adjusted, thereby generating a baseband signal. A driver generates a multi-value digital signal having a level that corresponds to the baseband signal output from the baseband signal generator. A multiplier amplitude-modulates a carrier signal with the multi-value digital signal. An adder sums the output signals of the multipliers. | 12-23-2010 |
20110054827 | TEST APPARATUS AND METHOD FOR MODULATED SIGNAL - A test apparatus tests a modulated signal under test received from a DUT. A cross timing data generating unit generates cross timing data which indicates a timing at which the level of the signal under test crosses each of multiple thresholds. An expected value data generating unit generates timing expected value data which indicates a timing at which an expected value waveform of the signal under test crosses each of the multiple thresholds when the expected value waveform is compared with each of the multiple thresholds. A timing comparison unit compares the cross timing data with the timing expected value data. | 03-03-2011 |
20110057642 | TEST APPARATUS FOR DIGITAL MODULATED SIGNAL - An amplitude expected value data generator generates amplitude expected value data that represents, in increments of sampling points, which of multiple amplitude segments the amplitude of a modulated signal waveform that corresponds to the expected value of data to be output from a device under test belongs to. A demodulator performs sampling of the signal waveform to be tested received from the device under test, and generates judgment data that represents, in increments of sampling points, which of the multiple amplitude segments the amplitude of the signal waveform belongs to. A judgment unit makes a comparison between the amplitude expected value data and the judgment data in increments of sampling points. | 03-10-2011 |
20110057665 | TEST APPARATUS FOR DIGITAL MODULATED SIGNAL - A pattern generator generates test data to be transmitted. An encoding circuit generates amplitude data which represent a modulated signal waveform that corresponds to the test data. The amplitude data are generated in a parallel manner in the form of multiple amplitude data in increments of multiple sampling points set within a predetermined period for cycles of the predetermined period. A data rate setting unit receives the multiple amplitude data in increments of sampling points, latches the amplitude data at corresponding sampling timings, and sequentially outputs the amplitude data thus latched. A multi-level driver receives sequentially input amplitude data, and generates a test signal having a level that corresponds to the value of the amplitude data thus received. | 03-10-2011 |
20110187400 | SEMICONDUCTOR TEST APPARATUS AND TEST METHOD - In a semiconductor test apparatus, a first device is tested as a device under test in a state where the first device provided with a transmitter transmitting a signal and a second device provided with a receiver receiving the signal transmitted by the transmitter, are connected together. The transmitter includes an equalizer circuit that shapes the waveform of the differential signal to be transmitted. The receiver includes a latch circuit that latches data corresponding to the differential signal thus received with the use of a clock, the timing of which is variable. A control unit varies, in a matrix, a parameter of the equalizer circuit and an edge timing of the clock CLK supplied to the latch circuit. | 08-04-2011 |
20120112783 | TEST APPARATUS - A test apparatus tests a DUT formed on a wafer. A power supply compensation circuit includes source and a sink switches each controlled according to a control signal. When the source or sink switch is turned on, a compensation pulse current is generated, and the compensation pulse current is injected into a power supply terminal of the DUT via a path that differs from that of a main power supply, or is drawn from the power supply current that flows from the main power supply to the DUT via a path that differs from that of the power supply terminal of the DUT. Of components forming the power supply compensation circuit, including the source and sink switches, a part is formed on the wafer. Pads are formed on the wafer in order to apply a signal to such a part of the power supply compensation circuit formed on the wafer. | 05-10-2012 |
20120146416 | TEST APPARATUS - A DUT comprises a notifying circuit configured to generate a notification signal which is used to notify an external circuit of an event that leads to a change in the operating current of the DUT before such an event occurs. A main power supply supplies electric power to a power supply terminal of the DUT. A power supply compensation circuit comprises a switch element which is controlled according to a control signal, and is configured to generate a compensation pulse current according to the on/off state of the switch element. A compensation control circuit receives the notification signal from the DUT, and outputs, to the power supply compensation circuit, a control signal which is used to control the switch element, and which is generated based upon at least the notification signal. | 06-14-2012 |
20120158348 | TIMING GENERATOR - A delay setting data generator generates delay setting data based on rate data. A variable delay circuit delays the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay. First rate data designates the period of the test pattern data with a precision determined by the unit amount of delay. Second rate data designates the period of the test pattern data with a precision higher than that determined by the unit amount of delay. The delay setting data generator outputs a first value and a second value in a time division manner at a ratio determined by the second rate data, the first and second values being determined by the first rate data. | 06-21-2012 |
20120319794 | TEST APPARATUS FOR DIGITAL MODULATED SIGNAL - A test apparatus includes digital modulators provided in increments of multiple channels. A baseband signal generator performs retiming of data input as a modulation signal for the in-phase (quadrature) component, using a timing signal the timing of which can be adjusted, thereby generating a baseband signal. A driver generates a multi-value digital signal having a level that corresponds to the baseband signal output from the baseband signal generator. A multiplier amplitude-modulates a carrier signal with the multi-value digital signal. An adder sums the output signals of the multipliers. | 12-20-2012 |
20130115723 | Method of manufacturing semiconductor device and semiconductor manufacturing system - In a method of manufacturing a semiconductor device using an electron beam lithography apparatus configured to emit an electron beam to perform lithography of a pattern, processing including pattern formation with the electron beam lithography apparatus is performed on a wafer, and an electric characteristic of the thus manufactured semiconductor devices is measured by a semiconductor testing apparatus. Then, electron beam lithography data to be used by the electron beam lithography apparatus is adjusted based on a result of measurement of the electric characteristic so as to reduce a variation in the electric characteristic of the semiconductor device within a surface of the wafer. | 05-09-2013 |
20130147499 | TEST APPARATUS AND TEST METHOD - A pattern generator generates a pattern signal which represents a test signal to be supplied to a DUT. A driver generates a test signal having a level that corresponds to the pattern signal, and outputs the test signal thus generated to the DUT. A voltage modulator changes, in a predetermined voltage range, the voltage level of the test signal output from the driver DR. | 06-13-2013 |
20140315644 | SERVER DEVICE, METHOD FOR CONTROLLING THE SAME, COMPUTER READABLE RECORDING MEDIUM, AND GAME SYSTEM - A server device and the like providing a game and capable of enhancing the unpredictability and amusement of the game and increasing the fun and thrill of the game as a whole are realized. A server device according to the present invention is connected to a terminal device via a network and provides a game, and includes: an information storage unit for storing information related to the game; and a control unit for accessing the information, executing various operations, and displaying images of the game on the terminal device. In the game, a plurality of item boxes of a plurality of types, each of which is assigned a predetermined reward item, are displayed on the terminal device. | 10-23-2014 |
20150054185 | Method for Producing Wafer Lens - Disclosed is a method for producing a wafer lens wherein a glass substrate is provided with a lens part which is made of a first curable resin. A sub-master molding part having a plurality of negative molding surfaces corresponding to the optical surface shape of the lens part is formed from a master having a plurality of positive molding surfaces corresponding to the optical surface shape of the lens part by using a second curable resin; a sub-master is formed by backing the sub-master molding part with a sub-master substrate; and the lens part is formed by filling the space between the sub-master and the glass substrate with the first curable resin and curing the resin therein. In this connection, the first curable resin is composed of an epoxy resin. Consequently, the production cost can be reduced, and a high-precision wafer lens having small curing shrinkage can be produced. | 02-26-2015 |