Patent application number | Description | Published |
20090074106 | MULTI-MODE AND MULTI-BAND TRANSMITTERS FOR WIRELESS COMMUNICATION - Transmitters supporting multiple modulation modes and/or multiple frequency bands are described. A transmitter may perform large signal polar modulation, small signal polar modulation, and/or quadrature modulation, which may support different modulation schemes and systems. Circuit blocks may be shared by the different modulation modes to reduce cost and power. For example, a single modulator and a single power amplifier may be used for small signal polar modulation and quadrature modulation. The transmitter may apply pre-distortion to improve performance, to allow a power amplifier to support multiple frequency bands, to allow the power amplifier to operate at higher output power levels, etc. Envelope and phase distortions due to non-linearity of the power amplifier may be characterized for different input levels and different bands and stored at the transmitter. Thereafter, envelope and phase signals may be pre-distorted based on the stored characterizations to compensate for non-linearity of the power amplifier. | 03-19-2009 |
20090102564 | METHOD AND APPARATUS FOR COMPENSATING FOR TUNING NONLINEARITY OF AN OSCILLATOR - Techniques to compensate for nonlinearity of a tuning function of an oscillator are described. The tuning nonlinearity of the oscillator may be modeled as a disturbance input to the oscillator and may be compensated with an equal but opposite disturbance. In one design, a nonlinearity correction signal to compensate for the tuning nonlinearity may be generated, e.g., based on a phase error signal in a phase-locked loop (PLL) and a scaling factor determined adaptively. The nonlinearity correction signal may compensate for the n-th (e.g., second) order tuning nonlinearity, and an n-th order (e.g., squared) modulating signal may be used to derive the scaling factor and the nonlinearity correction signal. A control signal for the oscillator may be generated based on the nonlinearity correction signal and possibly one or more other signals. The control signal may be applied to the oscillator to adjust the oscillation frequency of the oscillator. | 04-23-2009 |
20090141845 | DIGITAL PHASE-LOCKED LOOP OPERATING BASED ON FRACTIONAL INPUT AND OUTPUT PHASES - In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference between an oscillator signal from an oscillator and a reference signal, e.g., using a time-to-digital converter (TDC). The DPLL determines a phase error based on the fractional portion of the input phase and the fractional portion of the output phase. The DPLL then generates a control signal for the oscillator based on the phase error. In another aspect, a DPLL includes a synthesized accumulator that determines a coarse output phase by keeping tracking of the number of oscillator signal cycles based on the reference signal. | 06-04-2009 |
20090195426 | ADAPTIVE HIGH-ORDER DIGITAL-TO-ANALOG CONVERSION - Techniques for performing digital-to-analog conversion with first-order or higher-order hold using a simple analog circuit for signal reconstruction and employing feedback control techniques are described. In one design, a digital-to-analog conversion circuit includes an inverse model circuit, a feedback circuit, a zero-order hold (ZOH) circuit, and an analog circuit. The inverse model circuit processes a digital input signal and provides a first digital signal. The feedback circuit receives the first digital signal and an analog output signal from the analog circuit, performs low frequency noise filtering, and provides a second digital signal. The ZOH circuit converts the second digital signal from digital to analog with zero-order hold and provides an analog input signal for the analog circuit. The analog circuit operates on the analog input signal and provides the analog output signal. The analog circuit may be a simple circuit having one or more poles. | 08-06-2009 |
20090268859 | SYSTEM AND METHOD OF CONTROLLING POWER CONSUMPTION IN A DIGITAL PHASE LOCKED LOOP (DPLL) - An apparatus comprising a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency device is further adapted to maintain the same temporal relationship of the triggering edges of the reference clock when switching between the distinct frequency clocks. The apparatus further comprises a phase locked loop (PLL), such as a digital PLL (DPLL), that uses the selected reference clock to establish a predetermined phase relationship between an input signal and an output signal. By maintaining substantially the same temporal relationship of the reference clock when switching between distinct frequency clocks, the continual and effective operation of the phase locked loop (PLL) is not significantly disturbed while changing the reference clock. This may be used to control the power consumption of the apparatus. | 10-29-2009 |
20090273377 | THRESHOLD DITHERING FOR TIME-TO-DIGITAL CONVERTERS - Techniques for dithering quantization thresholds of time-to-digital converters (TDC's) in all-digital phase-locked loops (ADPLL's) are disclosed. In an embodiment, the delay introduced by an individual buffer in a TDC delay line may be dithered. In another embodiment, the delay associated with the TDC delay line may be extended by a fixed amount to accommodate dithering of the zero-delay threshold. | 11-05-2009 |
20090302951 | DITHERING A DIGITALLY-CONTROLLED OSCILLATOR OUTPUT IN A PHASE-LOCKED LOOP - A digitally-controlled oscillator (DCO) of a PLL is dithered such that a DCO_OUT signal has a frequency that changes at dithered intervals. In one example, the DCO receives an undithered stream of incoming digital tuning words, and receives a dithered reference clock signal REFD, and outputs the DCO_OUT signal such that its frequency changes occur at dithered intervals. Where the PLL is employed in the local oscillator of a cellular telephone transmitter, the novel dithering of the DCO spreads digital image noise out in frequency such that less digital image noise is present at a particular frequency offset from the main local oscillator frequency. Spreading digital image noise out in frequency allows a noise specification to be met without having to increase the frequency of the PLL reference clock. By avoiding increasing the frequency of the reference clock to meet the noise specification, increases in power consumption are avoided. | 12-10-2009 |
20090302963 | BI-POLAR MODULATOR - A bi-polar modulator that can perform quadrature modulation using amplitude modulators is described. In one design, the bi-polar modulator includes first and second amplitude modulators and a summer. The first amplitude modulator amplitude modulates a first carrier signal with a first input signal and provides a first amplitude modulated signal. The second amplitude modulator amplitude modulates a second carrier signal with a second input signal and provides a second amplitude modulated signal. The summer sums the first and second amplitude modulated signals and provides a quadrature modulated signal that is both amplitude and phase modulated. The first and second input signals may be obtained based on absolute values of first and second modulating signals, respectively. The first and second carrier signals have phases determined based on the sign of the first and second modulating signals, respectively. Each amplitude modulator may be implemented with a class-E amplifier. | 12-10-2009 |
20090309666 | DYNAMIC CALIBRATION TECHNIQUES FOR DIGITALLY CONTROLLED OSCILLATOR - Techniques for calibrating digitally controlled oscillators (DCOs) are disclosed. In an aspect of the disclosure, an initial set of control codes for operating the DCO is determined. A range of output frequencies produced from the initial set is identified. Gaps or instances of overlap are identified in the frequency range. For the overlap case, control codes are removed from the initial set that correspond to the overlap instance to establish a revised set. For the gap case, control codes are added to the initial set for producing frequencies values that fill the gap. An apparatus for performing the same is also disclosed. | 12-17-2009 |
20100141313 | DIGITAL PHASE-LOCKED LOOP WITH TWO-POINT MODULATION AND ADAPTIVE DELAY MATCHING - A digital phase-locked loop (DPLL) supporting two-point modulation with adaptive delay matching is described. The DPLL includes highpass and lowpass modulation paths that support wideband and narrowband modulation, respectively, of the frequency and/or phase of an oscillator. The DPLL can adaptively adjust the delay of one modulation path to match the delay of the other modulation path. In one design, the DPLL includes an adaptive delay unit that provides a variable delay for one of the two modulation paths. Within the adaptive delay unit, a delay computation unit determines the variable delay based on a modulating signal applied to the two modulation paths and a phase error signal in the DPLL. An interpolator provides a fractional portion of the variable delay, and a programmable delay unit provides an integer portion of the variable delay. | 06-10-2010 |
20100310031 | MULTI-RATE DIGITAL PHASE LOCKED LOOP - A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a DCO output signal and a reference clock and outputs a first stream of digital values. Quantization noise is reduced by clocking the TDC at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate, thereby reducing digital images. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate, thereby further reducing power consumption. | 12-09-2010 |
20100323641 | METHOD AND APPARATUS FOR USING PRE-DISTORTION AND FEEDBACK TO MITIGATE NONLINEARITY OF CIRCUITS - Techniques for mitigating nonlinearity of circuits with both pre-distortion and feedback are described. An apparatus may include at least one circuit (e.g., an upconverter, a power amplifier, etc.), a pre-distortion circuit, and a feedback circuit. The circuit(s) may generate an output signal having distortion components due to their nonlinearity. The pre-distortion circuit may receive an input signal and generate a pre-distorted signal based on at least one coefficient determined by the nonlinearity of the circuit(s). The pre-distortion circuit may adaptively determine the coefficient(s) based on the input signal and an error signal. The feedback circuit may generate the error signal based on the input signal and the output signal and may filter the error signal to obtain a filtered error signal. The circuit(s) may process the pre-distorted signal and the filtered error signal to generate the output signal, which may have attenuated distortion components due to pre-distortion and feedback. | 12-23-2010 |
20130181756 | CONFIGURABLE DIGITAL-ANALOG PHASE LOCKED LOOP - A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop. | 07-18-2013 |
20140155014 | RECEIVER IIP2 ANALOG CALIBRATION - Techniques for performing analog calibration of a receiver to optimize a second-order input intercept point (IIP2). In an aspect, a signal generator modeling an interferer is coupled to an adjustable input of a receiver, e.g., a gate bias voltage of a mixer. For example, the signal generator output may be a single-tone on-off keying (OOK) modulated signal. The mixer mixes the signal down to baseband, wherein an analog correlator correlates the down-converted signal with the known sequence of bits used to perform the OOK modulation. The analog correlation output is then provided to drive the bias voltage in the mixer, e.g., one or more gate voltages of transistors in the differential mixer, to optimize the overall receiver IIP2. Further aspects of the disclosure provide for calibrating receivers having multiple LNA's, and also dual or diversity receivers having multiple receive paths. | 06-05-2014 |
20150015343 | DEVICES AND METHODS FOR REDUCING NOISE IN DIGITALLY CONTROLLED OSCILLATORS - One feature pertains to a digitally controlled oscillator (DCO) that comprises a variable capacitor and noise reduction circuitry. The variable capacitor has a variable capacitance value that controls an output frequency of the DCO. The variable capacitance value is based on a first bank capacitance value provided by a first capacitor bank, a second bank capacitance value provided by a second capacitor bank, and an auxiliary bank capacitance value provided by an auxiliary capacitor bank. The noise reduction circuitry is adapted to adjust the variable capacitance value by adjusting the auxiliary bank capacitance value while maintaining at least one of the first bank capacitance value and/or the second bank capacitance value substantially unchanged. Prior to adjusting the variable capacitance value, the noise reduction circuitry may determine that a received input DCO control word transitions across a capacitor bank sensitive boundary. | 01-15-2015 |