Patent application number | Description | Published |
20090073827 | AUTOMATIC POWER CONTROL SYSTEM FOR OPTICAL DISC DRIVE AND METHOD THEREOF - An automatic power control system, a down sampling circuit and a down sampling method. The automatic power control system is incorporated in an optical disc drive comprising a laser diode for receiving a control signal to generate a laser beam; and a photodetector for detecting the laser beam to generate an analog input signal. The automatic power control system comprises an analog-to-digital converter, a down sampling circuit, a comparator, and a digital-to-analog converter. The analog-to-digital converter converts the analog input signal to digital data. The down sampling circuit, coupled to the analog-to-digital converter, comprises a down sampler, a counter, and a controller. The down sampler receives a predetermined amount of digital data to generate representation data. The counter, coupled to the down sampler, calculates the amount of digital data, and resets the down sampler when the amount equals or exceeds the predetermined count. The controller, coupled to the counter, disables the counter when the digital data is invalid. The comparator, coupled to the down sampling circuit, compares the representation data with predetermined target data to generate error data. The digital-to-analog converter, coupled to the comparator, converts the error data to analog to generate the control signal. | 03-19-2009 |
20090096538 | ALL-DIGITAL PHASE-LOCKED LOOP, LOOP BANDWIDTH CALIBRATION METHOD, AND LOOP GAIN CALIBRATION METHOD FOR THE SAME - For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner. | 04-16-2009 |
20090096539 | Error Protection Method, TDC module, CTDC Module, All-Digital Phase-Locked Loop, and Calibration Method thereof - An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well. | 04-16-2009 |
20090097609 | Error Compensation Method, Digital Phase Error Cancellation Module, and ADPLL thereof - Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop (ADPLL) is compensated by predicting possible phase error, which are predicted according to an estimated quantization error, a period of a digital-controlled oscillator (DCO), a gain of the TDC or a combination thereof. By appropriate inductions, the possible phase error may be further indicated by the quantization error, a code variance corresponding to a half of a reference period received by a TDC module having the TDC, a dividing ratio of a frequency divider of the ADPLL, a fractional number related to the quantization error o a combination thereof. A digital phase error cancellation module is also used for generating the possible phase error for compensating the phase error of the TDC. | 04-16-2009 |
20100117827 | METHOD FOR CURRENT REDUCTION FOR AN ANALOG CIRCUIT IN A DATA READ-OUT SYSTEM - The invention provides a method for current reduction for an analog circuit in a data read-out system. First, a performance indicator, indicating a performance of the data read-out system is generated. The performance indicator is then compared with a performance threshold level to generate a switch signal. A level of a current source biasing the analog circuit is then adjusted according to the switch signal. | 05-13-2010 |
20100264993 | PLL WITH LOOP BANDWIDTH CALIBRATION CIRCUIT - A phase locked loop (PLL) with a loop bandwidth calibration circuit is provided. The mixed-mode PLL comprises an analog phase correction path, a digital frequency correction path, a calibration current source, and a loop bandwidth calibration circuit. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. The calibration current source is coupled to the LPCU. The loop bandwidth calibration circuit is coupled to a frequency divider and coupled between the input and output of the PLL. The loop bandwidth calibration circuit operates after the calibration current source injects a calibration current into the LPCU. | 10-21-2010 |
20100277244 | ALL-DIGITAL PHASE-LOCKED LOOP, LOOP BANDWIDTH CALIBRATION METHOD, AND LOOP GAIN CALIBRATION METHOD FOR THE SAME - For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner. | 11-04-2010 |
20110099450 | Error Protection Method, TDC module, CTDC Module, All-Digital Phase-Locked Loop, and Calibration Method thereof - An error protection method for a time-to-digital converter (TDC) decoder of an all-digital phase-locked loop (ADPLL) includes: retrieving a digital code received by the TDC decoder; retrieving a cycle code received by the TDC decoder; performing an exclusive-or operation on a first predetermined bit of the digital code and a second predetermined bit of the cycle code for generating an error protection code; and using the error protection code to fix errors within the cycle code by adding the error protection code into the cycle code and shifting the cycle code by a third predetermined number of bits. | 04-28-2011 |
20110122747 | Automatic Power Control System for Optical Disc Drive and Method Thereof - An automatic power control system, an automatic power control method, a down sampling circuit and a down sampling method. The automatic power control system is incorporated in an optical disc drive comprising a laser diode for receiving a control signal to generate a laser beam; and a photodetector for detecting the laser beam to generate an analog input signal. The automatic power control system comprises an analog-to-digital converter, a down sampling circuit, a comparator, and a digital-to-analog converter. The analog-to-digital converter converts the analog input signal to digital data. The down sampling circuit, coupled to the analog-to-digital converter, comprises a down sampler, a counter, and a controller. The down sampler receives a predetermined amount of digital data to generate representation data. The counter, coupled to the down sampler, calculates the amount of digital data, and resets the down sampler when the amount equals or exceeds the predetermined count. The controller, coupled to the counter, disables the counter when the digital data is invalid. The comparator, coupled to the down sampling circuit, compares the representation data with predetermined target data to generate error data. The digital-to-analog converter, coupled to the comparator, converts the error data to analog to generate the control signal. | 05-26-2011 |