Patent application number | Description | Published |
20100299297 | SYSTEM FOR ELECTRONIC LEARNING SYNAPSE WITH SPIKE-TIMING DEPENDENT PLASTICITY USING PHASE CHANGE MEMORY - A system, method and computer program product for producing spike-dependent plasticity in an artificial synapse is disclosed. According to one embodiment, a method for producing spike-dependent plasticity in an artificial neuron comprises generating a pre-synaptic spiking event in a first neuron when a total integrated input to the first neuron exceeds a first predetermined threshold. A post-synaptic spiking event is generated in a second neuron when a total integrated input to the second neuron exceeds a second predetermined threshold. After the pre-synaptic spiking event, a first pulse is applied to a pre-synaptic node of a synapse having a phase change memory element. After the post-synaptic spiking event, a second varying pulse is applied to a post-synaptic node of the synapse, wherein current through the synapse is a function of the state of the second varying pulse at the time of the first pulse. | 11-25-2010 |
20110024712 | PCM With Poly-Emitter BJT Access Devices - A phase change memory (PCM) includes an array comprising a plurality of memory cells, a memory cell comprising a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor. A memory cell for a phase change memory (PCM) includes a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor. | 02-03-2011 |
20110038199 | MEASUREMENT METHOD FOR READING MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION - A memory system includes a memory cell configured to represent at least two binary values, a bit line coupled to the memory cell, and first and second comparators coupled to the bit line that, respectively, compare a first and second reference value to a value of a parameter of the bit-line. The system also includes a first and second timers configured to measures a time for the parameter of the bit line to decay. The system also includes a logic unit coupled to the first and second timers that selects the time for the parameter of the bit line to decay from to a first value or a second value. | 02-17-2011 |
20110116307 | PHASE CHANGE MEMORY DEVICE SUITABLE FOR HIGH TEMPERATURE OPERATION - A phase change memory cell that includes a bottom electrode, a top electrode separated from the bottom electrode, and growth-dominated phase change material deposited between the bottom electrode and the top electrode and contacting the bottom electrode and the top electrode and surrounded by insulation material at sidewalls thereof. The phase change memory cell in a reset state only includes an amorphous phase of the growth-dominated phase change material within an active volume of the phase change memory cell. | 05-19-2011 |
20110119214 | AREA EFFICIENT NEUROMORPHIC CIRCUITS - A neuromorphic circuit includes a first field effect transistor in a first diode configuration establishing an electrical connection between a first gate and a first drain of the first field effect transistor. The neuromorphic circuit also includes a second field effect transistor in a second diode configuration establishing an electrical connection between a second gate and a second drain of the second field effect transistor. The neuromorphic circuit further includes variable resistance material electrically connected to both the first drain and the second drain, where the variable resistance material provides a programmable resistance value. The neuromorphic circuit additionally includes a first junction electrically connected to the variable resistance material and providing a first connection point to an output of a neuron circuit, and a second junction electrically connected to the variable resistance material and providing a second connection point to the output of the neuron circuit. | 05-19-2011 |
20110119215 | HARDWARE ANALOG-DIGITAL NEURAL NETWORKS - An analog-digital crosspoint-network includes a plurality of rows and columns, a plurality of synaptic nodes, each synaptic node of the plurality of synaptic nodes disposed at an intersection of a row and column of the plurality of rows and columns, wherein each synaptic node of the plurality of synaptic nodes includes a weight associated therewith, a column controller associated with each column of the plurality of columns, wherein each column controller is disposed to enable a weight change at a synaptic node in communication with said column controller, and a row controller associated with each row of the plurality of rows, wherein each row controller is disposed to control a weight change at a synaptic node in communication with said row controller. | 05-19-2011 |
20110134676 | RESISTIVE MEMORY DEVICES HAVING A NOT-AND (NAND) STRUCTURE - Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element. | 06-09-2011 |
20110153533 | PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN AN ULTRA-DENSE SYNAPSE CROSS-BAR ARRAY - Embodiments of the invention relate to producing spike-timing dependent plasticity in an ultra-dense synapse cross-bar array for neuromorphic systems. An aspect of the invention includes when an electronic neuron spikes, an alert pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When the spiking electronic neuron sends the alert pulse, a gate pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When each electronic neuron receives the alert pulse, a response pulse is sent from each electronic neuron receiving the alert pulse to the spiking electronic neuron. The response pulse is a function of time since a last spiking of the electronic neuron receiving the alert pulse. In addition, the combination of the gate pulse and response pulse is capable increasing or decreasing conductance of a variable state resistor. | 06-23-2011 |
Patent application number | Description | Published |
20100328995 | METHODS AND APPARATUS FOR REDUCING DEFECT BITS IN PHASE CHANGE MEMORY - Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics. | 12-30-2010 |
20110069538 | MULTI-LEVEL CELL PROGRAMMING OF PCM BY VARYING THE RESET AMPLITUDE - A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse. | 03-24-2011 |
20120018845 | Polysilicon Plug Bipolar Transistor For Phase Change Memory - Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base. | 01-26-2012 |
20120120701 | TERNARY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES - A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care. | 05-17-2012 |
20120140554 | COMPACT LOW-POWER ASYNCHRONOUS RESISTOR-BASED MEMORY READ OPERATION AND CIRCUIT - A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states. | 06-07-2012 |
20120147666 | PHASE CHANGE MATERIAL CELL WITH STRESS INDUCER LINER - An example embodiment disclosed is a phase change memory cell. The memory cell includes a phase change material and a transducer positioned proximate the phase change material. The phase change material is switchable between at least an amorphous state and a crystalline state. The transducer is configured to activate when the phase change material is changed from the amorphous state to the crystalline state. In a particular embodiment, the transducer is ferroelectric material. | 06-14-2012 |
20130026436 | PHASE CHANGE MEMORY ELECTRODE WITH SHEATH FOR REDUCED PROGRAMMING CURRENT - An example embodiment is a phase change memory cell that includes a bottom contact and an electrically insulating layer disposed over the bottom contact. The electrically insulating layer defines an elongated via. Furthermore, a bottom electrode is disposed at least partially in the via. The bottom electrode includes a sleeve of a first electrically conductive material surrounding a rod of a second electrically conductive material. The first electrically conductive material and the second electrically conductive material have different specific electrical resistances. The memory cell also includes a phase change layer electrically coupled to the first electrode. | 01-31-2013 |
20130173515 | ELECTRONIC SYNAPSES FROM STOCHASTIC BINARY MEMORY DEVICES - According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state. | 07-04-2013 |
20130173516 | ELECTRONIC SYNAPSES FROM STOCHASTIC BINARY MEMORY DEVICES - According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state. | 07-04-2013 |
20130299768 | THERMALLY INSULATED PHASE CHANGE MATERIAL CELLS - Memory cell structures for phase change memory. An example memory cell structure comprising includes a bottom electrode comprised of electrically conducting material, and phase change material disposed above the bottom electrode. A layer of thermally insulating material is disposed, at least partially, between the bottom electrode and the phase change material. The thermally insulating material is comprised of Tantalum Oxide. A top electrode is comprised of electrically conducting material. | 11-14-2013 |
20130309782 | PHASE CHANGE MATERIAL CELL WITH PIEZOELECTRIC OR FERROELECTRIC STRESS INDUCER LINER - An example embodiment disclosed is a process for fabricating a phase change memory cell. The method includes forming a bottom electrode, creating a pore in an insulating layer above the bottom electrode, depositing piezoelectric material in the pore, depositing phase change material in the pore proximate the piezoelectric material, and forming a top electrode over the phase change material. Depositing the piezoelectric material in the pore may include conforming the piezoelectric material to at least one wall defining the pore such that the piezoelectric material is deposited between the phase change material and the wall. The conformal deposition may be achieved by chemical vapor deposition (CVD) or by atomic layer deposition (ALD). | 11-21-2013 |
20140078837 | COMPACT LOW-POWER ASYNCHRONOUS RESISTOR-BASED MEMORY READ OPERATION AND CIRCUIT - A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states. | 03-20-2014 |
20140241048 | PHASE CHANGE MEMORY MANAGEMENT - A three dimensional (3D) stack of phase change memory (PCM) devices which includes PCM devices stacked in a 3D array, the PCM devices having memory regions; a memory management unit on at least one of the PCM devices; a stack controller in the memory management unit to monitor an ambient device temperature (T | 08-28-2014 |
Patent application number | Description | Published |
20140094117 | ESTABLISHING COMMUNICATION BETWEEN DEVICES USING CLOSE PROXIMITY PROTOCOL - Methods and devices detect a near field communication (NFC) from a near field wireless communication device of an external computerized device, using an apparatus near field wireless communication device. Based on detecting the NFC, the methods/devices generate random identification and security codes, transmit the identification code and the security code from the apparatus near field wireless communication device to the device near field wireless communication device, and place the previously inactive apparatus wide-range wireless communication device in an active state. In response, the method receives the security code from a wide-range wireless communication device of the external computerized device using the apparatus wide-range wireless communication device. Then the method establishes a network communication session only between the external computerized device and the apparatus based on receiving the security code. | 04-03-2014 |
20140292496 | SYSTEM AND METHOD FOR VERIFYING PHYSICAL PROXIMITY TO A NETWORK DEVICE - Systems and methods for verifying physical proximity to a network device are provided. The method includes acquiring a tag identifier from a tag fixed in, on, or proximal to a network device, using a computing device. The tag is configured to be read and written to by electronic communication with the computing device, when the computing device is disposed in proximity to the tag. The method further includes transmitting data indicative of the tag identifier to a server, and receiving an authorization confirmation from the server. The method also includes rewriting the tag so as to replace the tag identifier with a new tag identifier, using the computing device, and performing one or more operations with the network device after receiving the authorization. | 10-02-2014 |
20140304333 | MULTI-FUNCTION DEVICE APPLICATION CATALOG WITH INTEGRATED DISCOVERY, MANAGEMENT, AND APPLICATION DESIGNER - Systems, methods, and computer-readable media for managing extensibility, e.g., on a network of multi-function devices are provided. The system includes an application catalog, in communication with an application database of a catalog server and configured to load applications therefrom. The system also includes a device manager configured to discover one or more devices on a network and to allow selection of one or more selected devices from among the one or more devices. The system further includes a data transfer system in communication with the one or more devices and to cause an application to be transmitted from the application catalog to the one or more selected devices, such that the one or more selected devices receive the application without communicating directly with the application database. | 10-09-2014 |
20140307167 | METHODS AND SYSTEMS FOR OPTIMIZING VISUAL DATA COMMUNICATION - A system and method for transmitting visual data by displaying a synchronization video that includes synchronization code sequences on a first device, capturing the synchronization video using a video camera of a second device, parsing and decoding the synchronization code sequences on the second device, displaying an indication of which of the synchronization code sequences are compatible for visual data transmission on the second device, receiving a selected synchronization code sequence of the synchronization code sequences on the first device, and displaying a data code sequence corresponding to the selected synchronization code sequence on the first device, wherein the data code sequence includes encoded data, and capturing and decoding the data code sequence on the second device. | 10-16-2014 |
Patent application number | Description | Published |
20100106722 | Synthetic Audiovisual Description Scheme, Method and System for MPEG-7 - A method and system for description of synthetic audiovisual content makes it easier for humans, software components or devices to identify, manage, categorize, search, browse and retrieve such content. For instance, a user may wish to search for specific synthetic audiovisual objects in digital libraries, Internet web sites or broadcast media; such a search is enabled by the invention. Key characteristics of synthetic audiovisual content itself such as the underlying 2d or 3d models and parameters for animation of these models are used to describe it. More precisely, to represent features of synthetic audiovisual content, depending on the description scheme to be used, a number of descriptors are selected and assigned values. The description scheme instantiated with descriptor values is used to generate the description, which is then stored for actual use during query/search. Typically, a user, to search for a needed synthetic audiovisual content initiates a query that is passed on to a search engine that then retrieves the candidate content from one or more databases whose description closely matches the query criteria specified by the user. | 04-29-2010 |
20150058361 | SYNTHETIC AUDIOVISUAL DESCRIPTION SCHEME, METHOD AND SYSTEM FOR MPEG-7 - A method and system for description of synthetic audiovisual content makes it easier for humans, software components or devices to identify, manage, categorize, search, browse and retrieve such content. For instance, a user may wish to search for specific synthetic audiovisual objects in digital libraries, Internet web sites or broadcast media; such a search is enabled by the invention. Key characteristics of synthetic audiovisual content itself such as the underlying 2d or 3d models and parameters for animation of these models are used to describe it. To represent features of synthetic audiovisual content, depending on the description scheme to be used, a number of descriptors are selected and assigned values. The description scheme instantiated with descriptor values is used to generate the description, which is then stored for actual use during query/search. | 02-26-2015 |