Patent application number | Description | Published |
20080246071 | MOS VARACTORS WITH LARGE TUNING RANGE - A MOS varactor includes a shallow PN junction beneath the surface of the substrate of a MOS structure. In depletion mode, the depletion region of the MOS structure merges with the depletion region of the shallow PN junction. This increases the total width of the depletion region of the MOS varactor to reduce C | 10-09-2008 |
20080246119 | LARGE TUNING RANGE JUNCTION VARACTOR - Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias. | 10-09-2008 |
20090072310 | SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE - A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure. | 03-19-2009 |
20090146258 | SELF-ALIGNED VERTICAL PNP TRANSISTOR FOR HIGH PERFORMANCE SiGe CBiCMOS PROCESS - A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction. | 06-11-2009 |
20100109097 | INTEGRATED CIRCUIT SYSTEM EMPLOYING AN ELEVATED DRAIN - A method for manufacturing an integrated circuit system that includes: providing a substrate including an active device; forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and forming a drain above the drift region. | 05-06-2010 |
20100117133 | MOS VARACTORS WITH LARGE TUNING RANGE - A device is presented. The device includes a substrate with a first well of a first polarity type. The first well defines a varactor region and comprises a lower first well boundary located above a bottom surface of the substrate. A second well in the varactor region is also included in the device. The second well comprises a buried well of a second polarity type having an upper second well boundary disposed below an upper portion of the first well from an upper first well boundary to the upper second well boundary and a lower second well boundary disposed above the lower first well boundary, wherein an interface of the second well and the upper portion of the first well forms a shallow PN junction in the varactor region. The device also includes a gate structure in the varactor region. The upper portion of the first well beneath the gate structure forms a channel region of the device. In depletion mode, a depletion region under the gate structure in the channel region merges with a depletion region of the shallow PN junction. | 05-13-2010 |
20100213543 | HIGH VOLTAGE DEVICE - A method of forming a device is presented. The method includes providing a substrate prepared with an active device region. The active device region includes gate stack layers of a gate stack including at least a gate electrode layer over a gate dielectric layer. A first mask is provided on the substrate corresponding to the gate. The substrate is patterned to at least remove portions of a top gate stack layer unprotected by the first mask. A second mask is also provided on the substrate with an opening exposing a portion of the first mask and the top gate stack layer. A channel well is formed by implanting ions through the opening and gate stack layers into the substrate. | 08-26-2010 |
20100213544 | HIGH VOLTAGE DEVICE - A method of forming a device is presented. A substrate prepared with an active device region is provided. The active device region includes gate stack layers of a gate stack that includes at least a gate electrode layer over a gate dielectric layer. An implant mask is formed on the substrate with an opening exposing a portion of a top gate stack layers. Ions are implanted through the opening and gate stack layers into the substrate to form a channel well. The substrate is patterned to at least remove portion of a top gate stack layer unprotected by the implant mask. | 08-26-2010 |
20100320529 | INTEGRATED CIRCUIT SYSTEM WITH HIGH VOLTAGE TRANSISTOR AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration; forming an isolation region around the active region; forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region; and applying an isolation edge implant, with the impurities of the first type at a third concentration greater than or equal to the second concentration, for suppressing the parasitic transistor. | 12-23-2010 |
20110042743 | LDMOS Using A Combination of Enhanced Dielectric Stress Layer and Dummy Gates - First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprise forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region | 02-24-2011 |
20110079850 | SEMICONDUCTOR STRUCTURE INCLUDING HIGH VOLTAGE DEVICE - A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure. | 04-07-2011 |
20110156121 | MEMORY CELL WITH IMPROVED RETENTION - A method for forming a device is presented. A substrate prepared with a feature having first and second adjacent surfaces is provided. A device layer is formed on the first and second adjacent surfaces of the feature. A first portion of the device layer over the first adjacent surface includes nano-crystals, whereas a second portion of the device layer over the second adjacent surface is devoid of nano-crystals. | 06-30-2011 |
20120098041 | SELF-ALIGNED BODY FULLY ISOLATED DEVICE - A device having a self-aligned body on a first side of a gate is disclosed. The self-aligned body helps to achieve very low channel length for low Rdson. The self-aligned body is isolated, enabling to bias the body at different bias potentials. The device may be configured into a finger architecture having a plurality of transistors with commonly coupled, sources, commonly coupled gates, and commonly coupled drains to achieve high drive current outputs. | 04-26-2012 |
20120280318 | HIGH VOLTAGE DEVICE - A device is disclosed. The device includes s substrate prepared with an active device region. The active device region includes a gate. The device also includes a doped channel well disposed in the substrate adjacent to a first edge of the gate. The first edge of the gate overlaps the channel well with a channel edge of the channel well beneath the gate. The first edge of the gate and channel edge defines an effective channel length of the device. The effective channel length is self-aligned to the gate. A doped drift well adjacent to a second edge of the gate is also included. | 11-08-2012 |
20130001688 | SELF-ALIGNED BODY FULLY ISOLATED DEVICE - A device having a self-aligned body on a first side of a gate is disclosed. The self-aligned body helps to achieve very low channel length for low Rdson. The self-aligned body is isolated, enabling to bias the body at different bias potentials. The device may be configured into a finger architecture having a plurality of transistors with commonly coupled, sources, commonly coupled gates, and commonly coupled drains to achieve high drive current outputs. | 01-03-2013 |
20130026565 | LOW RDSON RESISTANCE LDMOS - A device having a salicide block spacer on a second side of a gate is disclosed. The use of the salicide block spacer indirectly reduces the blocking effects during the implantation processes, thereby lowering the Rdson without compromising the breakdown voltage of the device. | 01-31-2013 |
20130062691 | SEMICONDUCTOR DEVICE INCLUDING AN N-WELL STRUCTURE - A device comprising a p-type base region, and a p-type region formed over the p-type base region and in contact with the p-type base region is disclosed. The device also includes an n-well region surrounded by the p-type region, wherein the n-well is formed from an n-type epitaxial layer and the p-type region is formed by counter-doping the same n-type epitaxial layer. | 03-14-2013 |
20130069144 | TRENCH TRANSISTOR - A method of forming a device is disclosed. A substrate defined with a device region is provided. A buried doped region is formed in the substrate in the device region. A gate is formed in a trench in the substrate in the device region. A channel of the device is disposed on a sidewall of the trench. The buried doped region is disposed below the gate. A distance from the buried doped region to the channel is a drift length L | 03-21-2013 |
20130074016 | METHODOLOGY FOR PERFORMING POST LAYER GENERATION CHECK - There is provided a method comprising receiving data corresponding to a layout design for a plurality of input mask layers and generating a layout design for at least one generated mask layer. The relationship between a first geometric element in a first layout pattern comprising one or more of the generated mask layers and a second geometric element in a second layout pattern is then determined and verified to check if they comply with predetermined rules. If the relationship does not conform with the predetermined rules the design of at least one of the generated mask layers associated with the first or second layout pattern is modified. | 03-21-2013 |
20130093012 | HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain. | 04-18-2013 |
20130181287 | HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate and a drain region defined thereon. A drift well is formed in the substrate adjacent to a second side of the gate. The drift well underlaps a portion of the gate with a first edge of the drift well beneath the gate. A secondary portion is formed in the drift well. The secondary portion underlaps a portion of the gate with a first edge of the secondary portion beneath the gate. The first edge of the secondary portion is offset from the first edge of the drift well. A gate dielectric of the gate comprises a first portion having a first thickness and a second portion having a second thickness. The second portion is over the secondary portion. | 07-18-2013 |
20130187218 | ESD PROTECTION CIRCUIT - A device which includes a substrate defined with a device region having an ESD protection circuit is disclosed. The ESD protection circuit has a transistor. The transistor includes a gate having first and second sides. A first diffusion region is disposed adjacent to the first side of the gate and a second diffusion region is disposed in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. A drift isolation region is disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. A drain well having dopants of the first polarity type is disposed under the second diffusion region and within the first device well. | 07-25-2013 |
20130187224 | INTEGRATION OF TRENCH MOS WITH LOW VOLTAGE INTEGRATED CIRCUITS - A high voltage trench MOS and its integration with low voltage integrated circuits is provided. Embodiments include forming, in a substrate, a first trench with a first oxide layer on side surfaces; a narrower second trench, below the first trench with a second oxide layer on side and bottom surfaces, and spacers on sides of the first and second trenches; removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers; filling the first and second trenches with a first poly-silicon to form a drain region; removing the spacers, exposing side surfaces of the first poly-silicon; forming a third oxide layer on side and top surfaces of the first poly-silicon; and filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region. | 07-25-2013 |
20130277741 | LDMOS DEVICE WITH FIELD EFFECT STRUCTURE TO CONTROL BREAKDOWN VOLTAGE, AND METHODS OF MAKING SUCH A DEVICE - In one embodiment of an LDMOS device disclosed herein, the device includes a source region, a drain region and a gate electrode that are formed in and above a semiconducting substrate, wherein the gate electrode is generally laterally positioned between the source region and the drain region, a metal-1 field plate positioned above the gate electrode, and a silicide block layer that is positioned in an area between the gate electrode and the drain region. The device further includes at least one source contact that is conductively coupled to the metal-1 field plate and a conductive structure that is conductively coupled to the metal-1 field plate, wherein at least a first portion of the conductive structure extends downward toward the substrate in the area between the gate electrode and the drain region. | 10-24-2013 |
20130292759 | TRENCH TRANSISTOR - A method of forming a device is disclosed. A substrate defined with a device region is provided. A buried doped region is formed in the substrate in the device region. A gate is formed in a trench in the substrate in the device region. A channel of the device is disposed on a sidewall of the trench. The buried doped region is disposed below the gate. A distance from the buried doped region to the channel is a drift length LD of the device. A surface doped region is formed adjacent to the gate. | 11-07-2013 |
20130320497 | ON-CHIP RESISTOR - An integrated circuit (IC) is disclosed. The IC includes a substrate with a resistor region and a resistor body disposed on the resistor region. A plurality of first resistor contact strips and a plurality of second resistor contact strips are disposed on the resistor body along a first direction. Two adjacent first and second resistor contact strips are separated by a respective one of contact strip spaces. The IC includes a plurality of first terminals and a plurality of second terminals. Each of the first terminals is coupled to a respective one of the first resistor contact strips while each of the second terminals is coupled to a respective one of the second resistor contact strips. A set of the first terminal and the second terminal forms first and second terminals of an on-chip resistor. | 12-05-2013 |
20130334601 | HIGH VOLTAGE TRENCH TRANSISTOR - A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having a gate electrode, first and second gate dielectric layers is formed in a trench. The trench has an upper trench portion and a lower trench portion. A field plate is formed in the trench. First and second diffusion regions are formed. The gate is displaced from the second diffusion region. | 12-19-2013 |
20140021534 | INTEGRATION OF HIGH VOLTAGE TRENCH TRANSISTOR WITH LOW VOLTAGE CMOS TRANSISTOR - A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having an upper and a lower portion is formed in a trench in the substrate in the device region. The upper portion forms a gate electrode and the lower portion forms a gate field plate. First and second surface doped regions are formed adjacent to the gate. The gate field plate introduces vertical reduced surface (RESURF) effect in a drift region of the device. | 01-23-2014 |
20140042499 | STRESS ENHANCED HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate region and a drain region defined thereon. A gate is formed in the gate region, a source is formed in the source region and drain is formed in the drain region. A trench is formed in an isolation region in the device region. The isolation region underlaps a portion of the gate. An etch stop (ES) stressor layer is formed over the substrate. The ES stressor layer lines the trench. | 02-13-2014 |
20140048874 | MOS WITH RECESSED LIGHTLY-DOPED DRAIN - LDD regions are provided with high implant energy in devices with reduced thickness poly-silicon layers and source/drain junctions. Embodiments include forming an oxide layer on a substrate surface, forming a poly-silicon layer over the oxide layer, forming first and second trenches through the oxide and poly-silicon layers and below the substrate surface, defining a gate region therebetween, implanting a dopant in a LDD region through the first and second trenches, forming spacers on opposite side surfaces of the gate region and extending into the first and second trenches, and implanting a dopant in a source/drain region below each of the first and second trenches. | 02-20-2014 |
20140070310 | INTEGRATION OF TRENCH MOS WITH LOW VOLTAGE INTEGRATED CIRCUITS - A high voltage trench MOS and its integration with low voltage integrated circuits. Embodiments include forming a first trench in a substrate, the first trench having a first width; forming a first oxide layer on side surfaces of the first trench; forming a second trench in the substrate, below the first trench, the second trench having a second width less than the first width; forming a second oxide layer on side and bottom surfaces of the second trench; forming spacers on sides of the first and second trenches; removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers; filling the first and second trenches with a first poly-silicon to form a drain region; removing the spacers, exposing side surfaces of the first poly-silicon; forming a third oxide layer on the side surfaces and a top surface of the first poly-silicon; and filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region. | 03-13-2014 |
20140203325 | INTEGRATION OF GERMANIUM PHOTO DETECTOR IN CMOS PROCESSING - A method and device are provided for forming an integrated Ge or Ge/Si photo detector in the CMOS process by non-selective epitaxial growth of the Ge or Ge/Si. Embodiments include forming an N-well in a Si substrate; forming a transistor or resistor in the Si substrate; forming an ILD over the Si substrate and the transistor or resistor; forming a Si-based dielectric layer on the ILD; forming a poly-Si or a-Si layer on the Si-based dielectric layer; forming a trench in the poly-Si or a-Si layer, the Si-based dielectric layer, the ILD, and the N-well; forming Ge or Ge/Si in the trench; and removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the Si-based dielectric layer down to an upper surface of the ILD. Further aspects include forming an in-situ doped Si cap epilayer or an ex-situ doped poly-Si or a-Si cap layer on the Ge or Ge/Si. | 07-24-2014 |
20140264584 | LATERAL DOUBLE-DIFFUSED HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. The method includes providing a substrate with a device region. The method also includes forming a transistor in the device region. The transistor includes a gate having first and second sides along a gate direction. The transistor also includes a first doped region adjacent to a first side of the gate, a second doped region adjacent to a second side of the gate, and a channel under the gate. The transistor further includes a channel trench in the channel of the gate, wherein the channel trench is along a trench direction which is at an angle θ other than 90° with respect to the gate direction. | 09-18-2014 |
20140319607 | MOS WITH RECESSED LIGHTLY-DOPED DRAIN - LDD regions are provided with high implant energy in devices with reduced thickness poly-silicon layers and source/drain junctions. Embodiments include forming an oxide layer on a substrate surface, forming a poly-silicon layer over the oxide layer, forming first and second trenches through the oxide and poly-silicon layers and below the substrate surface, defining a gate region therebetween, implanting a dopant in a LDD region through the first and second trenches, forming spacers on opposite side surfaces of the gate region and extending into the first and second trenches, and implanting a dopant in a source/drain region below each of the first and second trenches. | 10-30-2014 |
20140320174 | INTEGRATED CIRCUITS WITH LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR STRUCTURES - Integrated circuits with improved LDMOS structures are provided. An integrated circuit includes a semiconductor substrate, a plurality of shallow trench isolation (STI) regions, each extending at least a first depth below an upper surface of the semiconductor substrate. The STI regions electrically isolate devices fabricated in the semiconductor substrate. The integrated circuit further includes a transistor structure. The transistor structure includes a gate dielectric positioned over a portion of a first one of the plurality of STI regions, a drain region adjacent to the first one of the plurality of STI regions and spaced apart from the gate dielectric, a first gate electrode that extends over a first portion of the gate dielectric, a second gate electrode that extends over a second portion of the gate dielectric and positioned adjacent to the first gate electrode, and a source region positioned adjacent to the first portion of the gate dielectric. | 10-30-2014 |
20140332884 | HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain. | 11-13-2014 |
20140332887 | SILICON-ON-INSULATOR INTEGRATED CIRCUITS WITH LOCAL OXIDATION OF SILICON AND METHODS FOR FABRICATING THE SAME - Silicon-on-insulator integrated circuits with local oxidation of silicon and methods for fabricating the same are provided. An integrated circuit includes a semiconductor substrate and a plurality of shallow trench isolation (STI) regions, each extending at least a first depth below an upper surface of the semiconductor substrate. The STI regions electrically isolate devices fabricated in the semiconductor substrate. The integrated circuit further includes a transistor that includes source and drain regions located in the semiconductor substrate, a gate dielectric layer located between the source and drain regions, and a local oxide layer located in a second portion of the semiconductor substrate and extending a second depth below the upper surface of the semiconductor substrate. The first depth is greater than the second depth. Still further, the integrated circuit includes a first gate electrode that extends over the gate dielectric layer and the local oxide layer. | 11-13-2014 |
20150016769 | SEMICONDUCTOR DEVICES INCLUDING PHOTODETECTORS INTEGRATED ON WAVEGUIDES AND METHODS FOR FABRICATING THE SAME - Semiconductor devices and methods for fabricating semiconductor devices are provided. In one example, a method for fabricating a semiconductor device includes etching a waveguide layer in a detector region of a semiconductor substrate to form a recessed waveguide layer section. A ridge structure germanium (Ge) photodetector is formed overlying a portion of the recessed waveguide layer section. | 01-15-2015 |