Patent application number | Description | Published |
20090146243 | Semiconductor Device Having Recessed Channel and Method for Manufacturing the Same - A semiconductor device having a recessed channel and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate formed with an isolation layer defining an active region including a channel region and a junction region, a recessed trench including a top trench formed within the channel region of the semiconductor substrate and a bottom trench formed from a bottom surface of the top trench with a width narrower than the top trench, and a gate stack overlapping the recessed trench and extending across the active region. | 06-11-2009 |
20090278183 | Semiconductor Device with Channel of Fin Structure and Method for Manufacturing the Same - Provided are a semiconductor device with a channel of a FIN structure and a method for manufacturing the same. In the method, a device isolation layer defining an active region is formed on a semiconductor substrate. A recess trench with a first width is formed in the active region, and a trench with a second width larger than the first width is formed in the device isolation layer. The trench formed in the device isolation layer is filled with a capping layer. A cleaning process is performed on the recess trench to form a bottom protrusion of a FIN structure including a protrusion and a sidewall. Gate stacks filling the recess trench are formed. A landing plug, which is divided by the capping layer filling the trench, is formed between the gate stacks. | 11-12-2009 |
20100159683 | Method for Fabricating Semiconductor Device Having Recess Channel - A method for fabricating a semiconductor device having a recess channel includes forming an isolation layer that delimits an active region over a semiconductor substrate; exposing a region to be formed with a bulb recess trench over the semiconductor substrate; forming an upper trench by etching the exposed portion of the semiconductor substrate; forming, on a side wall of the upper trench, a silicon nitride barrier layer that exposes a bottom face of the upper trench but blocks a side wall of the upper trench; forming a lower trench of a bulb type by etching the exposed bottom face of the upper trench using the etch barrier layer as an etch mask, to form the bulb recess trench including the upper trench and the lower trench; forming a fin-structured bottom protrusion part including an upper face and a side face by etching the isolation layer so that the isolation layer has a surface lower than the bottom face of the lower trench; and forming a gate stack overlapped with the bulb recess trench and the bottom protrusion part. | 06-24-2010 |
20100163976 | Semiconductor Device Having Saddle Fin Transistor and Method for Fabricating the Same - A method for fabricating a semiconductor device includes forming a pad nitride layer that exposes an isolation region over a cell region of a semiconductor substrate; forming a trench in the isolation region of the semiconductor substrate; forming an isolation layer within the trench; etching an active region of the semiconductor substrate by a certain depth to form a recessed isolation region; etching the isolation layer by a certain depth to form a recessed isolation region; depositing a gate metal layer in the recessed active region and the recessed isolation region to form a gate of a cell transistor; forming an insulation layer over an upper portion of the gate; removing the pad nitride layer to expose a region of the semiconductor substrate to be formed with a contact plug; and depositing a conductive layer in the region of the semiconductor substrate to form a contact plug. | 07-01-2010 |
20100167211 | METHOD FOR FORMING FINE PATTERNS IN A SEMICONDUCTOR DEVICE - A method for forming fine patterns in a semiconductor device includes forming a first mask layer over an etch target layer, forming a first pattern over the first mask layer, reducing a size of the first pattern, forming a first spacer on a side face of the first pattern, removing the first pattern and patterning the first mask layer using the first spacer as a mask and removing the first spacer. The method also includes oxidating a surface of the patterned first mask layer, forming the first mask layer with reduced size by removing the oxidated portion over the surface of the first mask layer, forming a second spacer on a side wall of the first mask layer and removing the first mask layer, and patterning the etch target layer using the second spacer as a mask. | 07-01-2010 |
20100279497 | Method for Manufacturing Semiconductor Device with a Recessed Channel - A semiconductor device having a recessed channel and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate formed with an isolation layer defining an active region including a channel region and a junction region, a recessed trench including a top trench formed within the channel region of the semiconductor substrate and a bottom trench formed from a bottom surface of the top trench with a width narrower than the top trench, and a gate stack overlapping the recessed trench and extending across the active region. | 11-04-2010 |
20110027966 | Method for Fabricating Isolation Layer in Semiconductor Device - A method for fabricating an isolation layer in a semiconductor device, comprising: forming a trench in a semiconductor substrate; forming a flowable insulation layer on the trench and the semiconductor substrate; converting the flowable insulation layer to a silicon oxide layer by implementing a curing process comprising continuously heating the flowable insulation layer; and forming an isolation layer by planarizing the silicon oxide layer. | 02-03-2011 |
20110159677 | METHOD OF FABRICATING LANDING PLUG CONTACT IN SEMICONDUCTOR MEMORY DEVICE - A landing plug contact in a semiconductor memory device is fabricated by: forming gate spacer layers at sides of the gate stacks to define a first contact hole and a second contact hole, where a landing plug contact will be formed between the gate spacer layers of the first contact hole and no landing plug contact is formed in the second contact hole; forming a conductive layer to fill at least the first and second contact holes; forming a hard mask pattern over the conductive layer to expose the conductive layer filling the second contact hole; removing the conductive layer filling the second contact hole by an etching process; forming an insulation layer to fill at least the second contact hole where the conductive layer is removed; and forming a landing plug contact within the contact hole by performing a planarization process on the insulation layer and the conductive layer. | 06-30-2011 |
20130193549 | SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE PLUGS AND METHODS OF MANUFACTURING THE SAME - Methods of manufacturing a semiconductor device are provided. The method includes forming an isolation region in a substrate to define active regions extending in a single direction and being spaced apart from each other by the isolation region, forming a conductive layer in the isolation region and the active regions, etching the conductive layer to form bit line trenches extending in a first direction that is non-perpendicular to the single direction, forming bit line patterns in respective ones of the bit line trenches, etching the conductive layer to form a plurality of plug trenches two dimensionally arrayed along the first direction and a second direction perpendicular to the first direction, and filling the plug trenches with an insulation material to define conductive plug patterns in portions of the active regions. Related semiconductor devices are also provided. | 08-01-2013 |
20130244413 | Method for Fabricating a Semiconductor Device Having a Saddle Fin Transistor - A method for fabricating a semiconductor device includes forming a pad nitride layer that exposes an isolation region over a cell region of a semiconductor substrate; forming a trench in the isolation region of the semiconductor substrate; forming an isolation layer within the trench; etching an active region of the semiconductor substrate by a certain depth to form a recessed isolation region; etching the isolation layer by a certain depth to form a recessed isolation region; depositing a gate metal layer in the recessed active region and the recessed isolation region to form a gate of a cell transistor; forming an insulation layer over an upper portion of the gate; removing the pad nitride layer to expose a region of the semiconductor substrate to be formed with a contact plug; and depositing a conductive layer in the region of the semiconductor substrate to form a contact plug. | 09-19-2013 |
20140035018 | SEMICONDUCTOR DEVICES INCLUDING VERTICAL TRANSISTORS AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a first capacitor in a trench of a semiconductor substrate and an active pillar disposed on the semiconductor substrate opposite the first capacitor. The active pillar includes first region, first channel region, second region, second channel region and third region, sequentially stacked. A pillar connection pattern electrically connects the first capacitor to a first source region. A first gate electrode is disposed on a sidewall of the first channel region. A common drain region is disposed in the second region, and a common bit line is disposed on a sidewall of the common drain region. A second gate electrode is disposed on a sidewall of the second channel region, and a second source region is disposed in the third region. A second capacitor is disposed on a top surface of the second source region opposite the second channel region. | 02-06-2014 |
20140061780 | SEMICONDUCTOR DEVICE INCLUDING A GATE DIELECTRIC LAYER - A semiconductor device is fabricated by, inter alia, forming a sacrificial liner on an active portion of a semiconductor substrate, oxidizing the sacrificial liner to transform the sacrificial liner into a gate dielectric layer, and forming a gate on the gate dielectric layer. | 03-06-2014 |