Patent application number | Description | Published |
20090072253 | SEMICONDUCTOR LIGHT EMITTING DEVICE, METHOD FOR MANUFACTURING SAME, AND METHOD FOR FORMING UNDERLYING LAYER - Disclosed herein is a semiconductor light emitting device including: (A) an underlying layer configured to be formed on a major surface of a substrate having a {100} plane as the major surface; (B) a light emitting part; and (C) a current block layer, wherein the underlying layer is composed of a III-V compound semiconductor and is formed on the major surface of the substrate by epitaxial growth, the underlying layer extends in parallel to a <110> direction of the substrate, a sectional shape of the underlying layer obtained when the underlying layer is cut along a virtual plane perpendicular to the <110> direction of the substrate is a trapezoid, and oblique surfaces of the underlying layer corresponding to two oblique sides of the trapezoid are {111}B planes, and the top surface of the underlying layer corresponding to an upper side of the trapezoid is a {100} plane. | 03-19-2009 |
20090072266 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed herein is a semiconductor light emitting device including: a light emitting part formed of a multilayer structure arising from sequential stacking of a first compound semiconductor layer, an active layer, and a second compound semiconductor layer; a current block layer; and a burying layer, wherein a planar shape of the active layer is a strip shape in which a width of a center part is smaller than a width of both end parts, the current block layer is composed of third and fourth compound semiconductor layers, the burying layer is formed of a multilayer structure arising from sequential stacking of a first burying layer and a second burying layer, and an impurity for causing the second burying layer is such that a substitution site of the impurity in the second burying layer does not compete with a substitution site of an impurity in the third compound semiconductor layer. | 03-19-2009 |
20090137076 | SURFACE EMITTING SEMICONDUCTOR LASER, ITS MANUFACTURING METHOD, AND MANUFACTURING METHOD OF ELECTRON DEVICE - A surface emitting semiconductor laser which can perform laser oscillation in a single peak beam like that in a single lateral mode and a manufacturing method which can easily manufacture such a laser at a high yield are provided. When a surface emitting semiconductor laser having a post type mesa structure is formed on an n-type semiconductor substrate, a mesa portion is formed and up to a p-side electrode and an n-side electrode are formed. Thereafter, a voltage is applied across the p-side and n-side electrodes and the laser is subjected to a steam atmosphere while extracting output light, thereby forming an Al oxide layer onto a p-type Al | 05-28-2009 |
20100009485 | SEMICONDUCTOR LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING SAME, AND OPTICAL MODULE - A semiconductor light emitting device capable of realizing a long life, and a method of manufacturing the same. The impurity concentration of hydrogen in the active layer is 3×10 | 01-14-2010 |
20100019255 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - There is provided a semiconductor light-emitting device capable of an attempt to further decrease a leakage current in a current-blocking layer and including (A) a light-emitting portion ( | 01-28-2010 |
20100047947 | Semiconductor light-emitting element, fabrication method thereof, convex part formed on backing, and convex part formation method for backing - A convex part formation method of forming a convex part in parallel with a <110> direction of a backing on the backing having a {100} face as the top surface thereof, includes: (a) forming a mask layer in parallel with the <110> direction on the backing; (b) etch the backing so as to form a convex-part upper layer whose sectional shape on a cutting plane corresponding to a {110} face is an isosceles trapezoid, the base of which is longer than the upper side thereof, and the side surface of which has an inclination of θ | 02-25-2010 |
20100177799 | SURFACE LIGHT EMITTING SEMICONDUCTOR LASER ELEMENT - A surface light emitting semiconductor laser element, comprises a substrate, a lower reflector including a semiconductor multi-layer disposed on the substrate, an active layer disposed on the lower reflector, an upper reflector including a semiconductor multi-layer disposed on the active layer, a compound semiconductor layer having a first opening for exposing the upper reflector and extending over the upper reflector, and a metal film having a second opening for exposing the upper reflector disposed inside of the first opening and extending over the compound semiconductor layer, wherein the metal film and the compound semiconductor layer constitute a complex refractive index distribution structure where a complex refractive index is changed from the center of the second opening towards the outside. A method of emitting laser light in a single-peak transverse mode is also provided. | 07-15-2010 |
20110212559 | LIGHT-EMITTING DIODE AND METHOD FOR MANUFACTURING SAME, INTEGRATED LIGHT-EMITTING DIODE AND METHOD FOR MANUFACTURING SAME, METHOD FOR GROWING A NITRIDE-BASED III-V GROUP COMPOUND SEMICONDUCTOR, SUBSTRATE FOR GROWING A NITRIDE-BASED III-V GROUP COMPOUND SEMICONDUCTOR, LIGHT SOURCE CELL UNIT, LIGHT-EMITTING DIODE BACKLIGHT, LIGHT-EMITTING DIODE ILLUMINATING DEVICE, LIGHT-EMITTING DIODE DISPLAY AND ELECTRONIC INSTRUMENT, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a light-emitting diode, which includes the steps of: providing a substrate having a plurality of protruded portions on one main surface thereof wherein the protruded portion is made of a material different in type from that of the substrate and growing a first nitride-based III-V Group compound semiconductor layer on each recess portion of the substrate through a state of making a triangle in section wherein a bottom surface of the recess portion becomes a base of the triangle; laterally growing a second nitride-based III-V Group compound semiconductor layer on the substrate from the first nitride-based III-V Group compound semiconductor layer; and successively growing, on the second nitride-based III-V Group compound semiconductor layer, a third nitride-based III-V Group compound semiconductor layer of a first conduction type, an active layer, and a fourth nitride-based III-V compound semiconductor layer of a second conduction type. | 09-01-2011 |
20110249975 | Communications system and communications lighting apparatus - An optical-information transmitting, lighting apparatus | 10-13-2011 |
20120009711 | SEMICONDUCTOR LIGHT EMITTING DEVICE, METHOD FOR MANUFACTURING SAME, AND METHOD FOR FORMING UNDERLYING LAYER - A method of making a semiconductor light emitting device including: (A) an underlying layer configured to be formed on a major surface of a substrate having a {100} plane as the major surface; (B) a light emitting part; and (C) a current block layer, wherein the underlying layer is composed of a III-V compound semiconductor and is formed on the major surface of the substrate by epitaxial growth, the underlying layer extends in parallel to a <110> direction of the substrate, a sectional shape of the underlying layer obtained when the underlying layer is cut along a virtual plane perpendicular to the <110> direction of the substrate is a trapezoid, and oblique surfaces of the underlying layer corresponding to two oblique sides of the trapezoid are {111}B planes, and the top surface of the underlying layer corresponding to an upper side of the trapezoid is a {100} plane. | 01-12-2012 |
20120122257 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT, FABRICATION METHOD THEREOF, CONVEX PART FORMED ON BACKING, AND CONVEX PART FORMATION METHOD FOR BACKING - A convex part formation method of forming a convex part in parallel with a < | 05-17-2012 |
20130105836 | LIGHT EMITTING ELEMENT, METHOD OF MANUFACTURING THE SAME, AND LIGHT EMITTING DEVICE | 05-02-2013 |
20140151836 | OPTICAL SEMICONDUCTOR APPARATUS - The optical semiconductor apparatus includes, on an n-GaAs substrate, a surface-emitting semiconductor laser device and a photodiode integrated on the periphery of the laser device with an isolation region interposed there between. The laser device is composed of an n-DBR mirror, an active region, and a p-DBR mirror and includes a columnar layered structure with its sidewall covered with an insulating film. The photodiode is formed on the substrate and has a circular layered structure wherein an i-GaAs layer and a p-GaAs layer surrounds the laser device with an isolating region interposed between the i-GaAs and p-GaAs layers and the laser device. The diameter of the photodiode is smaller than the diameter of the optical fiber core optically coupled with the optical semiconductor apparatus. Since the laser device and the photodiode are monolithically integrated, the devices do not require optical alignment, and thus, facilitate optical coupling with an optical fiber. | 06-05-2014 |
Patent application number | Description | Published |
20090034353 | Semiconductor memory device - A semiconductor memory device includes multiple mats arranged in an array, each including multiple memory cells storing a charge as information, and multiple power-supply lines, one end of each line of the lines being connected in common to an internal power supply which decreases or increases a voltage which is supplied from an external power source. The power-supply lines extend in a given direction in an area in which the multiple mats are formed and the other end of each line of the multiple power-supply lines is connected in common on the edge mat. | 02-05-2009 |
20100164607 | SEMICONDUCTOR DEVICE THAT CAN ADJUST SUBSTRATE VOLTAGE - To provide a semiconductor device including: a MOS transistor formed in a semiconductor substrate and have a threshold voltage to be adjusted, a replica transistor of the MOS transistor, a monitoring circuit monitors a gate/source voltage needed when the replica transistor flows a current having a given designed value, a negative voltage pumping circuit generates a substrate voltage of the MOS transistor, based on an output from the monitoring circuit, and a limiting circuit defines the operation of the negative voltage pumping circuit, regardless of a monitoring result of the monitoring circuit, in response to an excess of the substrate voltage with respect to a predetermined value. | 07-01-2010 |
20100244908 | Semiconductor device having a complementary field effect transistor - A semiconductor device prevents the ON current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a buffer circuit that generates a power-supply voltage of a CMOS; a first replica transistor that is a replica of a p-channel MOS transistor forming the CMOS, and is diode-connected; a second replica transistor that is a replica of an n-channel MOS transistor forming the CMOS, and is diode-connected; and a voltage controller that controls the voltage between the anode and cathode of the replica transistors so that the current value of the current flowing into the replica transistor becomes equal to a given target value. In this semiconductor device, the buffer circuit generates the power-supply voltage, with the target voltage being a voltage that is controlled by the voltage controller. | 09-30-2010 |
20100244936 | Semiconductor device having a complementary field effect transistor - A semiconductor device prevents the OFF current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a substrate voltage generating circuit that generates the substrate voltage of an n-channel MOS transistor forming a CMOS; a replica transistor that is a replica of the n-channel MOS transistor, and is diode-connected; and a voltage applier that applies a voltage of a predetermined voltage value between the anode and cathode of the replica transistor. In this semiconductor device, the substrate voltage of the replica transistor is the substrate voltage generated by the substrate voltage generating circuit. The substrate voltage generating circuit controls the substrate voltage to be generated so that the current value of the current flowing into the replica transistor becomes equal to a given target value. | 09-30-2010 |
20110026292 | Semiconductor device having hierarchically structured bit lines and system including the same - To include memory mats each including a sense amplifier that amplifies a potential difference between global bit lines, a plurality of hierarchy switches connected to the global bit lines, and a plurality of local bit lines connected to the global bit lines via the hierarchy switches, and a control circuit that activates the hierarchy switches. The control circuit activates hierarchy switches that are located in the same distance from the sense amplifier along the global bit lines. According to the present invention, because there is no difference in the parasitic CR distributed constant regardless of a local bit line to be selected, it is possible to prevent the sensing sensitivity from being degraded. | 02-03-2011 |
20110026348 | Semiconductor device having hierarchically structured bit lines and system including the same - A semiconductor device includes a global bit line, a dummy global bit line that is shorter than the global bit line, a sense amplifier that amplifies a potential difference between the global bit line and the dummy global bit line, a plurality of memory blocks each including a hierarchy switch and a local bit line that is connected to the global bit line via the hierarchy switch, a dummy memory block that includes a dummy hierarchy switch and a dummy local bit line that is connected to the dummy global bit line via the dummy hierarchy switch, and a control circuit that activates any one of hierarchy switches and the dummy hierarchy switch. With this configuration, it is possible to obtain the same memory capacity between a memory mat located at an edge and the other memory mat. | 02-03-2011 |
20120014199 | Semiconductor device that performs refresh operation - To include a refresh control circuit that generates a refresh execution signal in response to a refresh command supplied from outside, and a refresh address counter that performs a counting operation in response to activation of the refresh execution signal. The refresh control circuit generates the refresh execution signal 2 | 01-19-2012 |
20120300529 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME - A device includes a first sense amplifier array including a plurality of first sense amplifiers arranged in a first direction, each of the first sense amplifiers including first and second nodes, a plurality of first global bit lines extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers, and a plurality of second global bit lines extending in the second direction, the second global bit lines being arranged in the first direction on a right side of the first sense amplifier array so that the second global bit lines being operatively connected to the second node of the associated one of the first sense amplifiers. | 11-29-2012 |
20130058180 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME - A system includes a first circuit and a second circuit that are constituted by a semiconductor device, the second circuit controlling the first circuit. The first circuit includes an interface unit that performs communication with the second circuit, a plurality of sense amplifiers including a first sense amplifier, each of the plurality of sense amplifiers performing communication with the interface unit, a first global bit line, a dummy global bit line, a plurality of first memory blocks, each of the first memory blocks including a first hierarchy switch that is connected to the first global bit line, a dummy memory block including a dummy hierarchy switch that is connected to the dummy global bit line, and a first dummy local bit line connected to the dummy global bit line, and a control circuit that controls the first hierarchy switches and the dummy hierarchy switch. | 03-07-2013 |
20130070553 | SEMICONDUCTOR DEVICE HAVING CHARGE PUMP CIRCUIT AND INFORMATION PROCESSING APPARATUS INCLUDING THE SAME - Disclosed herein is a device that includes a capacitor, a pumping circuit supplying a pumping signal changed between first and second potential to a first electrode of the capacitor, and an output circuit precharging a second electrode of the capacitor to a third potential different from the first and second potentials. The second electrode of the capacitor is thereby changed from the third potential to a fourth potential higher than the third potential when the pumping signal is changed from the first potential to the second potential. | 03-21-2013 |
20130163353 | SEMICONDUCTOR DEVICE HAVING ODT FUNCTION - Disclosed herein is a device that includes: a data strobe terminal; a data terminal; a first output driver coupled to the data strobe terminal; a second output driver coupled to the data terminal; and a data control circuit configured to enable the first and second output drivers to function as termination resistors in different timings from each other. | 06-27-2013 |
20130242674 | SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR SYSTEM - The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized. | 09-19-2013 |
20130294135 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME - A system includes a first circuit, a second circuit including a logic circuit, and a bus interconnecting the first and second circuits to each other so that the second circuit accesses the first circuit to perform a data transfer therebetween, wherein the first circuit includes a first sense amplifier array including a plurality of first sense amplifiers that are arranged in a first direction, each of the first sense amplifiers including first and second nodes; and a plurality of first global bit lines each extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that each of the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers. | 11-07-2013 |
20130301370 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME - A device includes first memory blocks each including a first local bit line, first memory cells connected to the first local bit line and a first hierarchy switch connected between a first global bit line and the first local bit line, a dummy global bit line connected to the second node of a first sense amplifier, a dummy block including a dummy local bit line, dummy memory cells connected to the dummy local bit line and a dummy hierarchy switch connected between the dummy global bit line and the dummy local bit line, and a control circuit supplied with address information and configured to respond to the address information designating any one of the first memory blocks to turn ON each of the dummy hierarchy switch of the dummy block and the first hierarchy switch of one of the first memory blocks designated by the address information. | 11-14-2013 |
20140104919 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME - A method for sensing data in an open bit line dynamic random access memory includes activating a word line in a first memory block of a first memory mat to transfer charge from memory cells to first sub-bit lines, the first memory mat being between a second memory mat and a third memory mat, activating first hierarchy switches corresponding to the first memory block to transfer charge from first sub-bit lines to global bit lines of the first memory mat, and activating second hierarchy switches corresponding to a second memory block in a second memory mat, to connect sub-bit lines to global bit lines of the second memory mat, the first memory block and the second memory block being equidistant from a first sense amplifier array located between the first memory mat and the second memory mat. | 04-17-2014 |
20140177372 | SEMICONDUCTOR DEVICE THAT PERFORMS REFRESH OPERATION - A method for refreshing memory cells in a DRAM includes receiving a refresh command, receiving a refresh mode specifying signal in synchronization with the refresh command, refreshing a first quantity of memory cells when the refresh mode specifying signal has a first value, and refreshing a second quantity of memory cells, at least double the first quantity, when the refresh mode specifying signal has a second value. | 06-26-2014 |
20140300408 | SEMICONDUCTOR DEVICE HAVING A COMPLEMENTARY FIELD EFFECT TRANSISTOR - A method for controlling power supply current in a CMOS circuit, the method including applying a first predetermined voltage to a diode connected n-channel replica transistor, the n-channel replica transistor operating in weak inversion, applying a first substrate voltage to the substrate of the n-channel replica transistor so that the current flowing in the n-channel replica transistor equals a first predetermined target current, and applying the first substrate voltage to substrates of n-channel transistors in the CMOS circuit | 10-09-2014 |
Patent application number | Description | Published |
20080205209 | OPTICAL DISC DEVICE - The invention provides an optical disc device conducting highly accurate skew adjustment, avoiding an increase in the number of components, and achieving downsizing. This optical disc device includes: a guide shaft for supporting an optical pickup and guiding its movement; a chassis the guide shaft is attached to; a coil spring attached to the chassis for applying force to an end of the guide shaft; an adjustment screw for adjusting the force applied by the coil spring, provided opposite the coil spring with respect to the guide shaft; and a weight addition member attached to the chassis, wherein internal threads for engaging with the adjustment screw are formed in the weight addition member, and the axis of the adjustment screw engaged with the internal thread, the center of a cross section of the guide shaft perpendicular to its axis, and the axis of the coil spring are aligned along the same line. | 08-28-2008 |
20080209457 | DISC DEVICE - The invention provides a disc device capable of offering good SATA interface performance by optimizing the placement of the SATA connector relative to the control board, solving problems concerning noise or unnecessary radiation. | 08-28-2008 |
20090288107 | OPTICAL DISC APPARATUS - An optical disc apparatus including first to fourth disc guides. At the end of disc loading, the first one, in a fixed position, contacts a peripheral side face of the optical disc at a first point thereon to support the disc; the second one has a plane opposite to the peripheral side face which contacts the peripheral side face of the optical disc at a second point to support the disc while restrained from moving away from the side face; the third one contacts the peripheral side face of the optical disc at a third point to support the disc while biased by a spring; and the fourth one contacts the side face at a fourth point while biased by a spring to support the disc, and is restrained from moving against the resilience of the spring. The disc, supported by those disc guides, is chucked by a clamper. | 11-19-2009 |
20090293077 | OPTICAL DISK DEVICE - An optical disk device in which the thickness of the device is not increased, and interference between the bottom surface of an optical pickup unit (OPU) and a bottom case of the device is prevented upon emergency ejection of an optical disk without moving the optical pickup unit to an outermost peripheral position of the disk in the event of abnormality such as power shutdown during an operation in the optical disk device. A support mechanism having a coil spring is provided at shaft-holders in three of four positions of a guide main shaft and a guide sub shaft to support an OPU, to perform skew adjustment. In another position, a support mechanism having a plate spring is provided such that, upon emergency ejection, the interference between the bottom surface of the OPU and the bottom case is mitigated. | 11-26-2009 |